OV - exec - Function _ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system

	Function: _ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv	Module: exec	Source: NewTimer.cpp:39-81 [...]	Coverage: 0.04%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 90 - 97

--------------------------------------------------------------------------------

90:     short_buckets[level] = c1;

91:     if (level >= max_level - 1)

92:     {

93:       timer_max_level_exceeded = true;

94:     }

95:     else

96:     {

97:       level++;

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h: 92 - 93

--------------------------------------------------------------------------------

92:     if (CurrentTimerStack.size() > 0)

93:       current = CurrentTimerStack.back();

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 39 - 81

--------------------------------------------------------------------------------

39:   if (active)

[...]

53:     for (int level = omp_get_level(); level > 0; level--)

54:       if (omp_get_ancestor_thread_num(level) != 0)

55:         is_true_master = false;

56:     if (is_true_master)

57:     {

58:       if (manager)

59:       {

60:         // compute current_stack_key

61:         TimerType* parent = manager->current_timer();

62:         if (parent)

63:         {

64:           current_stack_key = parent->get_stack_key();

65:           current_stack_key.add_id(timer_id);

66:         }

67:         else

68:         {

69:           current_stack_key = StackKey();

70:           current_stack_key.add_id(timer_id);

71:         }

72:

73:         manager->push_timer(this);

74:       }

75:       start_time = CLOCK::now();

[...]

81: }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 919 - 919

--------------------------------------------------------------------------------

919:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

0x497e00 CMPB	$0,0x38(%RDI)

0x497e04 JE	497fb8

0x497e0a PUSH	%RBP

0x497e0b MOV	%RSP,%RBP

0x497e0e PUSH	%R15

0x497e10 PUSH	%R14

0x497e12 PUSH	%R13

0x497e14 PUSH	%R12

0x497e16 PUSH	%RBX

0x497e17 SUB	$0x18,%RSP

0x497e1b MOV	%RDI,%R15

0x497e1e CALL	405990 <omp_get_level@plt>

0x497e23 TEST	%EAX,%EAX

0x497e25 JLE	497f2c

0x497e2b MOV	%R15,-0x38(%RBP)

0x497e2f MOV	$0x1,%R14B

0x497e32 MOV	%EAX,-0x2c(%RBP)

0x497e35 CMP	$0x8,%EAX

0x497e38 JB	497edd

0x497e3e MOV	-0x2c(%RBP),%EAX

0x497e41 MOV	%EAX,%ECX

0x497e43 SHR	$0x3,%ECX

0x497e46 MOV	$0x1,%R14B

0x497e49 MOV	%EAX,%R15D

0x497e4c NOPL	(%RAX)

(1568) 0x497e50 MOV	%ECX,-0x30(%RBP)

(1568) 0x497e53 MOV	%R15D,%EDI

(1568) 0x497e56 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497e5b MOV	%EAX,%R12D

(1568) 0x497e5e LEA	-0x1(%R15),%EDI

(1568) 0x497e62 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497e67 MOV	%EAX,%R13D

(1568) 0x497e6a OR	%R12D,%R13D

(1568) 0x497e6d LEA	-0x2(%R15),%EDI

(1568) 0x497e71 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497e76 MOV	%EAX,%R12D

(1568) 0x497e79 LEA	-0x3(%R15),%EDI

(1568) 0x497e7d CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497e82 MOV	%EAX,%EBX

(1568) 0x497e84 OR	%R12D,%EBX

(1568) 0x497e87 OR	%R13D,%EBX

(1568) 0x497e8a LEA	-0x4(%R15),%EDI

(1568) 0x497e8e CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497e93 MOV	%EAX,%R12D

(1568) 0x497e96 LEA	-0x5(%R15),%EDI

(1568) 0x497e9a CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497e9f MOV	%EAX,%R13D

(1568) 0x497ea2 OR	%R12D,%R13D

(1568) 0x497ea5 OR	%EBX,%R13D

(1568) 0x497ea8 LEA	-0x6(%R15),%EDI

(1568) 0x497eac CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497eb1 MOV	%EAX,%EBX

(1568) 0x497eb3 LEA	-0x7(%R15),%EDI

(1568) 0x497eb7 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1568) 0x497ebc MOV	-0x30(%RBP),%ECX

(1568) 0x497ebf OR	%EBX,%EAX

(1568) 0x497ec1 MOVZX	%R14B,%R14D

(1568) 0x497ec5 OR	%R13D,%EAX

(1568) 0x497ec8 MOV	$0,%EAX

(1568) 0x497ecd CMOVNE	%EAX,%R14D

(1568) 0x497ed1 ADD	$-0x8,%R15D

(1568) 0x497ed5 DEC	%ECX

(1568) 0x497ed7 JNE	497e50

0x497edd MOV	-0x2c(%RBP),%R12D

0x497ee1 MOV	%R12D,%EAX

0x497ee4 AND	$-0x8,%EAX

0x497ee7 SUB	%EAX,%R12D

0x497eea JBE	497f22

0x497eec XOR	%EBX,%EBX

0x497eee MOV	-0x38(%RBP),%R15

0x497ef2 NOPW	%CS:(%RAX,%RAX,1)

(1567) 0x497f00 MOV	%R12D,%EDI

(1567) 0x497f03 CALL	405370 <omp_get_ancestor_thread_num@plt>

(1567) 0x497f08 TEST	%EAX,%EAX

(1567) 0x497f0a MOVZX	%R14B,%R14D

(1567) 0x497f0e CMOVNE	%EBX,%R14D

(1567) 0x497f12 DEC	%R12D

(1567) 0x497f15 JNE	497f00

0x497f17 TEST	$0x1,%R14B

0x497f1b JNE	497f2c

0x497f1d JMP	497faa

0x497f22 MOV	-0x38(%RBP),%R15

0x497f26 TEST	$0x1,%R14B

0x497f2a JE	497faa

0x497f2c MOV	0x48(%R15),%RAX

0x497f30 TEST	%RAX,%RAX

0x497f33 JE	497fa2

0x497f35 MOV	0x48(%RAX),%RCX

0x497f39 CMP	0x40(%RAX),%RCX

0x497f3d JE	497f75

0x497f3f MOV	-0x8(%RCX),%RAX

0x497f43 TEST	%RAX,%RAX

0x497f46 JE	497f75

0x497f48 MOVUPS	0x50(%RAX),%XMM0

0x497f4c MOVUPS	%XMM0,0x50(%R15)

0x497f51 MOVSXD	0x60(%RAX),%RAX

0x497f55 MOV	%EAX,0x60(%R15)

0x497f59 MOVZX	0x40(%R15),%ECX

0x497f5e MOV	%CL,0x50(%R15,%RAX,1)

0x497f63 MOV	0x60(%R15),%EAX

0x497f67 CMP	$0xf,%EAX

0x497f6a JL	497f90

0x497f6c MOVB	$0x1,0x1124a4(%RIP)

0x497f73 JMP	497f96

0x497f75 XORPS	%XMM0,%XMM0

0x497f78 MOVUPS	%XMM0,0x50(%R15)

0x497f7d MOVZX	0x40(%R15),%EAX

0x497f82 MOV	%AL,0x50(%R15)

0x497f86 MOVL	$0x1,0x60(%R15)

0x497f8e JMP	497f96

0x497f90 INC	%EAX

0x497f92 MOV	%EAX,0x60(%R15)

0x497f96 MOV	0x48(%R15),%RDI

0x497f9a MOV	%R15,%RSI

0x497f9d CALL	49dc90 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE10push_timerEPS5_>

0x497fa2 CALL	405a80 <_ZNSt6chrono3_V212system_clock3nowEv@plt>

0x497fa7 MOV	%RAX,(%R15)

0x497faa ADD	$0x18,%RSP

0x497fae POP	%RBX

0x497faf POP	%R12

0x497fb1 POP	%R13

0x497fb3 POP	%R14

0x497fb5 POP	%R15

0x497fb7 POP	%RBP

0x497fb8 RET

0x497fb9 NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	NewTimer.cpp:39-81
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:90-97
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:39,53-75,81
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 5.00 cycles (2.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 13.50 to 1.42 cycles (9.53x speedup).

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE10push_timerEPS5_: 1 occurrences
_ZNSt6chrono3_V212system_clock3nowEv@plt: 1 occurrences
omp_get_level@plt: 1 occurrences

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 91 bytes. The binary function is storing 67 bytes.

General properties

nb instructions	81
nb uops	81
loop length	284
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	8.50	6.75	6.75	6.50	8.50	9.67	9.67	9.67	0.00	0.00	0.00	0.00	1.00	1.00
cycles	8.50	6.75	6.75	6.50	8.50	9.67	9.67	9.67	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	9.67
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	18%
load	25%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	7%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.96 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 13.50 to 9.67 cycles (1.40x speedup).

ASM code

In the binary file, the address of the function is: 497e00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
CMPB $0,0x38(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 497fb8 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405990 <omp_get_level@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 497f2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 497edd <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xdd>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%ECX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x2c(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB %EAX,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JBE 497f22 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x122>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 497f2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 497faa <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1aa>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 497faa <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1aa>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x48(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 497fa2 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1a2>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x48(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP 0x40(%RAX),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 497f75 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x175>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x8(%RCX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 497f75 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x175>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOVUPS 0x50(%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,0x50(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVSXD 0x60(%RAX),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOV %EAX,0x60(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVZX 0x40(%R15),%ECX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOV %CL,0x50(%R15,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x60(%R15),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP $0xf,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JL 497f90 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x190>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOVB $0x1,0x1124a4(%RIP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
JMP 497f96 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x196>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x50(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVZX 0x40(%R15),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOV %AL,0x50(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVL $0x1,0x60(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
JMP 497f96 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x196>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EAX,0x60(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x48(%R15),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 49dc90 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE10push_timerEPS5_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
CALL 405a80 <_ZNSt6chrono3_V212system_clock3nowEv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	NewTimer.cpp:39-81
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:90-97
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/TimerManager.h:92-93
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:39,53-75,81
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:919

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 13.50 to 5.00 cycles (2.70x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

18% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

25% of SSE/AVX loads are used in vector version.
22% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
10% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE10push_timerEPS5_: 1 occurrences
_ZNSt6chrono3_V212system_clock3nowEv@plt: 1 occurrences
omp_get_level@plt: 1 occurrences

Vector unaligned load/store instructions

Detected 3 suboptimal vector unaligned load/store instructions.

Details

MOVUPS: 3 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 91 bytes. The binary function is storing 67 bytes.

General properties

nb instructions	81
nb uops	81
loop length	284
used x86 registers	11
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	2

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	13.50 cycles
front end	13.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	8.50	6.75	6.75	6.50	8.50	9.67	9.67	9.67	0.00	0.00	0.00	0.00	1.00	1.00
cycles	8.50	6.75	6.75	6.50	8.50	9.67	9.67	9.67	0.00	0.00	0.00	0.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	13.50
Dispatch	9.67
Overall L1	13.50

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	18%
load	25%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Vector efficiency ratios

INT

all	7%
load	6%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
other	8%

all	25%
load	25%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	10%
load	11%
store	11%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	6%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 13.50 cycles. At this rate:

7% of peak load performance is reached (6.74 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (4.96 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 497e00

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
CMPB $0,0x38(%RDI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 497fb8 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1b8>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RDI,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405990 <omp_get_level@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
TEST %EAX,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JLE 497f2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %R15,-0x38(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EAX,-0x2c(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 497edd <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0xdd>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x2c(%RBP),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %EAX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%ECX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
MOV $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EAX,%R15D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV -0x2c(%RBP),%R12D	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R12D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $-0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
SUB %EAX,%R12D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JBE 497f22 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x122>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
XOR %EBX,%EBX	1	0	0	0	0	0	0	0	0	0	0	0	0.25
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
TEST $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JNE 497f2c <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x12c>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
JMP 497faa <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1aa>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV -0x38(%RBP),%R15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST $0x1,%R14B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 497faa <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1aa>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x48(%R15),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 497fa2 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x1a2>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x48(%RAX),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP 0x40(%RAX),%RCX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
JE 497f75 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x175>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV -0x8(%RCX),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JE 497f75 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x175>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOVUPS 0x50(%RAX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.50
MOVUPS %XMM0,0x50(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVSXD 0x60(%RAX),%RAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOV %EAX,0x60(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVZX 0x40(%R15),%ECX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOV %CL,0x50(%R15,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x60(%R15),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP $0xf,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JL 497f90 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x190>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOVB $0x1,0x1124a4(%RIP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
JMP 497f96 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x196>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
XORPS %XMM0,%XMM0	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOVUPS %XMM0,0x50(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	4	1
MOVZX 0x40(%R15),%EAX	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	1	0.33
MOV %AL,0x50(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOVL $0x1,0x60(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
JMP 497f96 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv+0x196>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
INC %EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EAX,0x60(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV 0x48(%R15),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %R15,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 49dc90 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE10push_timerEPS5_>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
CALL 405a80 <_ZNSt6chrono3_V212system_clock3nowEv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,(%R15)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
ADD $0x18,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv–	0.04	0.08
○Loop 1567 - NewTimer.cpp:53-54 - exec	0	0.01
○Loop 1568 - NewTimer.cpp:39-54 - exec	0	0

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code