OV - exec - Function _ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5

	Function: _ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEER ...	Module: exec	Source: SPOSet.h:81-88 [...]	Coverage: 0.41%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 249

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

249:   inline const_pointer data() const { return X; }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 81 - 88

--------------------------------------------------------------------------------

81:   {

82:     assert(psi.size() == psiinv.size());

83:     for (int iat = 0; iat < VP.getTotalNum(); ++iat)

84:     {

85:       evaluate(VP, iat, psi);

86:       ratios[iat] = simd::dot(psi.data(), psiinv.data(), psi.size());

87:     }

88:   }

0x444190 PUSH	%RBP

0x444191 MOV	%RSP,%RBP

0x444194 PUSH	%R15

0x444196 PUSH	%R14

0x444198 PUSH	%R13

0x44419a PUSH	%R12

0x44419c PUSH	%RBX

0x44419d PUSH	%RAX

0x44419e MOV	%RCX,-0x30(%RBP)

0x4441a2 CMPQ	$0,0x260(%RSI)

0x4441aa JE	44428c

0x4441b0 MOV	%R8,%RBX

0x4441b3 MOV	%RDX,%R15

0x4441b6 MOV	%RSI,%R12

0x4441b9 MOV	%RDI,%R13

0x4441bc XOR	%R14D,%R14D

0x4441bf JMP	4441ee

0x4441c1 NOPW	%CS:(%RAX,%RAX,1)

(831) 0x4441d0 XORPD	%XMM0,%XMM0

(831) 0x4441d4 MOV	(%RBX),%RAX

(831) 0x4441d7 MOVSD	%XMM0,(%RAX,%R14,8)

(831) 0x4441dd INC	%R14

(831) 0x4441e0 CMP	%R14,0x260(%R12)

(831) 0x4441e8 JBE	44428c

(831) 0x4441ee MOV	(%R13),%RAX

(831) 0x4441f2 MOV	%R13,%RDI

(831) 0x4441f5 MOV	%R12,%RSI

(831) 0x4441f8 MOV	%R14D,%EDX

(831) 0x4441fb MOV	%R15,%RCX

(831) 0x4441fe CALLQ	0x10(%RAX)

(831) 0x444201 MOV	0x8(%R15),%RDX

(831) 0x444205 TEST	%EDX,%EDX

(831) 0x444207 JLE	4441d0

(831) 0x444209 MOV	0x18(%R15),%RAX

(831) 0x44420d MOV	-0x30(%RBP),%RCX

(831) 0x444211 MOV	0x18(%RCX),%RCX

(831) 0x444215 MOVSXD	%EDX,%RDX

(831) 0x444218 MOV	%RDX,%RSI

(831) 0x44421b AND	$-0x2,%RSI

(831) 0x44421f JE	444260

(831) 0x444221 XORPD	%XMM1,%XMM1

(831) 0x444225 XOR	%EDI,%EDI

(831) 0x444227 NOPW	(%RAX,%RAX,1)

  (833) 0x444230 MOVUPD	(%RCX,%RDI,8),%XMM0

  (833) 0x444235 MOVUPD	(%RAX,%RDI,8),%XMM2

  (833) 0x44423a MULPD	%XMM0,%XMM2

  (833) 0x44423e ADDPD	%XMM2,%XMM1

  (833) 0x444242 ADD	$0x2,%RDI

  (833) 0x444246 CMP	%RSI,%RDI

  (833) 0x444249 JL	444230

(831) 0x44424b MOVAPD	%XMM1,%XMM0

(831) 0x44424f UNPCKHPD	%XMM1,%XMM0

(831) 0x444253 ADDSD	%XMM1,%XMM0

(831) 0x444257 JMP	444270

0x444259 NOPL	(%RAX)

(831) 0x444260 XORPD	%XMM0,%XMM0

(831) 0x444264 XOR	%ESI,%ESI

(831) 0x444266 JMP	444279

0x444268 NOPL	(%RAX,%RAX,1)

  (832) 0x444270 CMP	%RSI,%RDX

  (832) 0x444273 JE	4441d4

  (832) 0x444279 MOVSD	(%RCX,%RSI,8),%XMM1

  (832) 0x44427e MULSD	(%RAX,%RSI,8),%XMM1

  (832) 0x444283 ADDSD	%XMM1,%XMM0

  (832) 0x444287 INC	%RSI

  (832) 0x44428a JMP	444270

0x44428c ADD	$0x8,%RSP

0x444290 POP	%RBX

0x444291 POP	%R12

0x444293 POP	%R13

0x444295 POP	%R14

0x444297 POP	%R15

0x444299 POP	%RBP

0x44429a RET

0x44429b NOPL	(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SPOSet.h:81-88
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:81-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.17 to 0.28 cycles (14.97x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	29
nb uops	25
loop length	99
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.17
Dispatch	1.50
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.17 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.17 to 1.50 cycles (2.78x speedup).

ASM code

In the binary file, the address of the function is: 444190

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMPQ $0,0x260(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 44428c <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xfc>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0.17
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0.25
JMP 4441ee <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x5e>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	SPOSet.h:81-88
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:81-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	29
nb uops	25
loop length	99
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.17
Dispatch	1.50
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.17 cycles. At this rate:

2% of peak load performance is reached (1.92 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
3% of peak store performance is reached (1.92 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 444190

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
CMPQ $0,0x260(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
JE 44428c <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0xfc>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0.17
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0.25
JMP 4441ee <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x5e>	1	0.50	0	0	0	0.50	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
NOPL (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E–	0.41	0.85
▼Loop 831 - inner_product.hpp:82-83 - exec–	0.04	0.08
○Loop 833 - inner_product.hpp:82-83 - exec	0.37	0.7
○Loop 832 - inner_product.hpp:82-83 - exec	0	0

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code