OV - exec - Function _intel_fast

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x5074e0 ENDBR64

0x5074e4 MOV	0xa3d65(%RIP),%RAX

0x5074eb TEST	%RAX,%RAX

0x5074ee JE	507500

0x5074f4 JMP	%RAX

0x5074f6 NOPW	%CS:(%RAX,%RAX,1)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your function is not vectorized.

Details

No SSE/AVX instruction: only general purpose registers are used and data elements are processed one at a time.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes.

General properties

nb instructions	5
nb uops	4
loop length	22
used x86 registers	1
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	0.67 cycles
front end	0.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.50	0.25	0.25	1.00	0.33	0.33	0.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	0.50	0.25	0.25	1.00	0.33	0.33	0.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.67
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5074e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
MOV 0xa3d65(%RIP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 507500 <__real_memset_impl_setup>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Source file and lines
Module	exec

gain
potential
hint
expert

Vectorization

Your function is not vectorized.

Details

No SSE/AVX instruction: only general purpose registers are used and data elements are processed one at a time.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes.

General properties

nb instructions	5
nb uops	4
loop length	22
used x86 registers	1
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	0.67 cycles
front end	0.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	0.50	0.25	0.25	1.00	0.33	0.33	0.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	0.50	0.25	0.25	1.00	0.33	0.33	0.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

NA

Cycles summary

Front-end	0.67
Dispatch	1.00
Overall L1	1.00

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 5074e0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
MOV 0xa3d65(%RIP),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %RAX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 507500 <__real_memset_impl_setup>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP %RAX	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Name	Coverage (%)	Time (s)
○_intel_fast_memset	0.01	0.02

Report Configuration

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code