OV - exec - Function __libm_exp

	Function: __libm_exp_z0	Module: exec	Source: :0-0	Coverage: 0.02%

  ***  This Panel is Intentionally Left Blank.  ***

It is due to a lack of debug symbols in the given object
(loop or function).

0x4fc7a0 ENDBR64

0x4fc7a4 VMOVQ	%XMM0,%RAX

0x4fc7a9 SHR	$0x30,%RAX

0x4fc7ad AND	$0x7fff,%EAX

0x4fc7b2 LEA	-0x4084(%RAX),%ECX

0x4fc7b8 CMP	$-0x404,%ECX

0x4fc7be JB	4fc85b

0x4fc7c4 VMOVSD	0x41f8c(%RIP),%XMM1

0x4fc7cc VMOVSD	0x41f7c(%RIP),%XMM2

0x4fc7d4 VFMADD213SD	{rn-sae},%XMM1,%XMM0,%XMM2

0x4fc7da VADDSD	0x41f7e(%RIP),%XMM2,%XMM1

0x4fc7e2 VMOVQ	%XMM2,%RAX

0x4fc7e7 LEA	(%RAX,%RAX,1),%ECX

0x4fc7ea AND	$0x7e,%ECX

0x4fc7ed VFMADD231SD	0x41f72(%RIP),%XMM1,%XMM0

0x4fc7f6 VFMADD231SD	0x41f71(%RIP),%XMM1,%XMM0

0x4fc7ff AND	$0x3ffc0,%EAX

0x4fc804 VMOVD	%EAX,%XMM1

0x4fc808 VPSLLQ	$0x2e,%XMM1,%XMM1

0x4fc80d LEA	0x46cdc(%RIP),%RAX

0x4fc814 VMOVQ	(%RAX,%RCX,8),%XMM2

0x4fc819 VPOR	%XMM2,%XMM1,%XMM1

0x4fc81d VMULSD	%XMM0,%XMM0,%XMM2

0x4fc821 VMOVSD	0x41f4f(%RIP),%XMM3

0x4fc829 VFMADD213SD	0x41f4e(%RIP),%XMM0,%XMM3

0x4fc832 VMOVSD	0x41f4e(%RIP),%XMM4

0x4fc83a VFMADD213SD	0x41f4d(%RIP),%XMM0,%XMM4

0x4fc843 VFMADD231SD	%XMM3,%XMM2,%XMM4

0x4fc848 OR	$0x1,%ECX

0x4fc84b VADDSD	(%RAX,%RCX,8),%XMM0,%XMM0

0x4fc850 VFMADD231SD	%XMM4,%XMM2,%XMM0

0x4fc855 VFMADD132SD	%XMM1,%XMM1,%XMM0

0x4fc85a RET

0x4fc85b CMP	$0x3c7f,%EAX

0x4fc860 JA	4fc86b

0x4fc862 VADDSD	0x198be(%RIP),%XMM0,%XMM0

0x4fc86a RET

0x4fc86b JMP	4f5cb0

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines
Module	exec

This function has 3 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside function: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 2.94 to 0.45 cycles (6.50x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

FMA

Detected 2.67 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Type of elements and instruction set

4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 6.6666666666667 FP arithmetical operations:

3.67: addition or subtraction (2 inside FMA instructions)
3: multiply (2 inside FMA instructions)

The binary function is loading 32 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	18
nb uops	17
loop length	95.67
used x86 registers	2
used mmx registers	0
used xmm registers	2.33
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	2.83 cycles
front end	2.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.08	2.08	1.92	1.92	1.33	1.33	1.33	1.33	1.50	1.50	0.83	0.83	0.67	0.67
cycles	2.08	2.08	1.92	1.92	1.33	1.33	1.33	1.33	1.50	1.50	0.83	0.83	0.67	0.67

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.83
Dispatch	2.67
Overall L1	2.94

Vectorization ratios

INT

all	11%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	13%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	3%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Vector efficiency ratios

INT

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 2.94 cycles. At this rate:

7% of peak load performance is reached (7.02 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.33 to 4.50 cycles (1.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 5.33 to 1.12 cycles (4.74x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 8 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Type of elements and instruction set

11 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 19 FP arithmetical operations:

10: addition or subtraction (8 inside FMA instructions)
9: multiply (8 inside FMA instructions)

The binary function is loading 88 bytes (11 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.22 FP operations per loaded or stored byte.

General properties

nb instructions	33
nb uops	32
loop length	187
used x86 registers	2
used mmx registers	0
used xmm registers	5
used ymm registers	0
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	5.33 cycles
front end	5.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.75	2.75	2.75	2.75	1.00	3.67	3.67	3.67	4.50	4.50	2.00	2.00	1.00	1.00
cycles	2.75	2.75	2.75	2.75	1.00	3.67	3.67	3.67	4.50	4.50	2.00	2.00	1.00	1.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.33
Dispatch	4.50
Overall L1	5.33

Vectorization ratios

INT

all	33%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	40%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	9%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

Vector efficiency ratios

INT

all	15%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	13%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	12%
add-sub	12%
fma	12%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	16%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.33 cycles. At this rate:

17% of peak load performance is reached (16.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 5.33 to 4.50 cycles (1.19x speedup).

ASM code

In the binary file, the address of the function is: 4fc7a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SHR $0x30,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND $0x7fff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x4084(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x404,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 4fc85b <__libm_exp_z0+0xbb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x41f8c(%RIP),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD 0x41f7c(%RIP),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD {rn-sae},%XMM1,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VADDSD 0x41f7e(%RIP),%XMM2,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVQ %XMM2,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
LEA (%RAX,%RAX,1),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x7e,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD 0x41f72(%RIP),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD 0x41f71(%RIP),%XMM1,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
AND $0x3ffc0,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVD %EAX,%XMM1	1	0	0	1	0	0	0	0	0	0	0	0	0	0	0	5	1
VPSLLQ $0x2e,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
LEA 0x46cdc(%RIP),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVQ (%RAX,%RCX,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPOR %XMM2,%XMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMULSD %XMM0,%XMM0,%XMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVSD 0x41f4f(%RIP),%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x41f4e(%RIP),%XMM0,%XMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VMOVSD 0x41f4e(%RIP),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD213SD 0x41f4d(%RIP),%XMM0,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VFMADD231SD %XMM3,%XMM2,%XMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
OR $0x1,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDSD (%RAX,%RCX,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VFMADD231SD %XMM4,%XMM2,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD132SD %XMM1,%XMM1,%XMM0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.75 to 1.00 cycles (1.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 1.75 to 0.12 cycles (14.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary function is loading 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	11
nb uops	10
loop length	52
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.67 cycles
front end	1.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	1.50	0.33	0.33	0.33	0.00	0.00	0.50	0.50	0.50	0.50
cycles	1.75	1.75	1.50	1.50	1.50	0.33	0.33	0.33	0.00	0.00	0.50	0.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.67
Dispatch	1.75
Overall L1	1.75

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	9%

all	12%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	10%
load	12%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.75 cycles. At this rate:

4% of peak load performance is reached (4.57 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4fc7a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SHR $0x30,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND $0x7fff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x4084(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x404,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 4fc85b <__libm_exp_z0+0xbb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3c7f,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JA 4fc86b <__libm_exp_z0+0xcb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VADDSD 0x198be(%RIP),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50

Source file and lines
Module	exec

hoisting them (moving them outside the function)
turning them into conditional moves, MIN or MAX

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 1.75 to 1.00 cycles (1.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 1.75 to 0.11 cycles (16.00x speedup).

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function does not load or store any data.

General properties

nb instructions	10
nb uops	9
loop length	48
used x86 registers	2
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	1.50 cycles
front end	1.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.75	1.75	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.50	0.50
cycles	1.75	1.75	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00	0.00	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.50
Dispatch	1.75
Overall L1	1.75

Vectorization ratios

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 1.75 cycles. At this rate:

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 4fc7a0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
ENDBR64
VMOVQ %XMM0,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
SHR $0x30,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
AND $0x7fff,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x4084(%RAX),%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $-0x404,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JB 4fc85b <__libm_exp_z0+0xbb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3c7f,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JA 4fc86b <__libm_exp_z0+0xcb>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
JMP 4f5cb0 <__libm_exp_e7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Name	Coverage (%)	Time (s)
○__libm_exp_z0	0.02	0.04

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code