OV - exec - Function _ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd

	Function: _ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd	Module: exec	Source: OhmmsVector.h:182-302 [...]	Coverage: 0.01%

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h: 111 - 145

--------------------------------------------------------------------------------

111: 	if (__builtin_expect(__n > this->_M_max_size(), false))

112: 	  {

113: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

114: 	    // 3190. allocator::allocate sometimes returns too little storage

115: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

116: 	      std::__throw_bad_array_new_length();

117: 	    std::__throw_bad_alloc();

[...]

127: 	return static_cast<_Tp*>(::operator new(__n * sizeof(_Tp)));

[...]

145: 	::operator delete(__p

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 182 - 302

--------------------------------------------------------------------------------

182:   {

183:     static_assert(std::is_same<value_type, typename Alloc::value_type>::value,

184:                   "Vector and Alloc data types must agree!");

185:     if (nLocal > nAllocated)

186:       throw std::runtime_error("Resize not allowed on Vector constructed by initialized memory.");

187:

188:     if (n > nAllocated)

[...]

195:       if (n > nLocal)

196:         qmc_allocator_traits<Alloc>::fill_n(X + nLocal, n - nLocal, val);

197:       nLocal = n;

198:     }

199:     return;

[...]

296:     if (nAllocated)

297:     {

298:       mAllocator.deallocate(X, nAllocated);

299:     }

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

302:     nAllocated = n;

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 923 - 924

--------------------------------------------------------------------------------

923:       for (; __first != __last; ++__first)

924: 	*__first = __tmp;

0x422730 PUSH	%RBP

0x422731 MOV	%RSP,%RBP

0x422734 PUSH	%R14

0x422736 PUSH	%RBX

0x422737 SUB	$0x10,%RSP

0x42273b MOV	0x8(%RDI),%RAX

0x42273f MOV	0x10(%RDI),%RCX

0x422743 CMP	%RCX,%RAX

0x422746 JA	422900

0x42274c MOV	%RSI,%RBX

0x42274f MOV	%RDI,%R14

0x422752 CMP	%RSI,%RCX

0x422755 JAE	42282b

0x42275b TEST	%RCX,%RCX

0x42275e MOVSD	%XMM0,-0x18(%RBP)

0x422763 JE	42276e

0x422765 MOV	0x18(%R14),%RDI

0x422769 CALL	4052f0 <_ZdlPv@plt>

0x42276e MOV	%RBX,%RAX

0x422771 SHR	$0x3c,%RAX

0x422775 JNE	4228f0

0x42277b LEA	(,%RBX,8),%RDI

0x422783 CALL	4056d0 <_Znwm@plt>

0x422788 MOVSD	-0x18(%RBP),%XMM0

0x42278d MOV	%RAX,0x18(%R14)

0x422791 MOV	%RBX,0x8(%R14)

0x422795 MOV	%RBX,0x10(%R14)

0x422799 CMP	$0x8,%RBX

0x42279d JB	4227e0

0x42279f MOV	%RBX,%RCX

0x4227a2 SHR	$0x3,%RCX

0x4227a6 LEA	0x38(%RAX),%RDX

0x4227aa NOPW	(%RAX,%RAX,1)

(305) 0x4227b0 MOVSD	%XMM0,-0x38(%RDX)

(305) 0x4227b5 MOVSD	%XMM0,-0x30(%RDX)

(305) 0x4227ba MOVSD	%XMM0,-0x28(%RDX)

(305) 0x4227bf MOVSD	%XMM0,-0x20(%RDX)

(305) 0x4227c4 MOVSD	%XMM0,-0x18(%RDX)

(305) 0x4227c9 MOVSD	%XMM0,-0x10(%RDX)

(305) 0x4227ce MOVSD	%XMM0,-0x8(%RDX)

(305) 0x4227d3 MOVSD	%XMM0,(%RDX)

(305) 0x4227d7 ADD	$0x40,%RDX

(305) 0x4227db DEC	%RCX

(305) 0x4227de JNE	4227b0

0x4227e0 MOV	%EBX,%ECX

0x4227e2 AND	$0x7,%ECX

0x4227e5 DEC	%RCX

0x4227e8 CMP	$0x6,%RCX

0x4227ec JA	4228e7

0x4227f2 AND	$-0x8,%RBX

0x4227f6 JMP	0x517b98(,%RCX,8)

0x4227fd MOVSD	%XMM0,0x30(%RAX,%RBX,8)

0x422803 MOVSD	%XMM0,0x28(%RAX,%RBX,8)

0x422809 MOVSD	%XMM0,0x20(%RAX,%RBX,8)

0x42280f MOVSD	%XMM0,0x18(%RAX,%RBX,8)

0x422815 MOVSD	%XMM0,0x10(%RAX,%RBX,8)

0x42281b MOVSD	%XMM0,0x8(%RAX,%RBX,8)

0x422821 MOVSD	%XMM0,(%RAX,%RBX,8)

0x422826 JMP	4228e7

0x42282b MOV	%RBX,%RDX

0x42282e SUB	%RAX,%RDX

0x422831 JBE	4228e3

0x422837 MOV	0x18(%R14),%RCX

0x42283b CMP	$0x8,%RDX

0x42283f JB	422880

0x422841 MOV	%RDX,%RSI

0x422844 SHR	$0x3,%RSI

0x422848 LEA	(%RCX,%RAX,8),%RDI

0x42284c ADD	$0x38,%RDI

(304) 0x422850 MOVSD	%XMM0,-0x38(%RDI)

(304) 0x422855 MOVSD	%XMM0,-0x30(%RDI)

(304) 0x42285a MOVSD	%XMM0,-0x28(%RDI)

(304) 0x42285f MOVSD	%XMM0,-0x20(%RDI)

(304) 0x422864 MOVSD	%XMM0,-0x18(%RDI)

(304) 0x422869 MOVSD	%XMM0,-0x10(%RDI)

(304) 0x42286e MOVSD	%XMM0,-0x8(%RDI)

(304) 0x422873 MOVSD	%XMM0,(%RDI)

(304) 0x422877 ADD	$0x40,%RDI

(304) 0x42287b DEC	%RSI

(304) 0x42287e JNE	422850

0x422880 MOV	%EDX,%ESI

0x422882 AND	$0x7,%ESI

0x422885 DEC	%RSI

0x422888 CMP	$0x6,%RSI

0x42288c JA	4228e3

0x42288e AND	$-0x8,%RDX

0x422892 JMP	0x517b60(,%RSI,8)

0x422899 ADD	%RDX,%RAX

0x42289c JMP	4228de

0x42289e ADD	%RDX,%RAX

0x4228a1 JMP	4228d8

0x4228a3 ADD	%RDX,%RAX

0x4228a6 JMP	4228d2

0x4228a8 ADD	%RDX,%RAX

0x4228ab JMP	4228cc

0x4228ad ADD	%RDX,%RAX

0x4228b0 JMP	4228c6

0x4228b2 ADD	%RDX,%RAX

0x4228b5 JMP	4228c0

0x4228b7 ADD	%RDX,%RAX

0x4228ba MOVSD	%XMM0,0x30(%RCX,%RAX,8)

0x4228c0 MOVSD	%XMM0,0x28(%RCX,%RAX,8)

0x4228c6 MOVSD	%XMM0,0x20(%RCX,%RAX,8)

0x4228cc MOVSD	%XMM0,0x18(%RCX,%RAX,8)

0x4228d2 MOVSD	%XMM0,0x10(%RCX,%RAX,8)

0x4228d8 MOVSD	%XMM0,0x8(%RCX,%RAX,8)

0x4228de MOVSD	%XMM0,(%RCX,%RAX,8)

0x4228e3 MOV	%RBX,0x8(%R14)

0x4228e7 ADD	$0x10,%RSP

0x4228eb POP	%RBX

0x4228ec POP	%R14

0x4228ee POP	%RBP

0x4228ef RET

0x4228f0 SHR	$0x3d,%RBX

0x4228f4 JE	4228fb

0x4228f6 CALL	405890 <_ZSt28__throw_bad_array_new_lengthv@plt>

0x4228fb CALL	4056c0 <_ZSt17__throw_bad_allocv@plt>

0x422900 MOV	$0x10,%EDI

0x422905 CALL	405860 <__cxa_allocate_exception@plt>

0x42290a MOV	%RAX,%RBX

0x42290d MOV	$0x519242,%ESI

0x422912 MOV	%RAX,%RDI

0x422915 CALL	405170 <_ZNSt13runtime_errorC1EPKc@plt>

0x42291a MOV	$0x596800,%ESI

0x42291f MOV	$0x405b50,%EDX

0x422924 MOV	%RBX,%RDI

0x422927 CALL	405360 <__cxa_throw@plt>

0x42292c MOV	%RAX,%R14

0x42292f MOV	%RBX,%RDI

0x422932 CALL	405ba0 <__cxa_free_exception@plt>

0x422937 MOV	%R14,%RDI

0x42293a CALL	4053b0 <_Unwind_Resume@plt>

0x42293f NOP

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 7.50 cycles (2.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 12% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 20.00 to 1.58 cycles (12.69x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_Unwind_Resume@plt: 1 occurrences
_ZNSt13runtime_errorC1EPKc@plt: 1 occurrences
_ZSt17__throw_bad_allocv@plt: 1 occurrences
_ZSt28__throw_bad_array_new_lengthv@plt: 1 occurrences
_ZdlPv@plt: 1 occurrences
_Znwm@plt: 1 occurrences
__cxa_allocate_exception@plt: 1 occurrences
__cxa_free_exception@plt: 1 occurrences
__cxa_throw@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	111
nb uops	120
loop length	432
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.00 cycles
front end	20.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.50	11.75	11.75	11.50	14.50	11.67	11.67	11.67	0.00	0.00	0.00	0.00	7.50	7.50
cycles	14.50	11.75	11.75	11.50	14.50	11.67	11.67	11.67	0.00	0.00	0.00	0.00	7.50	7.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.00
Dispatch	14.50
Overall L1	20.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 20.00 to 14.50 cycles (1.38x speedup).

ASM code

In the binary file, the address of the function is: 422730

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 422900 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 42282b <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xfb>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
TEST %RCX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JE 42276e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3e>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALL 4052f0 <_ZdlPv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3c,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
JNE 4228f0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
LEA (,%RBX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 4056d0 <_Znwm@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOVSD -0x18(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 4227e0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA 0x38(%RAX),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %EBX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x7,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x6,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 4228e7 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
AND $-0x8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 0x517b98(,%RCX,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1
MOVSD %XMM0,0x30(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x28(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x20(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x18(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x10(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x8(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JMP 4228e7 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JBE 4228e3 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 422880 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x150>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x38,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 4228e3 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
AND $-0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 0x517b60(,%RSI,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228de <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228d8 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228d2 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228cc <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x19c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228c6 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x196>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228c0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x190>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,0x30(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x28(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x20(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x18(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x10(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x8(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
SHR $0x3d,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
JE 4228fb <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1cb>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CALL 405890 <_ZSt28__throw_bad_array_new_lengthv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
CALL 4056c0 <_ZSt17__throw_bad_allocv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 405860 <__cxa_allocate_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x519242,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405170 <_ZNSt13runtime_errorC1EPKc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV $0x596800,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x405b50,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405360 <__cxa_throw@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405ba0 <__cxa_free_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4053b0 <_Unwind_Resume@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	OhmmsVector.h:182-302
Module	exec

The function is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/ext/new_allocator.h:111-117,127,145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:182-188,195-199,296-302
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:923-924

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 7.50 cycles (2.67x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_Unwind_Resume@plt: 1 occurrences
_ZNSt13runtime_errorC1EPKc@plt: 1 occurrences
_ZSt17__throw_bad_allocv@plt: 1 occurrences
_ZSt28__throw_bad_array_new_lengthv@plt: 1 occurrences
_ZdlPv@plt: 1 occurrences
_Znwm@plt: 1 occurrences
__cxa_allocate_exception@plt: 1 occurrences
__cxa_free_exception@plt: 1 occurrences
__cxa_throw@plt: 1 occurrences

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

JMP: 2 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	111
nb uops	120
loop length	432
used x86 registers	9
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	20.00 cycles
front end	20.00 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	14.50	11.75	11.75	11.50	14.50	11.67	11.67	11.67	0.00	0.00	0.00	0.00	7.50	7.50
cycles	14.50	11.75	11.75	11.50	14.50	11.67	11.67	11.67	0.00	0.00	0.00	0.00	7.50	7.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	20.00
Dispatch	14.50
Overall L1	20.00

Vectorization ratios

INT

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
other	11%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	11%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

2% of peak load performance is reached (2.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
11% of peak store performance is reached (7.60 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 422730

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.50
SUB $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x8(%RDI),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x10(%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP %RCX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 422900 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RSI,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CMP %RSI,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JAE 42282b <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xfb>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
TEST %RCX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,-0x18(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JE 42276e <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x3e>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CALL 4052f0 <_ZdlPv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RBX,%RAX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3c,%RAX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
JNE 4228f0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
LEA (,%RBX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 4056d0 <_Znwm@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOVSD -0x18(%RBP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV %RAX,0x18(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
MOV %RBX,0x10(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
CMP $0x8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 4227e0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0xb0>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RBX,%RCX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RCX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA 0x38(%RAX),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0.09
MOV %EBX,%ECX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x7,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x6,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 4228e7 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
AND $-0x8,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 0x517b98(,%RCX,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1
MOVSD %XMM0,0x30(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x28(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x20(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x18(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x10(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x8(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,(%RAX,%RBX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
JMP 4228e7 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
MOV %RBX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %RAX,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JBE 4228e3 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV 0x18(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
CMP $0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JB 422880 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x150>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
MOV %RDX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
LEA (%RCX,%RAX,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x38,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %EDX,%ESI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
DEC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JA 4228e3 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1b3>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
AND $-0x8,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 0x517b60(,%RSI,8)	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228de <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1ae>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228d8 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228d2 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1a2>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228cc <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x19c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228c6 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x196>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JMP 4228c0 <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x190>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1
ADD %RDX,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSD %XMM0,0x30(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x28(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x20(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x18(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x10(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,0x8(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOVSD %XMM0,(%RCX,%RAX,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV %RBX,0x8(%R14)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50
ADD $0x10,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50
SHR $0x3d,%RBX	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
JE 4228fb <_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd+0x1cb>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1
CALL 405890 <_ZSt28__throw_bad_array_new_lengthv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
CALL 4056c0 <_ZSt17__throw_bad_allocv@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV $0x10,%EDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CALL 405860 <__cxa_allocate_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV $0x519242,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405170 <_ZNSt13runtime_errorC1EPKc@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV $0x596800,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV $0x405b50,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405360 <__cxa_throw@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %RAX,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 405ba0 <__cxa_free_exception@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
MOV %R14,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0.17
CALL 4053b0 <_Unwind_Resume@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0	0	0.50
NOP	0	0	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus6VectorIdSaIdEE6resizeEmd–	0.01	0.02
○Loop 305 - stl_algobase.h:923-924 - exec	0.01	0.02
○Loop 304 - stl_algobase.h:923-924 - exec	0	0

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Cycles and memory resources usage

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