OV - exec - Function _ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi

	Function: _ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi	Module: exec	Source: SoaDistanceTableAAOMPTarget.h:430-445 [...]	Coverage: 1.36%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

244:         *(_base + M * i) = rhs[i];

[...]

263:   inline Accessor operator()(size_t i) { return Accessor(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 182 - 182

--------------------------------------------------------------------------------

182:       inverse[d] = -X[d];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 248

--------------------------------------------------------------------------------

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h: 430 - 445

--------------------------------------------------------------------------------

430:   {

431:     ScopedTimer local_timer(update_timer_);

432:     //update [0, iat) columns

433:     const int nupdate = iat;

434:     //copy row

435:     assert(nupdate <= temp_r_.size());

436:     std::copy_n(temp_r_.data(), nupdate, distances_[iat].data());

437:     for (int idim = 0; idim < D; ++idim)

438:       std::copy_n(temp_dr_.data(idim), nupdate, displacements_[iat].data(idim));

439:     //copy column

440:     for (size_t i = iat + 1; i < num_targets_; ++i)

441:     {

442:       distances_[i][iat]     = temp_r_[i];

443:       displacements_[i](iat) = -temp_dr_[i];

444:     }

445:   }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 429 - 431

--------------------------------------------------------------------------------

429: 	  const ptrdiff_t _Num = __last - __first;

430: 	  if (_Num)

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h: 751 - 751

--------------------------------------------------------------------------------

751:       if (__n2 <= 0)

0x4c2240 PUSH	%RBP

0x4c2241 MOV	%RSP,%RBP

0x4c2244 PUSH	%R15

0x4c2246 PUSH	%R14

0x4c2248 PUSH	%R13

0x4c224a PUSH	%R12

0x4c224c PUSH	%RBX

0x4c224d PUSH	%RAX

0x4c224e MOV	%ESI,%R15D

0x4c2251 MOV	%RDI,%R14

0x4c2254 MOV	0x288(%RDI),%R12

0x4c225b MOV	%R12,%RDI

0x4c225e CALL	497e00 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>

0x4c2263 MOVSXD	%R15D,%R13

0x4c2266 TEST	%R13D,%R13D

0x4c2269 JLE	4c2293

0x4c226b LEA	(,%R13,4),%RAX

0x4c2273 ADD	%R13,%RAX

0x4c2276 MOV	0x48(%R14),%RCX

0x4c227a MOV	0x90(%R14),%RSI

0x4c2281 MOV	0x18(%RCX,%RAX,8),%RDI

0x4c2286 LEA	(,%R13,8),%RDX

0x4c228e CALL	4050e0 <memmove@plt>

0x4c2293 TEST	%R15D,%R15D

0x4c2296 JLE	4c2320

0x4c229c MOV	%R12,-0x30(%RBP)

0x4c22a0 LEA	(,%R13,8),%R12

0x4c22a8 LEA	(%R12,%R12,4),%RBX

0x4c22ac MOV	0x60(%R14),%RAX

0x4c22b0 MOV	0xb8(%R14),%RSI

0x4c22b7 MOV	0x18(%RAX,%RBX,1),%RDI

0x4c22bc MOV	%R12,%RDX

0x4c22bf CALL	4050e0 <memmove@plt>

0x4c22c4 MOV	0x60(%R14),%RAX

0x4c22c8 MOV	0x8(%RAX,%RBX,1),%RDI

0x4c22cd SAL	$0x3,%RDI

0x4c22d1 ADD	0x18(%RAX,%RBX,1),%RDI

0x4c22d6 MOV	0xa8(%R14),%RSI

0x4c22dd SAL	$0x3,%RSI

0x4c22e1 ADD	0xb8(%R14),%RSI

0x4c22e8 MOV	%R12,%RDX

0x4c22eb CALL	4050e0 <memmove@plt>

0x4c22f0 MOV	0x60(%R14),%RAX

0x4c22f4 MOV	0x8(%RAX,%RBX,1),%RDI

0x4c22f9 SAL	$0x4,%RDI

0x4c22fd ADD	0x18(%RAX,%RBX,1),%RDI

0x4c2302 MOV	0xa8(%R14),%RSI

0x4c2309 SAL	$0x4,%RSI

0x4c230d ADD	0xb8(%R14),%RSI

0x4c2314 MOV	%R12,%RDX

0x4c2317 MOV	-0x30(%RBP),%R12

0x4c231b CALL	4050e0 <memmove@plt>

0x4c2320 INC	%R15D

0x4c2323 MOVSXD	%R15D,%RAX

0x4c2326 MOV	0x18(%R14),%RSI

0x4c232a CMP	%RAX,%RSI

0x4c232d JBE	4c23fe

0x4c2333 MOV	0x48(%R14),%RAX

0x4c2337 MOV	0x60(%R14),%RCX

0x4c233b MOV	0xb8(%R14),%R10

0x4c2342 MOVSXD	0xa8(%R14),%RDI

0x4c2349 MOV	%R13,%RDX

0x4c234c NOT	%RDX

0x4c234f ADD	%RSI,%RDX

0x4c2352 LEA	(,%RDI,2),%RSI

0x4c235a ADD	%R13,%RSI

0x4c235d LEA	(%R10,%RSI,8),%RSI

0x4c2361 ADD	$0x8,%RSI

0x4c2365 ADD	%R13,%RDI

0x4c2368 LEA	(%R10,%RDI,8),%RDI

0x4c236c ADD	$0x8,%RDI

0x4c2370 LEA	0x8(,%R13,4),%R8

0x4c2378 ADD	%R13,%R8

0x4c237b LEA	0x8(,%R13,8),%R9

0x4c2383 LEA	(%R10,%R13,8),%R10

0x4c2387 ADD	$0x8,%R10

0x4c238b ADD	0x90(%R14),%R9

0x4c2392 XOR	%R11D,%R11D

0x4c2395 MOVAPS	0x53d14(%RIP),%XMM0

0x4c239c NOPL	(%RAX)

(1983) 0x4c23a0 MOV	(%RAX,%R8,8),%RBX

(1983) 0x4c23a4 MOVSD	(%R9,%R11,8),%XMM1

(1983) 0x4c23aa MOVSD	%XMM1,(%RBX,%R13,8)

(1983) 0x4c23b0 MOVSD	(%R10,%R11,8),%XMM1

(1983) 0x4c23b6 XORPS	%XMM0,%XMM1

(1983) 0x4c23b9 MOVSD	(%RDI,%R11,8),%XMM2

(1983) 0x4c23bf XORPS	%XMM0,%XMM2

(1983) 0x4c23c2 MOVSD	(%RSI,%R11,8),%XMM3

(1983) 0x4c23c8 MOV	-0x10(%RCX,%R8,8),%RBX

(1983) 0x4c23cd MOV	(%RCX,%R8,8),%R14

(1983) 0x4c23d1 MOVLPS	%XMM1,(%R14,%R13,8)

(1983) 0x4c23d6 LEA	(%RBX,%R13,1),%R15

(1983) 0x4c23da MOVLPS	%XMM2,(%R14,%R15,8)

(1983) 0x4c23df XORPS	%XMM0,%XMM3

(1983) 0x4c23e2 LEA	(,%RBX,2),%RBX

(1983) 0x4c23ea ADD	%R13,%RBX

(1983) 0x4c23ed MOVLPS	%XMM3,(%R14,%RBX,8)

(1983) 0x4c23f2 INC	%R11

(1983) 0x4c23f5 ADD	$0x5,%R8

(1983) 0x4c23f9 CMP	%R11,%RDX

(1983) 0x4c23fc JNE	4c23a0

0x4c23fe MOV	%R12,%RDI

0x4c2401 CALL	497fd0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>

0x4c2406 ADD	$0x8,%RSP

0x4c240a POP	%RBX

0x4c240b POP	%R12

0x4c240d POP	%R13

0x4c240f POP	%R14

0x4c2411 POP	%R15

0x4c2413 POP	%RBP

0x4c2414 RET

0x4c2415 MOV	%RAX,%RDI

0x4c2418 CALL	410010 <__clang_call_terminate>

0x4c241d NOPL	(%RAX)

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SoaDistanceTableAAOMPTarget.h:430-445
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,244,263,271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:182
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:430-445
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:429-431
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:751

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 16.33 to 1.50 cycles (10.89x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 16.33 to 2.35 cycles (6.94x speedup).

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
__clang_call_terminate: 1 occurrences
memmove@plt: 4 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 204 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	93
nb uops	98
loop length	386
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.25	10.25	5.50	11.00	11.00	11.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.50	10.50	10.25	10.25	5.50	11.00	11.00	11.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.33
Dispatch	11.00
Overall L1	16.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	18%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

13% of peak load performance is reached (12.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.49 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 16.33 to 11.00 cycles (1.48x speedup).

ASM code

In the binary file, the address of the function is: 4c2240

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %ESI,%R15D	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
MOV 0x288(%RDI),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 497e00 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOVSXD %R15D,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
TEST %R13D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4c2293 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x53>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
LEA (,%R13,4),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x48(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x90(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RCX,%RAX,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (,%R13,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4c2320 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0xe0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA (,%R13,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R12,%R12,4),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x60(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0xb8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RAX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x60(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RAX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0x18(%RAX,%RBX,1),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV 0xa8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0xb8(%R14),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x60(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RAX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x4,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0x18(%RAX,%RBX,1),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV 0xa8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x4,%RSI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0xb8(%R14),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x30(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
INC %R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVSXD %R15D,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x18(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JBE 4c23fe <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x1be>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x48(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x60(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0xb8(%R14),%R10	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD 0xa8(%R14),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
NOT %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (,%RDI,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RSI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x8(,%R13,4),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x8(,%R13,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%R13,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD 0x90(%R14),%R9	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25
MOVAPS 0x53d14(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 497fd0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 410010 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

Source file and lines	SoaDistanceTableAAOMPTarget.h:430-445
Module	exec

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,244,263,271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:182
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:430-445
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:429-431
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:751

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

6% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

50% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
0% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv: 1 occurrences
_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv: 1 occurrences
__clang_call_terminate: 1 occurrences
memmove@plt: 4 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 204 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	93
nb uops	98
loop length	386
used x86 registers	16
used mmx registers	0
used xmm registers	1
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	16.33 cycles
front end	16.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	10.50	10.50	10.25	10.25	5.50	11.00	11.00	11.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	10.50	10.50	10.25	10.25	5.50	11.00	11.00	11.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	16.33
Dispatch	11.00
Overall L1	16.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	6%
load	50%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
other	10%

all	25%
load	25%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	18%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	10%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 16.33 cycles. At this rate:

13% of peak load performance is reached (12.49 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.49 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 4c2240

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	1	0.50
MOV %ESI,%R15D	1	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R14	1	0	0	0	0	0	0	0	0	0	0.17
MOV 0x288(%RDI),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 497e00 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOVSXD %R15D,%R13	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
TEST %R13D,%R13D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4c2293 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x53>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
LEA (,%R13,4),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x48(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x90(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RCX,%RAX,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
LEA (,%R13,8),%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
TEST %R15D,%R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 4c2320 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0xe0>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV %R12,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	4	0.50
LEA (,%R13,8),%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R12,%R12,4),%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x60(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0xb8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x18(%RAX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x60(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RAX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0x18(%RAX,%RBX,1),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV 0xa8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x3,%RSI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0xb8(%R14),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x60(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%RAX,%RBX,1),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x4,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0x18(%RAX,%RBX,1),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV 0xa8(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
SAL $0x4,%RSI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0xb8(%R14),%RSI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R12,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
MOV -0x30(%RBP),%R12	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 4050e0 <memmove@plt>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
INC %R15D	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOVSXD %R15D,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV 0x18(%R14),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CMP %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JBE 4c23fe <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi+0x1be>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x48(%R14),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x60(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0xb8(%R14),%R10	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD 0xa8(%R14),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV %R13,%RDX	1	0	0	0	0	0	0	0	0	0	0.17
NOT %RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %RSI,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (,%RDI,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RSI,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%RDI,8),%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x8,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x8(,%R13,4),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD %R13,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA 0x8(,%R13,8),%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
LEA (%R10,%R13,8),%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x8,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD 0x90(%R14),%R9	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0.25
MOVAPS 0x53d14(%RIP),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	3	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09
MOV %R12,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 497fd0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	1	0.33
RET	1	0.50	0	0	0	0.50	0	0	0	1	0.50
MOV %RAX,%RDI	1	0	0	0	0	0	0	0	0	0	0.17
CALL 410010 <__clang_call_terminate>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
NOPL (%RAX)	0	0	0	0	0	0	0	0	0	0	0.09

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE6updateEi–	1.36	2.84
○Loop 1983 - SoaDistanceTableAAOMPTarget.h:440-442 - exec	1.36	2.6

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code