OV - exec - Loop 984

	Loop Id: 984	Module: exec	Source: SPOSet.h:83-86 [...]	Coverage: 0.04%

0x495650 MOV	-0x68(%RBP),%RCX

0x495654 MOV	%R13,%RDI

0x495657 MOV	%R15D,%EDX

0x49565a MOV	%RBX,%RSI

0x49565d CALLQ	0x10(%R8)

0x495661 MOV	0x198(%R14),%R10

0x495668 MOV	0x420(%R14),%RDI

0x49566f MOV	0x1a8(%R14),%RCX

0x495676 TEST	%R10D,%R10D

0x495679 JLE	495910

0x49567f LEA	-0x1(%R10),%R8D

0x495683 CMP	$0x6,%R8D

0x495687 JBE	495916

0x49568d MOV	%R10D,%R9D

0x495690 XOR	%EDX,%EDX

0x495692 VXORPD	%XMM8,%XMM8,%XMM8

0x495697 SHR	$0x3,%R9D

0x49569b SAL	$0x6,%R9

0x49569f LEA	-0x40(%R9),%RSI

0x4956a3 SHR	$0x6,%RSI

0x4956a7 INC	%RSI

0x4956aa AND	$0x7,%ESI

0x4956ad JE	495761

0x4956b3 CMP	$0x1,%RSI

0x4956b7 JE	495746

0x4956bd CMP	$0x2,%RSI

0x4956c1 JE	495734

0x4956c3 CMP	$0x3,%RSI

0x4956c7 JE	495722

0x4956c9 CMP	$0x4,%RSI

0x4956cd JE	495710

0x4956cf CMP	$0x5,%RSI

0x4956d3 JE	4956fe

0x4956d5 CMP	$0x6,%RSI

0x4956d9 JE	4956ec

0x4956db MOV	$0x40,%EDX

0x4956e0 VMOVUPD	(%RCX),%ZMM5

0x4956e6 VFMADD231PD	(%RDI),%ZMM5,%ZMM8

0x4956ec VMOVUPD	(%RCX,%RDX,1),%ZMM4

0x4956f3 VFMADD231PD	(%RDI,%RDX,1),%ZMM4,%ZMM8

0x4956fa ADD	$0x40,%RDX

0x4956fe VMOVUPD	(%RCX,%RDX,1),%ZMM6

0x495705 VFMADD231PD	(%RDI,%RDX,1),%ZMM6,%ZMM8

0x49570c ADD	$0x40,%RDX

0x495710 VMOVUPD	(%RCX,%RDX,1),%ZMM7

0x495717 VFMADD231PD	(%RDI,%RDX,1),%ZMM7,%ZMM8

0x49571e ADD	$0x40,%RDX

0x495722 VMOVUPD	(%RCX,%RDX,1),%ZMM9

0x495729 VFMADD231PD	(%RDI,%RDX,1),%ZMM9,%ZMM8

0x495730 ADD	$0x40,%RDX

0x495734 VMOVUPD	(%RCX,%RDX,1),%ZMM10

0x49573b VFMADD231PD	(%RDI,%RDX,1),%ZMM10,%ZMM8

0x495742 ADD	$0x40,%RDX

0x495746 VMOVUPD	(%RCX,%RDX,1),%ZMM11

0x49574d VFMADD231PD	(%RDI,%RDX,1),%ZMM11,%ZMM8

0x495754 ADD	$0x40,%RDX

0x495758 CMP	%RDX,%R9

0x49575b JE	4957ef

  (985) 0x495761 VMOVUPD	(%RCX,%RDX,1),%ZMM12

  (985) 0x495768 VMOVUPD	0x40(%RCX,%RDX,1),%ZMM13

  (985) 0x495770 VMOVUPD	0x80(%RCX,%RDX,1),%ZMM14

  (985) 0x495778 VFMADD231PD	(%RDI,%RDX,1),%ZMM12,%ZMM8

  (985) 0x49577f VMOVUPD	0xc0(%RCX,%RDX,1),%ZMM15

  (985) 0x495787 VMOVUPD	0x100(%RCX,%RDX,1),%ZMM0

  (985) 0x49578f VMOVUPD	0x140(%RCX,%RDX,1),%ZMM1

  (985) 0x495797 VFMADD231PD	0x40(%RDI,%RDX,1),%ZMM13,%ZMM8

  (985) 0x49579f VMOVUPD	0x180(%RCX,%RDX,1),%ZMM2

  (985) 0x4957a7 VMOVUPD	0x1c0(%RCX,%RDX,1),%ZMM3

  (985) 0x4957af VFMADD231PD	0x80(%RDI,%RDX,1),%ZMM14,%ZMM8

  (985) 0x4957b7 VFMADD231PD	0xc0(%RDI,%RDX,1),%ZMM15,%ZMM8

  (985) 0x4957bf VFMADD231PD	0x100(%RDI,%RDX,1),%ZMM0,%ZMM8

  (985) 0x4957c7 VFMADD231PD	0x140(%RDI,%RDX,1),%ZMM1,%ZMM8

  (985) 0x4957cf VFMADD231PD	0x180(%RDI,%RDX,1),%ZMM2,%ZMM8

  (985) 0x4957d7 VFMADD231PD	0x1c0(%RDI,%RDX,1),%ZMM3,%ZMM8

  (985) 0x4957df ADD	$0x200,%RDX

  (985) 0x4957e6 CMP	%RDX,%R9

  (985) 0x4957e9 JNE	495761

0x4957ef VEXTRACTF64X4	$0x1,%ZMM8,%YMM5

0x4957f6 MOV	%R10D,%EAX

0x4957f9 VADDPD	%YMM8,%YMM5,%YMM4

0x4957fe AND	$-0x8,%EAX

0x495801 VADDPD	%YMM5,%YMM8,%YMM3

0x495805 MOV	%EAX,%R11D

0x495808 VEXTRACTF64X2	$0x1,%YMM4,%XMM6

0x49580f VADDPD	%XMM4,%XMM6,%XMM7

0x495813 VUNPCKHPD	%XMM7,%XMM7,%XMM9

0x495817 VADDPD	%XMM7,%XMM9,%XMM2

0x49581b TEST	$0x7,%R10B

0x49581f JE	4958d0

0x495825 MOV	%R10D,%R8D

0x495828 SUB	%EAX,%R8D

0x49582b LEA	-0x1(%R8),%R9D

0x49582f CMP	$0x2,%R9D

0x495833 JBE	495862

0x495835 VMOVUPD	(%RCX,%RAX,8),%YMM8

0x49583a VFMADD231PD	(%RDI,%RAX,8),%YMM8,%YMM3

0x495840 VEXTRACTF64X2	$0x1,%YMM3,%XMM10

0x495847 VADDPD	%XMM3,%XMM10,%XMM11

0x49584b VUNPCKHPD	%XMM11,%XMM11,%XMM12

0x495850 VADDPD	%XMM11,%XMM12,%XMM2

0x495855 TEST	$0x3,%R8B

0x495859 JE	4958d0

0x49585b AND	$-0x4,%R8D

0x49585f ADD	%R8D,%R11D

0x495862 MOVSXD	%R11D,%RSI

0x495865 LEA	0x1(%R11),%EDX

0x495869 VMOVSD	(%RCX,%RSI,8),%XMM13

0x49586e LEA	(,%RSI,8),%RAX

0x495876 VFMADD231SD	(%RDI,%RSI,8),%XMM13,%XMM2

0x49587c CMP	%EDX,%R10D

0x49587f JLE	4958d0

0x495881 ADD	$0x2,%R11D

0x495885 VMOVSD	0x8(%RDI,%RAX,1),%XMM14

0x49588b VFMADD231SD	0x8(%RCX,%RAX,1),%XMM14,%XMM2

0x495892 CMP	%R11D,%R10D

0x495895 JLE	4958d0

0x495897 VMOVSD	0x10(%RCX,%RAX,1),%XMM15

0x49589d VFMADD231SD	0x10(%RDI,%RAX,1),%XMM15,%XMM2

0x4958a4 VZEROUPPER

0x4958a7 MOV	(%R12),%R10

0x4958ab VMOVSD	%XMM2,(%R10,%R15,8)

0x4958b1 INC	%R15

0x4958b4 CMP	0x260(%RBX),%R15

0x4958bb JAE	4958e8

0x4958bd MOV	(%R13),%R8

0x4958c1 JMP	495650

0x4958d0 VZEROUPPER

0x4958d3 JMP	4958a7

0x495910 VXORPD	%XMM2,%XMM2,%XMM2

0x495914 JMP	4958a7

0x495916 XOR	%EAX,%EAX

0x495918 XOR	%R11D,%R11D

0x49591b VXORPD	%XMM3,%XMM3,%XMM3

0x49591f VXORPD	%XMM2,%XMM2,%XMM2

0x495923 JMP	495825

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 249

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

249:   inline const_pointer data() const { return X; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 83 - 86

--------------------------------------------------------------------------------

83:     for (int iat = 0; iat < VP.getTotalNum(); ++iat)

84:     {

85:       evaluate(VP, iat, psi);

86:       ratios[iat] = simd::dot(psi.data(), psiinv.data(), psi.size());

Path /

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.83
CQA cycles if no scalar integer	12.67
CQA cycles if FP arith vectorized	18.88
CQA cycles if fully vectorized	15.18
Front-end cycles	19.83
DIV/SQRT cycles	12.50
P0 cycles	12.50
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	10.50
P4 cycles	15.33
P5 cycles	15.33
P6 cycles	15.33
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	116.00
Nb uops	119.00
Nb loads	30.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	7.16
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	63.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.45
Bytes prefetched	0.00
Bytes loaded	1072.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	59.62
Vectorization ratio load	72.73
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	72.73
Vectorization ratio div_sqrt	NA
Vectorization ratio other	39.13
Vector-efficiency ratio all	41.95
Vector-efficiency ratio load	71.59
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	33.33
Vector-efficiency ratio fma	71.59
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.12

Metric	Value
CQA speedup if no scalar integer	1.57
CQA speedup if FP arith vectorized	1.05
CQA speedup if fully vectorized	1.31
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.29
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source	inner_product.hpp:82-83,OhmmsVector.h:178-178,OhmmsVector.h:248-249,SPOSet.h:83-86
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	19.83
CQA cycles if no scalar integer	12.67
CQA cycles if FP arith vectorized	18.88
CQA cycles if fully vectorized	15.18
Front-end cycles	19.83
DIV/SQRT cycles	12.50
P0 cycles	12.50
P1 cycles	12.25
P2 cycles	12.25
P3 cycles	10.50
P4 cycles	15.33
P5 cycles	15.33
P6 cycles	15.33
P7 cycles	9.00
P8 cycles	9.00
P9 cycles	5.50
P10 cycles	5.50
P11 cycles	0.50
P12 cycles	0.50
P13 cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	116.00
Nb uops	119.00
Nb loads	30.00
Nb stores	1.00
Nb stack references	1.00
FLOP/cycle	7.16
Nb FLOP add-sub	16.00
Nb FLOP mul	0.00
Nb FLOP fma	63.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	54.45
Bytes prefetched	0.00
Bytes loaded	1072.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	59.62
Vectorization ratio load	72.73
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	72.73
Vectorization ratio div_sqrt	NA
Vectorization ratio other	39.13
Vector-efficiency ratio all	41.95
Vector-efficiency ratio load	71.59
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	33.33
Vector-efficiency ratio fma	71.59
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	17.12

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source file and lines	SPOSet.h:83-86
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 128 paths individually, rerun with max-paths=128
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

Try to simplify control and/or increase the maximum number of paths per function/loop through the 'max-paths-nb' option.

This loop has 128 execution paths.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 19.83 to 12.67 cycles (1.57x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is partially vectorized. Only 41% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 19.83 to 15.18 cycles (1.31x speedup).

Details

59% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

3 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 4 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time). 3 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time). 7 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 142 FP arithmetical operations:

79: addition or subtraction (63 inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary loop is loading 1072 bytes (134 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	119
loop length	517
used x86 registers	15
used mmx registers	0
used xmm registers	13
used ymm registers	4
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.83 cycles
front end	19.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.25	12.25	10.50	10.67	10.67	10.67	5.50	5.50	5.50	5.50	0.50	0.50
cycles	12.50	12.50	12.25	12.25	10.50	15.33	15.33	15.33	9.00	9.00	5.50	5.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.83
Dispatch	15.33
Overall L1	19.83

Vectorization ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	76%
load	72%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	77%

INT+FP

all	59%
load	72%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	52%
load	71%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	41%
load	71%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.83 cycles. At this rate:

56% of peak load performance is reached (54.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 19.83 to 15.33 cycles (1.29x speedup).

ASM code

In the binary file, the address of the loop is: 495650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x68(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALLQ 0x10(%R8)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	0	0	0	0	2.20
MOV 0x198(%R14),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x420(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x1a8(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %R10D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 495910 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x530>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA -0x1(%R10),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x6,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 495916 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x536>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R10D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%R9D	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x40(%R9),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x6,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495761 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x381>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495746 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x366>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495734 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x354>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495722 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x342>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495710 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4956fe <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x31e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4956ec <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x30c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x40,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI),%ZMM5,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD (%RCX,%RDX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM4,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM6,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM9,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM10,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM11,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4957ef <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x40f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VEXTRACTF64X4 $0x1,%ZMM8,%YMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDPD %YMM8,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
AND $-0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDPD %YMM5,%YMM8,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VEXTRACTF64X2 $0x1,%YMM4,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM4,%XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM7,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM7,%XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST $0x7,%R10B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R10D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %EAX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1(%R8),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 495862 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x482>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD (%RCX,%RAX,8),%YMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VFMADD231PD (%RDI,%RAX,8),%YMM8,%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VEXTRACTF64X2 $0x1,%YMM3,%XMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM3,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM11,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM11,%XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST $0x3,%R8B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
AND $-0x4,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R8D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R11),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%RSI,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (,%RSI,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%RDI,%RSI,8),%XMM13,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
CMP %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
ADD $0x2,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8(%RDI,%RAX,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231SD 0x8(%RCX,%RAX,1),%XMM14,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
CMP %R11D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x10(%RCX,%RAX,1),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231SD 0x10(%RDI,%RAX,1),%XMM15,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
MOV (%R12),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM2,(%R10,%R15,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP 0x260(%RBX),%R15	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JAE 4958e8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x508>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JMP 495650 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
JMP 4958a7 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4c7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 4958a7 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4c7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 495825 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x445>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE
Source file and lines	SPOSet.h:83-86
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248-249
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:83-86

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Too many paths. If you really need to analyze all of the 128 paths individually, rerun with max-paths=128
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

59% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

72% of SSE/AVX loads are used in vector version.
0% of SSE/AVX stores are used in vector version.
72% of SSE/AVX fused multiply-add instructions are used in vector version.
39% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 63 FMA (fused multiply-add) operations.

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Vector unaligned load/store instructions

Detected 1 optimal vector unaligned load/store instructions.

Details

VMOVUPD: 1 occurrences

Workaround

Use vector aligned instructions:

align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 142 FP arithmetical operations:

79: addition or subtraction (63 inside FMA instructions)
63: multiply (all inside FMA instructions)

The binary loop is loading 1072 bytes (134 double precision FP elements). The binary loop is storing 8 bytes (1 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.13 FP operations per loaded or stored byte.

General properties

nb instructions	116
nb uops	119
loop length	517
used x86 registers	15
used mmx registers	0
used xmm registers	13
used ymm registers	4
used zmm registers	8
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	19.83 cycles
front end	19.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	12.50	12.50	12.25	12.25	10.50	10.67	10.67	10.67	5.50	5.50	5.50	5.50	0.50	0.50
cycles	12.50	12.50	12.25	12.25	10.50	15.33	15.33	15.33	9.00	9.00	5.50	5.50	0.50	0.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	19.83
Dispatch	15.33
Overall L1	19.83

Vectorization ratios

INT

all	14%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	14%

all	76%
load	72%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	77%

INT+FP

all	59%
load	72%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	72%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	39%

Vector efficiency ratios

INT

all	12%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	52%
load	71%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	25%

INT+FP

all	41%
load	71%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	33%
fma	71%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	17%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 19.83 cycles. At this rate:

56% of peak load performance is reached (54.05 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
0% of peak store performance is reached (0.40 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the loop is: 495650

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
MOV -0x68(%RBP),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %R13,%RDI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %R15D,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
CALLQ 0x10(%R8)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	0	0	0	0	0	0	2.20
MOV 0x198(%R14),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x420(%R14),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV 0x1a8(%R14),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
TEST %R10D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 495910 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x530>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
LEA -0x1(%R10),%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x6,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 495916 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x536>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R10D,%R9D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %EDX,%EDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VXORPD %XMM8,%XMM8,%XMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SHR $0x3,%R9D	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
SAL $0x6,%R9	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
LEA -0x40(%R9),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
SHR $0x6,%RSI	1	0	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50
INC %RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
AND $0x7,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495761 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x381>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x1,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495746 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x366>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x2,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495734 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x354>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x3,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495722 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x342>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x4,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 495710 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x330>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x5,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4956fe <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x31e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
CMP $0x6,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4956ec <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x30c>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV $0x40,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI),%ZMM5,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVUPD (%RCX,%RDX,1),%ZMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM4,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM6,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM7,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM9,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM10,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD (%RCX,%RDX,1),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD (%RDI,%RDX,1),%ZMM11,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
ADD $0x40,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %RDX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4957ef <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x40f>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VEXTRACTF64X4 $0x1,%ZMM8,%YMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.50
MOV %R10D,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDPD %YMM8,%YMM5,%YMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
AND $-0x8,%EAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VADDPD %YMM5,%YMM8,%YMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
MOV %EAX,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VEXTRACTF64X2 $0x1,%YMM4,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM4,%XMM6,%XMM7	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM7,%XMM7,%XMM9	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM7,%XMM9,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST $0x7,%R10B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R10D,%R8D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
SUB %EAX,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA -0x1(%R8),%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP $0x2,%R9D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JBE 495862 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x482>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVUPD (%RCX,%RAX,8),%YMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
VFMADD231PD (%RDI,%RAX,8),%YMM8,%YMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VEXTRACTF64X2 $0x1,%YMM3,%XMM10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	4	0.25
VADDPD %XMM3,%XMM10,%XMM11	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VUNPCKHPD %XMM11,%XMM11,%XMM12	1	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.33
VADDPD %XMM11,%XMM12,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
TEST $0x3,%R8B	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
AND $-0x4,%R8D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
ADD %R8D,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOVSXD %R11D,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x1(%R11),%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD (%RCX,%RSI,8),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
LEA (,%RSI,8),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VFMADD231SD (%RDI,%RSI,8),%XMM13,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
CMP %EDX,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
ADD $0x2,%R11D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x8(%RDI,%RAX,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231SD 0x8(%RCX,%RAX,1),%XMM14,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
CMP %R11D,%R10D	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JLE 4958d0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4f0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
VMOVSD 0x10(%RCX,%RAX,1),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231SD 0x10(%RDI,%RAX,1),%XMM15,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	0.50
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
MOV (%R12),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
VMOVSD %XMM2,(%R10,%R15,8)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
INC %R15	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP 0x260(%RBX),%R15	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
JAE 4958e8 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x508>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV (%R13),%R8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
JMP 495650 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x270>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
JMP 4958a7 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4c7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 4958a7 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x4c7>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
XOR %EAX,%EAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
XOR %R11D,%R11D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
VXORPD %XMM3,%XMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VXORPD %XMM2,%XMM2,%XMM2	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
JMP 495825 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x445>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

CALL instructions

Details

Vector unaligned load/store instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code