OV - exec - Loop 899

	Loop Id: 899	Module: exec	Source: einspline_spo_ref.hpp:223-227 [...]	Coverage: 0.39%

0x482960 VMOVSD	(%R9,%RAX,1),%XMM8    [10]

0x482966 VMOVSD	%XMM8,(%R8,%RAX,1)    [8]

0x48296c VMOVSD	(%R12,%RAX,1),%XMM10    [4]

0x482972 VMOVHPD	(%R13,%RAX,1),%XMM10,%XMM11    [5]

0x482979 VMOVSD	(%RCX,%RAX,1),%XMM9    [9]

0x48297e VMOVUPD	%XMM11,(%RDX)    [12]

0x482982 VMOVSD	%XMM9,0x10(%RDX)    [12]

0x482987 VMOVSD	(%R15,%RAX,1),%XMM12    [2]

0x48298d VMOVSD	%XMM12,(%R14,%RAX,1)    [1]

0x482993 VMOVSD	0x8(%R9,%RAX,1),%XMM13    [10]

0x48299a VMOVSD	%XMM13,0x8(%RAX,%R8,1)    [11]

0x4829a1 VMOVSD	0x8(%R12,%RAX,1),%XMM15    [4]

0x4829a8 VMOVHPD	0x8(%R13,%RAX,1),%XMM15,%XMM0    [5]

0x4829af VMOVSD	0x8(%RCX,%RAX,1),%XMM14    [9]

0x4829b5 VMOVSD	%XMM14,0x28(%RDX)    [12]

0x4829ba ADD	$0x60,%RDX

0x4829be VMOVUPD	%XMM0,-0x48(%RDX)    [6]

0x4829c3 VMOVSD	0x8(%R15,%RAX,1),%XMM4    [2]

0x4829ca VMOVSD	%XMM4,0x8(%RAX,%R14,1)    [3]

0x4829d1 VMOVSD	0x10(%R9,%RAX,1),%XMM5    [10]

0x4829d8 VMOVSD	%XMM5,0x10(%RAX,%R8,1)    [11]

0x4829df VMOVSD	0x10(%R12,%RAX,1),%XMM6    [4]

0x4829e6 VMOVHPD	0x10(%R13,%RAX,1),%XMM6,%XMM9    [5]

0x4829ed VMOVSD	0x10(%RCX,%RAX,1),%XMM8    [9]

0x4829f3 VMOVUPD	%XMM9,-0x30(%RDX)    [6]

0x4829f8 VMOVSD	%XMM8,-0x20(%RDX)    [6]

0x4829fd VMOVSD	0x10(%R15,%RAX,1),%XMM10    [2]

0x482a04 VMOVSD	%XMM10,0x10(%RAX,%R14,1)    [3]

0x482a0b VMOVSD	0x18(%R9,%RAX,1),%XMM11    [10]

0x482a12 VMOVSD	%XMM11,0x18(%RAX,%R8,1)    [11]

0x482a19 VMOVSD	0x18(%R12,%RAX,1),%XMM13    [4]

0x482a20 VMOVHPD	0x18(%R13,%RAX,1),%XMM13,%XMM14    [5]

0x482a27 VMOVSD	0x18(%RCX,%RAX,1),%XMM12    [9]

0x482a2d VMOVUPD	%XMM14,-0x18(%RDX)    [6]

0x482a32 VMOVSD	%XMM12,-0x8(%RDX)    [6]

0x482a37 VMOVSD	0x18(%R15,%RAX,1),%XMM15    [2]

0x482a3e ADD	$0x20,%RAX

0x482a42 VMOVSD	%XMM15,-0x8(%RAX,%R14,1)    [7]

0x482a49 CMP	%RAX,%RSI

0x482a4c JNE	482960

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227

--------------------------------------------------------------------------------

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:145-145,einspline_spo_ref.hpp:223-227
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	2.50
Front-end cycles	6.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	0.00
P8 cycles	1.33
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	20.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	160.00
Stride 0	0.00
Stride 1	5.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	13.89
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	15.63
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.80
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.50
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	TinyVector.h:145-145,einspline_spo_ref.hpp:223-227
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	12.00
CQA cycles if no scalar integer	12.00
CQA cycles if FP arith vectorized	12.00
CQA cycles if fully vectorized	2.50
Front-end cycles	6.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	12.00
P5 cycles	12.00
P6 cycles	12.00
P7 cycles	0.00
P8 cycles	1.33
P9 cycles	1.33
P10 cycles	1.33
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	20.00
Nb stores	16.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	26.67
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	160.00
Stride 0	0.00
Stride 1	5.00
Stride n	5.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	11.11
Vectorization ratio load	0.00
Vectorization ratio store	25.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	13.89
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	15.63
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 12.00 to 2.50 cycles (4.80x speedup).

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 160 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	40
nb uops	39
loop length	242
used x86 registers	10
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	0.00	1.33	1.33	1.33	8.00	8.00
cycles	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	0.00	1.33	1.33	1.33	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	13%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (13.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 482960

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%R9,%RAX,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM8,(%R8,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD (%R12,%RAX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%R13,%RAX,1),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RCX,%RAX,1),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVUPD %XMM11,(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM9,0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD (%R15,%RAX,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM12,(%R14,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x8(%R9,%RAX,1),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM13,0x8(%RAX,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x8(%R12,%RAX,1),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x8(%R13,%RAX,1),%XMM15,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x8(%RCX,%RAX,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM14,0x28(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
ADD $0x60,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM0,-0x48(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD 0x8(%R15,%RAX,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM4,0x8(%RAX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x10(%R9,%RAX,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM5,0x10(%RAX,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x10(%R12,%RAX,1),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x10(%R13,%RAX,1),%XMM6,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x10(%RCX,%RAX,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVUPD %XMM9,-0x30(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM8,-0x20(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x10(%R15,%RAX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM10,0x10(%RAX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x18(%R9,%RAX,1),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM11,0x18(%RAX,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x18(%R12,%RAX,1),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x18(%R13,%RAX,1),%XMM13,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x18(%RCX,%RAX,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVUPD %XMM14,-0x18(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM12,-0x8(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x18(%R15,%RAX,1),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
ADD $0x20,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM15,-0x8(%RAX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
CMP %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 482960 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x390>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	einspline_spo_ref.hpp:223-227
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Details

11% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

0% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 12.00 to 8.00 cycles (1.50x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 5 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 160 bytes. The binary loop is storing 160 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	40
nb uops	39
loop length	242
used x86 registers	10
used mmx registers	0
used xmm registers	12
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	0.00	1.33	1.33	1.33	8.00	8.00
cycles	0.75	0.75	0.50	0.50	0.50	12.00	12.00	12.00	0.00	1.33	1.33	1.33	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	12.00
Data deps.	1.00
Overall L1	12.00

Vectorization ratios

all	11%
load	0%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	13%
load	12%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 12.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (13.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 482960

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVSD (%R9,%RAX,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM8,(%R8,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD (%R12,%RAX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD (%R13,%RAX,1),%XMM10,%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RCX,%RAX,1),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVUPD %XMM11,(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM9,0x10(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD (%R15,%RAX,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM12,(%R14,%RAX,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x8(%R9,%RAX,1),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM13,0x8(%RAX,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x8(%R12,%RAX,1),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x8(%R13,%RAX,1),%XMM15,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x8(%RCX,%RAX,1),%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM14,0x28(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
ADD $0x60,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVUPD %XMM0,-0x48(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD 0x8(%R15,%RAX,1),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM4,0x8(%RAX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x10(%R9,%RAX,1),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM5,0x10(%RAX,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x10(%R12,%RAX,1),%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x10(%R13,%RAX,1),%XMM6,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x10(%RCX,%RAX,1),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVUPD %XMM9,-0x30(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM8,-0x20(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x10(%R15,%RAX,1),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM10,0x10(%RAX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x18(%R9,%RAX,1),%XMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVSD %XMM11,0x18(%RAX,%R8,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x18(%R12,%RAX,1),%XMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVHPD 0x18(%R13,%RAX,1),%XMM13,%XMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.33	0.33	0.33	0	0	9	0.50
VMOVSD 0x18(%RCX,%RAX,1),%XMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
VMOVUPD %XMM14,-0x18(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	4	1
VMOVSD %XMM12,-0x8(%RDX)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
VMOVSD 0x18(%R15,%RAX,1),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	1	0.50
ADD $0x20,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD %XMM15,-0x8(%RAX,%R14,1)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0.50	0.50	1	1
CMP %RAX,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25
JNE 482960 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x390>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code