OV - exec - Loop 1244

0x4bef50 MOV	(%RSI,%R12,8),%RDI    [3]

0x4bef54 MOV	%RBX,%RSI

0x4bef57 MOV	(%RDI),%RCX    [2]

0x4bef5a CALLQ	0x10(%RCX)

0x4bef5d MOV	0x1e0(%RBX),%RSI    [1]

0x4bef64 MOV	0x1e8(%RBX),%RDI    [1]

0x4bef6b INC	%R12

0x4bef6e SUB	%RSI,%RDI

0x4bef71 SAR	$0x3,%RDI

0x4bef75 CMP	%RDI,%R12

0x4bef78 JB	4bef50

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp: 242 - 243

--------------------------------------------------------------------------------

242:   for (int i = 0; i < DistTables.size(); i++)

243:     DistTables[i]->evaluate(*this);

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h: 990 - 990

--------------------------------------------------------------------------------

990:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h: 199 - 199

--------------------------------------------------------------------------------

199:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus11ParticleSet6updateEb
Source	ParticleSet.cpp:242-243,stl_vector.h:990-990,unique_ptr.h:199-199
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.17
CQA cycles if no scalar integer	2.17
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	2.17
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	13.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.46
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	NA
CQA speedup if fully vectorized	NA
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks	micro-operation queue,
Function	_ZN11qmcplusplus11ParticleSet6updateEb
Source	ParticleSet.cpp:242-243,stl_vector.h:990-990,unique_ptr.h:199-199
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.17
CQA cycles if no scalar integer	2.17
CQA cycles if FP arith vectorized	NA
CQA cycles if fully vectorized	NA
Front-end cycles	2.17
DIV/SQRT cycles	1.00
P0 cycles	1.00
P1 cycles	1.00
P2 cycles	1.00
P3 cycles	1.00
P4 cycles	2.00
P5 cycles	2.00
P6 cycles	2.00
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	11.00
Nb uops	13.00
Nb loads	5.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.46
Bytes prefetched	0.00
Bytes loaded	40.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	1.00
Stride n	0.00
Stride unknown	1.00
Stride indirect	1.00
Vectorization ratio all	NA
Vectorization ratio load	NA
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	NA
Vector-efficiency ratio load	NA
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN11qmcplusplus11ParticleSet6updateEb
Source file and lines	stl_vector.h:990-990
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:242-243
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h:199

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No SSE/AVX instruction: only general purpose registers are used and data elements are processed one at a time.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	13
loop length	42
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.17
Dispatch	2.00
Data deps.	1.00
Overall L1	2.17

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.17 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.17 to 2.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 4bef50

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV (%RSI,%R12,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
MOV (%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALLQ 0x10(%RCX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
MOV 0x1e0(%RBX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x1e8(%RBX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SAR $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
CMP %RDI,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JB 4bef50 <_ZN11qmcplusplus11ParticleSet6updateEb+0x50>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Function	_ZN11qmcplusplus11ParticleSet6updateEb
Source file and lines	stl_vector.h:990-990
Module	exec

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:242-243
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/stl_vector.h:990
/cluster/comp/gcc/13.2.0/include/c++/13.2.0/bits/unique_ptr.h:199

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized.

Details

No SSE/AVX instruction: only general purpose registers are used and data elements are processed one at a time.

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 1 occurrence(s)
Irregular (variable stride) or indirect: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)
Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 40 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or by recompiling with -funroll-loops and/or -floop-unroll-and-jam. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma GCC unroll N

General properties

nb instructions	11
nb uops	13
loop length	42
used x86 registers	5
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.00	1.00	1.00	1.00	1.00	2.00	2.00	2.00	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.17
Dispatch	2.00
Data deps.	1.00
Overall L1	2.17

Vectorization ratios

No vectorizable/vectorized instructions

Vector efficiency ratios

No vectorizable/vectorized instructions

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.17 cycles. At this rate:

19% of peak load performance is reached (18.46 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 2.17 to 2.00 cycles (1.08x speedup).

ASM code

In the binary file, the address of the loop is: 4bef50

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOV (%RSI,%R12,8),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %RBX,%RSI	1	0	0	0	0	0	0	0	0	0	0.17
MOV (%RDI),%RCX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALLQ 0x10(%RCX)	4	0.50	0	0	0	0.50	0.67	0.67	0.67	0	2.20
MOV 0x1e0(%RBX),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x1e8(%RBX),%RDI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
INC %R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SUB %RSI,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
SAR $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
CMP %RDI,%R12	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JB 4bef50 <_ZN11qmcplusplus11ParticleSet6updateEb+0x50>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code