OV - exec - Loop 905 - libqmcwfs.so

	Loop Id: 905	Module: libqmcwfs.so	Source: inner_product.hpp:155-155 [...]	Coverage: 0.02%

0x4cef0 VMOVUPD	(%R9),%ZMM21    [1]

0x4cef6 VMOVUPD	0x40(%R9),%ZMM20    [1]

0x4cefd VMOVUPD	0x80(%R9),%ZMM25    [1]

0x4cf04 VMOVUPD	(%RAX,%R8,8),%ZMM24    [2]

0x4cf0b VMOVUPD	0x40(%RAX,%R8,8),%ZMM26    [2]

0x4cf13 VMOVAPD	%ZMM21,%ZMM22

0x4cf19 VPERMT2PD	%ZMM20,%ZMM6,%ZMM22

0x4cf1f VMOVAPD	%ZMM21,%ZMM23

0x4cf25 VPERMT2PD	%ZMM20,%ZMM8,%ZMM23

0x4cf2b VPERMT2PD	%ZMM21,%ZMM10,%ZMM20

0x4cf31 VPERMT2PD	%ZMM25,%ZMM7,%ZMM22

0x4cf37 VPERMT2PD	%ZMM25,%ZMM9,%ZMM23

0x4cf3d VPERMT2PD	%ZMM25,%ZMM12,%ZMM20

0x4cf43 VMOVUPD	0xc0(%R9),%ZMM25    [1]

0x4cf4a VFMADD231PD	%ZMM22,%ZMM24,%ZMM2

0x4cf50 VMOVUPD	0x100(%R9),%ZMM22    [1]

0x4cf57 VFMADD231PD	%ZMM20,%ZMM24,%ZMM16

0x4cf5d VFMADD231PD	%ZMM23,%ZMM24,%ZMM11

0x4cf63 VMOVUPD	0x140(%R9),%ZMM24    [1]

0x4cf6a VMOVAPD	%ZMM25,%ZMM20

0x4cf70 VMOVAPD	%ZMM25,%ZMM21

0x4cf76 VPERMT2PD	%ZMM22,%ZMM6,%ZMM20

0x4cf7c VPERMT2PD	%ZMM22,%ZMM8,%ZMM21

0x4cf82 VPERMT2PD	%ZMM25,%ZMM10,%ZMM22

0x4cf88 VMOVUPD	0x180(%R9),%ZMM25    [1]

0x4cf8f VPERMT2PD	%ZMM24,%ZMM7,%ZMM20

0x4cf95 VPERMT2PD	%ZMM24,%ZMM12,%ZMM22

0x4cf9b VPERMT2PD	%ZMM24,%ZMM9,%ZMM21

0x4cfa1 VMOVUPD	0x200(%R9),%ZMM24    [1]

0x4cfa8 VMOVAPD	%ZMM25,%ZMM23

0x4cfae VFMADD231PD	%ZMM20,%ZMM26,%ZMM3

0x4cfb4 VMOVUPD	0x1c0(%R9),%ZMM20    [1]

0x4cfbb VFMADD231PD	%ZMM22,%ZMM26,%ZMM17

0x4cfc1 VMOVAPD	%ZMM25,%ZMM22

0x4cfc7 VFMADD231PD	%ZMM21,%ZMM26,%ZMM13

0x4cfcd VPERMT2PD	%ZMM20,%ZMM6,%ZMM22

0x4cfd3 VPERMT2PD	%ZMM20,%ZMM8,%ZMM23

0x4cfd9 VPERMT2PD	%ZMM25,%ZMM10,%ZMM20

0x4cfdf VMOVUPD	0x80(%RAX,%R8,8),%ZMM25    [2]

0x4cfe7 VPERMT2PD	%ZMM24,%ZMM7,%ZMM22

0x4cfed VPERMT2PD	%ZMM24,%ZMM9,%ZMM23

0x4cff3 VPERMT2PD	%ZMM24,%ZMM12,%ZMM20

0x4cff9 VMOVUPD	0x240(%R9),%ZMM24    [1]

0x4d000 VFMADD231PD	%ZMM22,%ZMM25,%ZMM4

0x4d006 VMOVUPD	0x280(%R9),%ZMM22    [1]

0x4d00d VFMADD231PD	%ZMM20,%ZMM25,%ZMM18

0x4d013 VFMADD231PD	%ZMM23,%ZMM25,%ZMM14

0x4d019 VMOVUPD	0x2c0(%R9),%ZMM25    [1]

0x4d020 ADD	$0x300,%R9

0x4d027 VMOVAPD	%ZMM24,%ZMM20

0x4d02d VMOVAPD	%ZMM24,%ZMM21

0x4d033 VPERMT2PD	%ZMM22,%ZMM6,%ZMM20

0x4d039 VPERMT2PD	%ZMM22,%ZMM8,%ZMM21

0x4d03f VPERMT2PD	%ZMM24,%ZMM10,%ZMM22

0x4d045 VMOVUPD	0xc0(%RAX,%R8,8),%ZMM24    [2]

0x4d04d ADD	$0x20,%R8

0x4d051 VPERMT2PD	%ZMM25,%ZMM7,%ZMM20

0x4d057 VPERMT2PD	%ZMM25,%ZMM9,%ZMM21

0x4d05d VPERMT2PD	%ZMM25,%ZMM12,%ZMM22

0x4d063 VFMADD231PD	%ZMM20,%ZMM24,%ZMM5

0x4d069 VFMADD231PD	%ZMM21,%ZMM24,%ZMM15

0x4d06f VFMADD231PD	%ZMM22,%ZMM24,%ZMM19

0x4d075 CMP	%R8,%RSI

0x4d078 JNE	4cef0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 155

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	unrolled by 24
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	24
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	10.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	2.25
Bottlenecks	P8, P9, P10,
Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source	inner_product.hpp:155-155,OperatorTags.h:63-63,OperatorTags.h:94-94
Source loop unroll info	unrolled by 24
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	24
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	10.50
DIV/SQRT cycles	0.75
P0 cycles	0.75
P1 cycles	0.50
P2 cycles	0.50
P3 cycles	0.50
P4 cycles	10.67
P5 cycles	10.67
P6 cycles	10.67
P7 cycles	24.00
P8 cycles	24.00
P9 cycles	24.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	4
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	64.00
Nb uops	63.00
Nb loads	16.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	8.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	96.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	42.67
Bytes prefetched	0.00
Bytes loaded	1024.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	100.00
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	inner_product.hpp:155-155
Module	libqmcwfs.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

It is main loop of related source loop which is unrolled by 24 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 10.67 cycles (2.25x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	63
loop length	398
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	25
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	5.33	5.33	5.33	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.50
Dispatch	24.00
Data deps.	4.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4cef0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%R9),%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x40(%R9),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x80(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%RAX,%R8,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x40(%RAX,%R8,8),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM21,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM20,%ZMM6,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM21,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM20,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM21,%ZMM10,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM12,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0xc0(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM22,%ZMM24,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x100(%R9),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM20,%ZMM24,%ZMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM23,%ZMM24,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x140(%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM25,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM22,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x180(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM7,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM12,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM9,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x200(%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM25,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM20,%ZMM26,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x1c0(%R9),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM22,%ZMM26,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVAPD %ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM21,%ZMM26,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VPERMT2PD %ZMM20,%ZMM6,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM20,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM10,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x80(%RAX,%R8,8),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM12,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x240(%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM22,%ZMM25,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x280(%R9),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM20,%ZMM25,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM23,%ZMM25,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x2c0(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVAPD %ZMM24,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM24,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM22,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0xc0(%RAX,%R8,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VPERMT2PD %ZMM25,%ZMM7,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM9,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM12,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD231PD %ZMM20,%ZMM24,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM21,%ZMM24,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM22,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 4cef0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x2d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE
Source file and lines	inner_product.hpp:155-155
Module	libqmcwfs.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94

It is main loop of related source loop which is unrolled by 24 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 96 FMA (fused multiply-add) operations.

Type of elements and instruction set

12 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 192 FP arithmetical operations:

96: addition or subtraction (all inside FMA instructions)
96: multiply (all inside FMA instructions)

The binary loop is loading 1024 bytes (128 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.19 FP operations per loaded or stored byte.

General properties

nb instructions	64
nb uops	63
loop length	398
used x86 registers	4
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	25
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	10.50 cycles
front end	10.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.75	0.75	0.50	0.50	0.50	5.33	5.33	5.33	12.00	24.00	24.00	0.00	0.00	0.00
cycles	0.75	0.75	0.50	0.50	0.50	10.67	10.67	10.67	24.00	24.00	24.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	4.00

Cycles summary

Front-end	10.50
Dispatch	24.00
Data deps.	4.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Vector efficiency ratios

all	100%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

44% of peak load performance is reached (42.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 4cef0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	Latency	Recip. throughput
VMOVUPD (%R9),%ZMM21	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x40(%R9),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x80(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD (%RAX,%R8,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVUPD 0x40(%RAX,%R8,8),%ZMM26	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM21,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM20,%ZMM6,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVAPD %ZMM21,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM20,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM21,%ZMM10,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM12,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0xc0(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM22,%ZMM24,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x100(%R9),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM20,%ZMM24,%ZMM16	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM23,%ZMM24,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x140(%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM25,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM25,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM22,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x180(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM7,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM12,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM9,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x200(%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VMOVAPD %ZMM25,%ZMM23	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM20,%ZMM26,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x1c0(%R9),%ZMM20	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM22,%ZMM26,%ZMM17	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVAPD %ZMM25,%ZMM22	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD %ZMM21,%ZMM26,%ZMM13	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VPERMT2PD %ZMM20,%ZMM6,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM20,%ZMM8,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM10,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x80(%RAX,%R8,8),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VPERMT2PD %ZMM24,%ZMM7,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM9,%ZMM23	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM12,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0x240(%R9),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM22,%ZMM25,%ZMM4	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x280(%R9),%ZMM22	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
VFMADD231PD %ZMM20,%ZMM25,%ZMM18	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM23,%ZMM25,%ZMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VMOVUPD 0x2c0(%R9),%ZMM25	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x300,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VMOVAPD %ZMM24,%ZMM20	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VMOVAPD %ZMM24,%ZMM21	1	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VPERMT2PD %ZMM22,%ZMM6,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM22,%ZMM8,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM24,%ZMM10,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VMOVUPD 0xc0(%RAX,%R8,8),%ZMM24	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	3	1
ADD $0x20,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
VPERMT2PD %ZMM25,%ZMM7,%ZMM20	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM9,%ZMM21	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VPERMT2PD %ZMM25,%ZMM12,%ZMM22	1	0	0	0	0	0	0	0	0	0	1	1	5	1
VFMADD231PD %ZMM20,%ZMM24,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM21,%ZMM24,%ZMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
VFMADD231PD %ZMM22,%ZMM24,%ZMM19	1	0	0	0	0	0	0	0	0	0.50	0.50	0	4	1
CMP %R8,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
JNE 4cef0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x2d0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code