OV - exec - Loop 836 - libqmcwfs.so

	Loop Id: 836	Module: libqmcwfs.so	Source: einspline_spo_ref.hpp:223-227 [...]	Coverage: 0.46%

0x46890 MOV	0x310(%R12),%RDX    [2]

0x46898 LEA	(%RCX,%RCX,2),%RSI

0x4689c MOV	(%RDX,%RSI,8),%RDX    [3]

0x468a0 LEA	(,%RCX,8),%RSI

0x468a8 LEA	(%RSI,%RSI,4),%RSI

0x468ac VMOVSD	(%RDX,%R9,1),%XMM0    [10]

0x468b2 MOV	0x18(%R15),%RDX    [14]

0x468b6 VMOVSD	%XMM0,(%RDX,%RDI,8)    [13]

0x468bb MOV	0x328(%R12),%RDX    [2]

0x468c3 MOV	0x8(%RDX,%RSI,1),%R10    [9]

0x468c8 MOV	0x18(%RDX,%RSI,1),%RDX    [9]

0x468cd SAL	$0x20,%R10

0x468d1 VMOVSD	(%RDX,%R9,1),%XMM0    [15]

0x468d7 ADD	%R9,%RDX

0x468da MOV	%R10,%R11

0x468dd SAR	$0x1d,%R11

0x468e1 SAR	$0x1c,%R10

0x468e5 VMOVSD	(%R11,%RDX,1),%XMM1    [1]

0x468eb VMOVQ	(%R10,%RDX,1),%XMM2    [7]

0x468f1 MOV	0x18(%R14),%RDX    [4]

0x468f5 VMOVSD	%XMM0,-0x10(%RDX,%R8,8)    [11]

0x468fc VMOVSD	%XMM1,-0x8(%RDX,%R8,8)    [11]

0x46903 VMOVQ	%XMM2,(%RDX,%R8,8)    [11]

0x46909 MOV	0x340(%R12),%RDX    [2]

0x46911 MOV	0x18(%RDX,%RSI,1),%RDX    [6]

0x46916 VMOVSD	(%RDX,%R9,1),%XMM0    [8]

0x4691c MOV	0x18(%RBX),%RDX    [5]

0x46920 VMOVSD	%XMM0,(%RDX,%RDI,8)    [12]

0x46925 INC	%RDI

0x46928 MOV	0x40(%R12),%ESI    [2]

0x4692d MOV	0x8(%R12),%EDX    [2]

0x46932 MOV	%ESI,%R10D

0x46935 IMUL	%EAX,%R10D

0x46939 CMP	%R10D,%EDX

0x4693c CMOVL	%EDX,%R10D

0x46940 ADD	$0x3,%R8

0x46944 ADD	$0x8,%R9

0x46948 MOVSXD	%R10D,%R10

0x4694b CMP	%R10,%RDI

0x4694e JL	46890

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 144 - 145

--------------------------------------------------------------------------------

144:     for (int i = 0; i < D; ++i)

145:       X[i] = base[i * offset];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

--------------------------------------------------------------------------------

223:     return X[i];

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 235 - 235

--------------------------------------------------------------------------------

235:       if (__b < __a)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 223 - 227

--------------------------------------------------------------------------------

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

Path /

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,TinyVector.h:144-145,OhmmsVector.h:223-223,stl_vector.h:1046-1046,stl_algobase.h:235-235,einspline_spo_ref.hpp:223-227
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.33
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	7.33
CQA cycles if fully vectorized	1.54
Front-end cycles	6.50
DIV/SQRT cycles	3.75
P0 cycles	3.75
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	0.50
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	17.00
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.91
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	40.00
Stride 0	4.00
Stride 1	1.00
Stride n	2.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Metric	Value
CQA speedup if no scalar integer	2.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	4.76
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.13
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source	VectorSoAContainer.h:231-231,VectorSoAContainer.h:271-271,TinyVector.h:144-145,OhmmsVector.h:223-223,stl_vector.h:1046-1046,stl_algobase.h:235-235,einspline_spo_ref.hpp:223-227
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	7.33
CQA cycles if no scalar integer	3.67
CQA cycles if FP arith vectorized	7.33
CQA cycles if fully vectorized	1.54
Front-end cycles	6.50
DIV/SQRT cycles	3.75
P0 cycles	3.75
P1 cycles	3.50
P2 cycles	3.50
P3 cycles	0.50
P4 cycles	7.33
P5 cycles	7.33
P6 cycles	7.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	2.50
P12 cycles	2.50
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	40.00
Nb uops	39.00
Nb loads	17.00
Nb stores	5.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	22.91
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	40.00
Stride 0	4.00
Stride 1	1.00
Stride n	2.00
Stride unknown	4.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	11.93
Vector-efficiency ratio load	12.50
Vector-efficiency ratio store	12.50
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	6.25

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	einspline_spo_ref.hpp:223-227
Module	libqmcwfs.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.33 to 3.67 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 11% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 7.33 to 1.54 cycles (4.76x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.33 to 6.50 cycles (1.13x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 40 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	40
nb uops	39
loop length	196
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.75	3.75	3.50	3.50	0.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50
cycles	3.75	3.75	3.50	3.50	0.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	7.33
Data deps.	1.00
Overall L1	7.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.33 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46890

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV 0x310(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RCX,%RCX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RDX,%RSI,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RSI,4),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD (%RDX,%R9,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x328(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%RDX,%RSI,1),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RSI,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SAL $0x20,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VMOVSD (%RDX,%R9,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SAR $0x1c,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VMOVSD (%R11,%RDX,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVQ (%R10,%RDX,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,-0x10(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD %XMM1,-0x8(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVQ %XMM2,(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x340(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RSI,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD (%RDX,%R9,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x40(%R12),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%R12),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %ESI,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EAX,%R10D	1	0	1	0	0	0	0	0	0	0	0	3	1
CMP %R10D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMOVL %EDX,%R10D	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
ADD $0x3,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JL 46890 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1d70>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_
Source file and lines	einspline_spo_ref.hpp:223-227
Module	libqmcwfs.so

The loop is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,271
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:144-145
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:223-227

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 7.33 to 3.67 cycles (2.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 7.33 to 6.50 cycles (1.13x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

No data for this section

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant unknown stride: 4 occurrence(s)
Constant non-unit stride: 2 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 128 bytes. The binary loop is storing 40 bytes.

Unroll opportunity

Loop is data access bound.

Workaround

General properties

nb instructions	40
nb uops	39
loop length	196
used x86 registers	13
used mmx registers	0
used xmm registers	3
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	6.50 cycles
front end	6.50 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.75	3.75	3.50	3.50	0.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50
cycles	3.75	3.75	3.50	3.50	0.50	7.33	7.33	7.33	0.00	0.00	0.00	0.00	2.50	2.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.50
Dispatch	7.33
Data deps.	1.00
Overall L1	7.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	10%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	6%

all	12%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	11%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	6%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 7.33 cycles. At this rate:

18% of peak load performance is reached (17.45 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (5.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 46890

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP4	FP5	Latency	Recip. throughput
MOV 0x310(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (%RCX,%RCX,2),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV (%RDX,%RSI,8),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
LEA (,%RCX,8),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
LEA (%RSI,%RSI,4),%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
VMOVSD (%RDX,%R9,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R15),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x328(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%RDX,%RSI,1),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RSI,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
SAL $0x20,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VMOVSD (%RDX,%R9,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
ADD %R9,%RDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV %R10,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0.17
SAR $0x1d,%R11	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
SAR $0x1c,%R10	1	0	0.50	0.50	0	0	0	0	0	0	0	1	0.50
VMOVSD (%R11,%RDX,1),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
VMOVQ (%R10,%RDX,1),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%R14),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,-0x10(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVSD %XMM1,-0x8(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
VMOVQ %XMM2,(%RDX,%R8,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
MOV 0x340(%R12),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x18(%RDX,%RSI,1),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD (%RDX,%R9,1),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	1	0.50
MOV 0x18(%RBX),%RDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
VMOVSD %XMM0,(%RDX,%RDI,8)	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	1	1
INC %RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOV 0x40(%R12),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV 0x8(%R12),%EDX	1	0	0	0	0	0	0.33	0.33	0.33	0	0	3	0.33
MOV %ESI,%R10D	1	0	0	0	0	0	0	0	0	0	0	0	0.17
IMUL %EAX,%R10D	1	0	1	0	0	0	0	0	0	0	0	3	1
CMP %R10D,%EDX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMOVL %EDX,%R10D	1	0.50	0	0	0.50	0	0	0	0	0	0	1	0.50
ADD $0x3,%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
ADD $0x8,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
MOVSXD %R10D,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
CMP %R10,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	1	0.25
JL 46890 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x1d70>	1	0.50	0	0	0	0.50	0	0	0	0	0	1	0.50-1

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code