OV - exec - Loop 820 - libqmcwfs.so

	Loop Id: 820	Module: libqmcwfs.so	Source: einspline_spo_ref.hpp:183-187 [...]	Coverage: 0.01%

0x44ab0 MOVSXD	%EAX,%RCX

0x44ab3 ADD	$0x18,%RBX

0x44ab7 CMP	%RCX,%R14

0x44aba JGE	44b01

0x44abc MOV	0x40(%R13),%ECX    [1]

0x44ac0 MOV	0x8(%R13),%ESI    [1]

0x44ac4 MOV	%R14D,%EDX

0x44ac7 INC	%R14

0x44aca IMUL	%EAX,%EDX

0x44acd IMUL	%R14D,%ECX

0x44ad1 CMP	%ECX,%ESI

0x44ad3 CMOVL	%ESI,%ECX

0x44ad6 SUB	%EDX,%ECX

0x44ad8 JLE	44ab0

0x44ada MOV	0x310(%R13),%RAX    [1]

0x44ae1 MOVSXD	%EDX,%RDI

0x44ae4 MOV	%ECX,%EDX

0x44ae6 SAL	$0x3,%RDX

0x44aea SAL	$0x3,%RDI

0x44aee ADD	0x18(%R15),%RDI    [3]

0x44af2 MOV	(%RAX,%RBX,1),%RSI    [2]

0x44af6 CALL	4f010 <@plt_start@+0x670>

0x44afb MOV	0x30(%R13),%EAX    [1]

0x44aff JMP	44ab0

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1169

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

[...]

1169:       { return _M_data_ptr(this->_M_impl._M_start); }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h: 235 - 431

--------------------------------------------------------------------------------

235:       if (__b < __a)

[...]

429: 	  const ptrdiff_t _Num = __last - __first;

430: 	  if (_Num)

431: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h: 725 - 751

--------------------------------------------------------------------------------

725:     { return std::copy(__first, __first + __n, __result); }

[...]

751:       if (__n2 <= 0)

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 183 - 187

--------------------------------------------------------------------------------

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	11.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.08
Bottlenecks
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:235-235,stl_algobase.h:429-431,stl_algo.h:725-725,stl_algo.h:751-751,einspline_spo_ref.hpp:183-187
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.21
CQA cycles if no scalar integer	3.21
CQA cycles if FP arith vectorized	3.21
CQA cycles if fully vectorized	0.29
Front-end cycles	3.17
DIV/SQRT cycles	3.00
P0 cycles	3.00
P1 cycles	3.00
P2 cycles	3.00
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	1.50
P6 cycles	1.50
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	19.00
Nb uops	19.00
Nb loads	4.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	6.10
Bytes prefetched	0.00
Bytes loaded	22.00
Bytes stored	0.00
Stride 0	1.50
Stride 1	0.00
Stride n	0.50
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	9.24
Vector-efficiency ratio load	7.29
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	10.94
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.15

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	10.53
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.11
Bottlenecks	micro-operation queue,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:235-235,stl_algobase.h:429-431,stl_algo.h:725-725,stl_algo.h:751-751,einspline_spo_ref.hpp:183-187
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	4.17
CQA cycles if no scalar integer	4.17
CQA cycles if FP arith vectorized	4.17
CQA cycles if fully vectorized	0.40
Front-end cycles	4.17
DIV/SQRT cycles	3.75
P0 cycles	3.75
P1 cycles	3.75
P2 cycles	3.75
P3 cycles	2.00
P4 cycles	2.33
P5 cycles	2.33
P6 cycles	2.33
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	24.00
Nb uops	25.00
Nb loads	6.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	8.64
Bytes prefetched	0.00
Bytes loaded	36.00
Bytes stored	0.00
Stride 0	2.00
Stride 1	0.00
Stride n	1.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	0.00
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	8.48
Vector-efficiency ratio load	8.33
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	6.25
Vector-efficiency ratio add_sub	9.38
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	8.93

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	12.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.04
Bottlenecks	P0, P1, P2, P3,
Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source	stl_vector.h:1046-1046,stl_vector.h:1169-1169,stl_algobase.h:235-235,stl_algobase.h:429-431,stl_algo.h:725-725,stl_algo.h:751-751,einspline_spo_ref.hpp:183-187
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	2.25
CQA cycles if no scalar integer	2.25
CQA cycles if FP arith vectorized	2.25
CQA cycles if fully vectorized	0.19
Front-end cycles	2.17
DIV/SQRT cycles	2.25
P0 cycles	2.25
P1 cycles	2.25
P2 cycles	2.25
P3 cycles	1.00
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.67
P7 cycles	0.00
P8 cycles	0.00
P9 cycles	0.00
P10 cycles	0.00
P11 cycles	0.00
P12 cycles	0.00
P13 cycles	0.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	14.00
Nb uops	13.00
Nb loads	2.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	3.56
Bytes prefetched	0.00
Bytes loaded	8.00
Bytes stored	0.00
Stride 0	1.00
Stride 1	0.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	10.00
Vector-efficiency ratio load	6.25
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	12.50
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	9.38

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	einspline_spo_ref.hpp:183-187
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187

The related source loop is not unrolled or unrolled with no peel/tail loop.
The structure of this loop is probably <if then [else] end>.

The presence of multiple execution paths is typically the main/first bottleneck.
Try to simplify control inside loop: ideally, try to remove all conditional expressions, for example by (if applicable):

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 9% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.21 to 0.29 cycles (11.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

CALL instructions

Detected function call instructions.

Details

Calling (and then returning from) a function prevents many compiler optimizations (like vectorization), breaks control flow (which reduces pipeline performance) and executes extra instructions to save/restore the registers used inside it, which is very expensive (dozens of cycles). Consider to inline small functions.

unknown: 1 occurrences

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 22 bytes.

General properties

nb instructions	19
nb uops	19
loop length	61.50
used x86 registers	8
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.00	3.00	3.00	3.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.00	3.00	3.00	3.00	1.50	1.50	1.50	1.50	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	3.17
Dispatch	3.00
Data deps.	1.00
Overall L1	3.21

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	9%
load	7%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	10%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.21 cycles. At this rate:

6% of peak load performance is reached (6.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	einspline_spo_ref.hpp:183-187
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 8% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 4.17 to 0.40 cycles (10.53x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

CALL instructions

Detected function call instructions.

Details

unknown: 1 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Constant non-unit stride: 1 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 36 bytes.

Unroll opportunity

Loop is potentially data access bound.

Workaround

Unroll your loop if trip count is significantly higher than target unroll factor and if some data references are common to consecutive iterations. This can be done manually. Or with the unroll (resp. unroll_and_jam) directive on top of the inner (resp. surrounding) loop. You can enforce an unroll factor: #pragma unroll_and_jam N, unroll_and_jam(N), unroll N or unroll(N)

General properties

nb instructions	24
nb uops	25
loop length	81
used x86 registers	9
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.17 cycles
front end	4.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	3.75	3.75	3.75	3.75	2.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00
cycles	3.75	3.75	3.75	3.75	2.00	2.33	2.33	2.33	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	4.17
Dispatch	3.75
Data deps.	1.00
Overall L1	4.17

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	8%
load	8%
store	NA (no store vectorizable/vectorized instructions)
mul	6%
add-sub	9%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	8%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 4.17 cycles. At this rate:

8% of peak load performance is reached (8.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.17 to 3.75 cycles (1.11x speedup).

ASM code

In the binary file, the address of the loop is: 44abc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %RCX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JGE 44b01 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xcd1>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x40(%R13),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%R13),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0.17
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %EAX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %R14D,%ECX	1	0	1	0	0	0	0	0	0	3	1
CMP %ECX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %ESI,%ECX	1	0.50	0	0	0.50	0	0	0	0	1	0.50
SUB %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 44ab0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc80>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x310(%R13),%RAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOVSXD %EDX,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
MOV %ECX,%EDX	1	0	0	0	0	0	0	0	0	0	0.17
SAL $0x3,%RDX	1	0	0.50	0.50	0	0	0	0	0	1	0.50
SAL $0x3,%RDI	1	0	0.50	0.50	0	0	0	0	0	1	0.50
ADD 0x18(%R15),%RDI	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	1	0.33
MOV (%RAX,%RBX,1),%RSI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
CALL 4f010 <@plt_start@+0x670>	2	0.50	0	0	0	0.50	0.33	0.33	0.33	0	0.50
MOV 0x30(%R13),%EAX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
JMP 44ab0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc80>	1	0.50	0	0	0	0.50	0	0	0	0	1

Function	_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE
Source file and lines	einspline_spo_ref.hpp:183-187
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046,1169
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algobase.h:235,429-431
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_algo.h:725,751
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:183-187

hoisting them (moving them outside the loop)
turning them into conditional moves, MIN or MAX

Ex: if (x<0) x=0 => x = (x<0 ? 0 : x) (or MAX(0,x) after defining the corresponding macro)

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 10% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your loop, you can lower the cost of an iteration from 2.25 to 0.19 cycles (12.00x speedup).

Details

All SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This loop is probably writing/copying data or processing integer elements.

Matching between your loop (in the source code) and the binary loop

The binary loop does not contain any FP arithmetical operations. The binary loop is loading 8 bytes.

General properties

nb instructions	14
nb uops	13
loop length	42
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	2.17 cycles
front end	2.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	2.25	2.25	2.25	2.25	1.00	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	2.25	2.25	2.25	2.25	1.00	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	2.17
Dispatch	2.25
Data deps.	1.00
Overall L1	2.25

Vectorization ratios

all	0%
load	0%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

all	10%
load	6%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	12%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	9%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.25 cycles. At this rate:

3% of peak load performance is reached (3.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 44abc

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	Latency	Recip. throughput
MOVSXD %EAX,%RCX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
ADD $0x18,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMP %RCX,%R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JGE 44b01 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xcd1>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1
MOV 0x40(%R13),%ECX	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV 0x8(%R13),%ESI	1	0	0	0	0	0	0.33	0.33	0.33	3	0.33
MOV %R14D,%EDX	1	0	0	0	0	0	0	0	0	0	0.17
INC %R14	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
IMUL %EAX,%EDX	1	0	1	0	0	0	0	0	0	3	1
IMUL %R14D,%ECX	1	0	1	0	0	0	0	0	0	3	1
CMP %ECX,%ESI	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
CMOVL %ESI,%ECX	1	0.50	0	0	0.50	0	0	0	0	1	0.50
SUB %EDX,%ECX	1	0.25	0.25	0.25	0.25	0	0	0	0	1	0.25
JLE 44ab0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0xc80>	1	0.50	0	0	0	0.50	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

CALL instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Vectorization

Details

Workaround

Execution units bottlenecks

CALL instructions

Details

Slow data structures access

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Unroll opportunity

Workaround

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code