OV - exec - Loop 638 - libqmcwfs.so

	Loop Id: 638	Module: libqmcwfs.so	Source: TwoBodyJastrowRef.h:324-331	Coverage: 0.14%

0x3a8c0 VMOVUPD	(%RCX,%R11,8),%ZMM9    [4]

0x3a8c7 VMOVUPD	0x40(%RCX,%R11,8),%ZMM10    [4]

0x3a8cf VMOVUPD	0x80(%RCX,%R11,8),%ZMM11    [4]

0x3a8d7 VMOVUPD	0xc0(%RCX,%R11,8),%ZMM12    [4]

0x3a8df VMOVUPD	(%RSI,%R11,8),%ZMM5    [7]

0x3a8e6 VMOVUPD	0x40(%RSI,%R11,8),%ZMM6    [7]

0x3a8ee VMOVUPD	0x80(%RSI,%R11,8),%ZMM7    [7]

0x3a8f6 VMOVUPD	0xc0(%RSI,%R11,8),%ZMM8    [7]

0x3a8fe VMOVUPD	(%R9,%R11,8),%ZMM13    [5]

0x3a905 VMOVUPD	0x40(%R9,%R11,8),%ZMM14    [5]

0x3a90d VMOVUPD	0x80(%R9,%R11,8),%ZMM15    [5]

0x3a915 VMOVUPD	0xc0(%R9,%R11,8),%ZMM16    [5]

0x3a91d VFMADD213PD	(%R8,%R11,8),%ZMM1,%ZMM9    [2]

0x3a924 VFMADD213PD	0x40(%R8,%R11,8),%ZMM1,%ZMM10    [2]

0x3a92c VFMADD213PD	0x80(%R8,%R11,8),%ZMM1,%ZMM11    [2]

0x3a934 VFMADD213PD	0xc0(%R8,%R11,8),%ZMM1,%ZMM12    [2]

0x3a93c VSUBPD	(%RDI,%R11,8),%ZMM5,%ZMM5    [6]

0x3a943 VSUBPD	0x40(%RDI,%R11,8),%ZMM6,%ZMM6    [6]

0x3a94b VSUBPD	0x80(%RDI,%R11,8),%ZMM7,%ZMM7    [6]

0x3a953 VSUBPD	0xc0(%RDI,%R11,8),%ZMM8,%ZMM8    [6]

0x3a95b VADDPD	(%R10,%R11,8),%ZMM5,%ZMM5    [1]

0x3a962 VADDPD	0x40(%R10,%R11,8),%ZMM6,%ZMM6    [1]

0x3a96a VADDPD	0x80(%R10,%R11,8),%ZMM7,%ZMM7    [1]

0x3a972 VADDPD	0xc0(%R10,%R11,8),%ZMM8,%ZMM8    [1]

0x3a97a VSUBPD	%ZMM9,%ZMM13,%ZMM13

0x3a980 VSUBPD	%ZMM10,%ZMM14,%ZMM14

0x3a986 VSUBPD	%ZMM11,%ZMM15,%ZMM15

0x3a98c VSUBPD	%ZMM12,%ZMM16,%ZMM16

0x3a992 VFMADD231PD	(%RDX,%R11,8),%ZMM1,%ZMM13    [8]

0x3a999 VFMADD231PD	0x40(%RDX,%R11,8),%ZMM1,%ZMM14    [8]

0x3a9a1 VFMADD231PD	0x80(%RDX,%R11,8),%ZMM1,%ZMM15    [8]

0x3a9a9 VFMADD231PD	0xc0(%RDX,%R11,8),%ZMM1,%ZMM16    [8]

0x3a9b1 VSUBPD	%ZMM9,%ZMM0,%ZMM0

0x3a9b7 VSUBPD	%ZMM10,%ZMM2,%ZMM2

0x3a9bd VSUBPD	%ZMM11,%ZMM3,%ZMM3

0x3a9c3 VSUBPD	%ZMM12,%ZMM4,%ZMM4

0x3a9c9 VMOVUPD	%ZMM5,(%R10,%R11,8)    [1]

0x3a9d0 VMOVUPD	%ZMM6,0x40(%R10,%R11,8)    [1]

0x3a9d8 VMOVUPD	%ZMM7,0x80(%R10,%R11,8)    [1]

0x3a9e0 VMOVUPD	%ZMM8,0xc0(%R10,%R11,8)    [1]

0x3a9e8 VADDPD	(%R14,%R11,8),%ZMM13,%ZMM5    [3]

0x3a9ef VADDPD	0x40(%R14,%R11,8),%ZMM14,%ZMM6    [3]

0x3a9f7 VADDPD	0x80(%R14,%R11,8),%ZMM15,%ZMM7    [3]

0x3a9ff VADDPD	0xc0(%R14,%R11,8),%ZMM16,%ZMM8    [3]

0x3aa07 VMOVUPD	%ZMM5,(%R14,%R11,8)    [3]

0x3aa0e VMOVUPD	%ZMM6,0x40(%R14,%R11,8)    [3]

0x3aa16 VMOVUPD	%ZMM7,0x80(%R14,%R11,8)    [3]

0x3aa1e VMOVUPD	%ZMM8,0xc0(%R14,%R11,8)    [3]

0x3aa26 ADD	$0x20,%R11

0x3aa2a CMP	%R11,%RAX

0x3aa2d JNE	3a8c0

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 324 - 331

--------------------------------------------------------------------------------

324:   for (int jat = 0; jat < N; jat++)

325:   {

326:     const valT du   = cur_u[jat] - old_u[jat];

327:     const valT newl = cur_d2u[jat] + lapfac * cur_du[jat];

328:     const valT dl   = old_d2u[jat] + lapfac * old_du[jat] - newl;

329:     Uat[jat] += du;

330:     d2Uat[jat] += dl;

331:     cur_d2Uat -= newl;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source	TwoBodyJastrowRef.h:324-331
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	20.00
P10 cycles	20.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	58.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	160.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	106.67
Bytes prefetched	0.00
Bytes loaded	2048.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.20
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source	TwoBodyJastrowRef.h:324-331
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	24.00
CQA cycles if no scalar integer	24.00
CQA cycles if FP arith vectorized	24.00
CQA cycles if fully vectorized	24.00
Front-end cycles	9.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	24.00
P5 cycles	24.00
P6 cycles	24.00
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	20.00
P10 cycles	20.00
P11 cycles	8.00
P12 cycles	8.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	51.00
Nb uops	58.00
Nb loads	32.00
Nb stores	8.00
Nb stack references	0.00
FLOP/cycle	12.00
Nb FLOP add-sub	160.00
Nb FLOP mul	0.00
Nb FLOP fma	64.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	106.67
Bytes prefetched	0.00
Bytes loaded	2048.00
Bytes stored	512.00
Stride 0	0.00
Stride 1	8.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source file and lines	TwoBodyJastrowRef.h:324-331
Module	libqmcwfs.so

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:324-331.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 20.00 cycles (1.20x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Type of elements and instruction set

28 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

224: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 2048 bytes (256 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	58
loop length	371
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	17
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	4.00	4.00	10.00	10.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	24.00	24.00	24.00	8.00	8.00	20.00	20.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.67
Dispatch	24.00
Data deps.	3.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

88% of peak load performance is reached (85.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (21.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3a8c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%RCX,%R11,8),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%RCX,%R11,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%RCX,%R11,8),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%RCX,%R11,8),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RSI,%R11,8),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%RSI,%R11,8),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%RSI,%R11,8),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%RSI,%R11,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R9,%R11,8),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%R9,%R11,8),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%R9,%R11,8),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%R9,%R11,8),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD213PD (%R8,%R11,8),%ZMM1,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD 0x40(%R8,%R11,8),%ZMM1,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD 0x80(%R8,%R11,8),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD 0xc0(%R8,%R11,8),%ZMM1,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD (%RDI,%R11,8),%ZMM5,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x40(%RDI,%R11,8),%ZMM6,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x80(%RDI,%R11,8),%ZMM7,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0xc0(%RDI,%R11,8),%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%R10,%R11,8),%ZMM5,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R10,%R11,8),%ZMM6,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%R10,%R11,8),%ZMM7,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R10,%R11,8),%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM9,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM11,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM12,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD (%RDX,%R11,8),%ZMM1,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%RDX,%R11,8),%ZMM1,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x80(%RDX,%R11,8),%ZMM1,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0xc0(%RDX,%R11,8),%ZMM1,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM9,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM11,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM12,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM5,(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM6,0x40(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM7,0x80(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM8,0xc0(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VADDPD (%R14,%R11,8),%ZMM13,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R14,%R11,8),%ZMM14,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%R14,%R11,8),%ZMM15,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R14,%R11,8),%ZMM16,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM5,(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM6,0x40(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM7,0x80(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM8,0xc0(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x20,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R11,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 3a8c0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x4c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source file and lines	TwoBodyJastrowRef.h:324-331
Module	libqmcwfs.so

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 24.00 to 20.00 cycles (1.20x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 64 FMA (fused multiply-add) operations.

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 8 occurrences

Type of elements and instruction set

28 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

224: addition or subtraction (64 inside FMA instructions)
64: multiply (all inside FMA instructions)

The binary loop is loading 2048 bytes (256 double precision FP elements). The binary loop is storing 512 bytes (64 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.11 FP operations per loaded or stored byte.

General properties

nb instructions	51
nb uops	58
loop length	371
used x86 registers	10
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	17
nb stack references	0

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	9.67 cycles
front end	9.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	13.33	13.33	13.33	4.00	4.00	10.00	10.00	8.00	8.00
cycles	0.50	0.50	0.25	0.25	0.50	24.00	24.00	24.00	8.00	8.00	20.00	20.00	8.00	8.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	9.67
Dispatch	24.00
Data deps.	3.00
Overall L1	24.00

Vectorization ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 24.00 cycles. At this rate:

88% of peak load performance is reached (85.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
33% of peak store performance is reached (21.33 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3a8c0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD (%RCX,%R11,8),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%RCX,%R11,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%RCX,%R11,8),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%RCX,%R11,8),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%RSI,%R11,8),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%RSI,%R11,8),%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%RSI,%R11,8),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%RSI,%R11,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R9,%R11,8),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x40(%R9,%R11,8),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0x80(%R9,%R11,8),%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD 0xc0(%R9,%R11,8),%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD213PD (%R8,%R11,8),%ZMM1,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD 0x40(%R8,%R11,8),%ZMM1,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD 0x80(%R8,%R11,8),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD 0xc0(%R8,%R11,8),%ZMM1,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD (%RDI,%R11,8),%ZMM5,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x40(%RDI,%R11,8),%ZMM6,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0x80(%RDI,%R11,8),%ZMM7,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD 0xc0(%RDI,%R11,8),%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%R10,%R11,8),%ZMM5,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R10,%R11,8),%ZMM6,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%R10,%R11,8),%ZMM7,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R10,%R11,8),%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM9,%ZMM13,%ZMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM14,%ZMM14	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM11,%ZMM15,%ZMM15	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM12,%ZMM16,%ZMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VFMADD231PD (%RDX,%R11,8),%ZMM1,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x40(%RDX,%R11,8),%ZMM1,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x80(%RDX,%R11,8),%ZMM1,%ZMM15	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0xc0(%RDX,%R11,8),%ZMM1,%ZMM16	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VSUBPD %ZMM9,%ZMM0,%ZMM0	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM10,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM11,%ZMM3,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VSUBPD %ZMM12,%ZMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM5,(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM6,0x40(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM7,0x80(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM8,0xc0(%R10,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VADDPD (%R14,%R11,8),%ZMM13,%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x40(%R14,%R11,8),%ZMM14,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0x80(%R14,%R11,8),%ZMM15,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD 0xc0(%R14,%R11,8),%ZMM16,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM5,(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM6,0x40(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM7,0x80(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM8,0xc0(%R14,%R11,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x20,%R11	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R11,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 3a8c0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x4c0>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code