OV - exec - Loop 631 - libqmcwfs.so

	Loop Id: 631	Module: libqmcwfs.so	Source: TwoBodyJastrowRef.h:342-347	Coverage: 0.12%

0x3b280 VMOVUPD	-0xc0(%R9,%R10,8),%ZMM7    [1]

0x3b288 VMOVUPD	-0x80(%R9,%R10,8),%ZMM8    [1]

0x3b290 VMOVUPD	-0x40(%R9,%R10,8),%ZMM9    [1]

0x3b298 VMOVUPD	(%R9,%R10,8),%ZMM10    [1]

0x3b29f VMOVUPD	-0xc0(%R8,%R10,8),%ZMM11    [3]

0x3b2a7 VMOVUPD	-0x80(%R8,%R10,8),%ZMM12    [3]

0x3b2af VMOVUPD	-0x40(%R8,%R10,8),%ZMM13    [3]

0x3b2b7 VMOVUPD	(%R8,%R10,8),%ZMM14    [3]

0x3b2be VMULPD	(%RCX,%R10,8),%ZMM7,%ZMM7    [5]

0x3b2c5 VMULPD	0x40(%RCX,%R10,8),%ZMM8,%ZMM8    [5]

0x3b2cd VMULPD	0x80(%RCX,%R10,8),%ZMM9,%ZMM9    [5]

0x3b2d5 VMULPD	0xc0(%RCX,%R10,8),%ZMM10,%ZMM10    [5]

0x3b2dd VFMSUB132PD	(%RDX,%R10,8),%ZMM7,%ZMM11    [2]

0x3b2e4 VFMSUB132PD	0x40(%RDX,%R10,8),%ZMM8,%ZMM12    [2]

0x3b2ec VFMSUB132PD	0x80(%RDX,%R10,8),%ZMM9,%ZMM13    [2]

0x3b2f4 VFMSUB132PD	0xc0(%RDX,%R10,8),%ZMM10,%ZMM14    [2]

0x3b2fc VADDPD	%ZMM3,%ZMM7,%ZMM3

0x3b302 VADDPD	%ZMM4,%ZMM8,%ZMM4

0x3b308 VADDPD	%ZMM5,%ZMM9,%ZMM5

0x3b30e VADDPD	%ZMM6,%ZMM10,%ZMM6

0x3b314 VADDPD	-0xc0(%RSI,%R10,8),%ZMM11,%ZMM11    [4]

0x3b31c VADDPD	-0x80(%RSI,%R10,8),%ZMM12,%ZMM12    [4]

0x3b324 VADDPD	-0x40(%RSI,%R10,8),%ZMM13,%ZMM13    [4]

0x3b32c VADDPD	(%RSI,%R10,8),%ZMM14,%ZMM14    [4]

0x3b333 VMOVUPD	%ZMM11,-0xc0(%RSI,%R10,8)    [4]

0x3b33b VMOVUPD	%ZMM12,-0x80(%RSI,%R10,8)    [4]

0x3b343 VMOVUPD	%ZMM13,-0x40(%RSI,%R10,8)    [4]

0x3b34b VMOVUPD	%ZMM14,(%RSI,%R10,8)    [4]

0x3b352 ADD	$0x20,%R10

0x3b356 CMP	%R10,%RAX

0x3b359 JNE	3b280

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 342 - 347

--------------------------------------------------------------------------------

342:     for (int jat = 0; jat < N; jat++)

343:     {

344:       const valT newg = cur_du_pt[jat] * new_dX[jat];

345:       const valT dg   = newg - old_du_pt[jat] * old_dX[jat];

346:       save_g[jat] -= dg;

347:       cur_g += newg;

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	14.67
CQA cycles if no scalar integer	14.67
CQA cycles if FP arith vectorized	14.67
CQA cycles if fully vectorized	14.67
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	14.67
P5 cycles	14.67
P6 cycles	14.67
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	20.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	10.91
Nb FLOP add-sub	64.00
Nb FLOP mul	32.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	104.73
Bytes prefetched	0.00
Bytes loaded	1280.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.00
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.83
Bottlenecks	P5, P6, P7,
Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 32
Source loop unroll confidence level	max
Unroll/vectorization loop type	main
Unroll factor	32
CQA cycles	14.67
CQA cycles if no scalar integer	14.67
CQA cycles if FP arith vectorized	14.67
CQA cycles if fully vectorized	14.67
Front-end cycles	5.67
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	14.67
P5 cycles	14.67
P6 cycles	14.67
P7 cycles	8.00
P8 cycles	8.00
P9 cycles	8.00
P10 cycles	8.00
P11 cycles	4.00
P12 cycles	4.00
P13 cycles	0.00
Inter-iter dependencies cycles	3
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	34.00
Nb loads	20.00
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	10.91
Nb FLOP add-sub	64.00
Nb FLOP mul	32.00
Nb FLOP fma	32.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	104.73
Bytes prefetched	0.00
Bytes loaded	1280.00
Bytes stored	256.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	100.00
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	100.00
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	libqmcwfs.so

The loop is defined in /beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:342-347.

It is main loop of related source loop which is unrolled by 32 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 14.67 to 8.00 cycles (1.83x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction (32 inside FMA instructions)
64: multiply (32 inside FMA instructions)

The binary loop is loading 1280 bytes (160 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	34
loop length	223
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	4.00	4.00	4.00	4.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	14.67	14.67	14.67	8.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	5.67
Dispatch	14.67
Data deps.	3.00
Overall L1	14.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.67 cycles. At this rate:

90% of peak load performance is reached (87.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (17.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3b280

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD -0xc0(%R9,%R10,8),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x80(%R9,%R10,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x40(%R9,%R10,8),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R9,%R10,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0xc0(%R8,%R10,8),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x80(%R8,%R10,8),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x40(%R8,%R10,8),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R8,%R10,8),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD (%RCX,%R10,8),%ZMM7,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%RCX,%R10,8),%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x80(%RCX,%R10,8),%ZMM9,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0xc0(%RCX,%R10,8),%ZMM10,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMSUB132PD (%RDX,%R10,8),%ZMM7,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMSUB132PD 0x40(%RDX,%R10,8),%ZMM8,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMSUB132PD 0x80(%RDX,%R10,8),%ZMM9,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMSUB132PD 0xc0(%RDX,%R10,8),%ZMM10,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM3,%ZMM7,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM4,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM5,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM6,%ZMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD -0xc0(%RSI,%R10,8),%ZMM11,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD -0x80(%RSI,%R10,8),%ZMM12,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD -0x40(%RSI,%R10,8),%ZMM13,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%RSI,%R10,8),%ZMM14,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM11,-0xc0(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM12,-0x80(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM13,-0x40(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM14,(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x20,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 3b280 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0xe80>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	libqmcwfs.so

gain
potential
hint
expert

Vectorization

Your loop is fully vectorized, using full register length.

Details

All SSE/AVX instructions are used in vector version (process two or more data elements in vector registers).

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 14.67 to 8.00 cycles (1.83x speedup).

Workaround

Read less array elements
Write less array elements
Provide more information to your compiler:
- hardcode the bounds of the corresponding 'for' loop

FMA

Detected 32 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VMOVUPD: 4 occurrences

Type of elements and instruction set

16 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 160 FP arithmetical operations:

96: addition or subtraction (32 inside FMA instructions)
64: multiply (32 inside FMA instructions)

The binary loop is loading 1280 bytes (160 double precision FP elements). The binary loop is storing 256 bytes (32 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	31
nb uops	34
loop length	223
used x86 registers	7
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	12
nb stack references	0
ADD-SUB / MUL ratio	2.00

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	5.67 cycles
front end	5.67 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	8.00	8.00	8.00	4.00	4.00	4.00	4.00	4.00	4.00
cycles	0.50	0.50	0.25	0.25	0.50	14.67	14.67	14.67	8.00	8.00	8.00	8.00	4.00	4.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	3.00

Cycles summary

Front-end	5.67
Dispatch	14.67
Data deps.	3.00
Overall L1	14.67

Vectorization ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Vector efficiency ratios

all	100%
load	100%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 14.67 cycles. At this rate:

90% of peak load performance is reached (87.27 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (17.45 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 3b280

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVUPD -0xc0(%R9,%R10,8),%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x80(%R9,%R10,8),%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x40(%R9,%R10,8),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R9,%R10,8),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0xc0(%R8,%R10,8),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x80(%R8,%R10,8),%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD -0x40(%R8,%R10,8),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVUPD (%R8,%R10,8),%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMULPD (%RCX,%R10,8),%ZMM7,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x40(%RCX,%R10,8),%ZMM8,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0x80(%RCX,%R10,8),%ZMM9,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMULPD 0xc0(%RCX,%R10,8),%ZMM10,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VFMSUB132PD (%RDX,%R10,8),%ZMM7,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMSUB132PD 0x40(%RDX,%R10,8),%ZMM8,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMSUB132PD 0x80(%RDX,%R10,8),%ZMM9,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMSUB132PD 0xc0(%RDX,%R10,8),%ZMM10,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VADDPD %ZMM3,%ZMM7,%ZMM3	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM4,%ZMM8,%ZMM4	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM5,%ZMM9,%ZMM5	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD %ZMM6,%ZMM10,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VADDPD -0xc0(%RSI,%R10,8),%ZMM11,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD -0x80(%RSI,%R10,8),%ZMM12,%ZMM12	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD -0x40(%RSI,%R10,8),%ZMM13,%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VADDPD (%RSI,%R10,8),%ZMM14,%ZMM14	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	1
VMOVUPD %ZMM11,-0xc0(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM12,-0x80(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM13,-0x40(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
VMOVUPD %ZMM14,(%RSI,%R10,8)	2	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	1	1	5	2
ADD $0x20,%R10	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
CMP %R10,%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 3b280 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0xe80>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code