OV - exec - Loop 450 - libqmcwfs.so

	Loop Id: 450	Module: libqmcwfs.so	Source: BsplineFunctor.h:302-336 [...]	Coverage: 0.02%

0x31790 VMOVAPD	(%R10,%RBX,4),%ZMM31    [25]

0x31797 VPCMPEQD	%YMM9,%YMM9,%YMM9

0x3179c VMOVAPD	0x900(%RSP),%ZMM13    [38]

0x317a4 KXNORW	%K0,%K0,%K1

0x317a8 VMULPD	%ZMM30,%ZMM31,%ZMM1

0x317ae VCVTTPD2DQ	%ZMM1,%YMM4

0x317b4 VPADDD	0x180(%RSP),%YMM4,%YMM11    [38]

0x317bd VRNDSCALEPD	$0xb,%ZMM1,%ZMM2

0x317c4 VPMOVSXDQ	%YMM4,%ZMM3

0x317ca VPSUBD	%YMM9,%YMM4,%YMM9

0x317cf VSUBPD	%ZMM2,%ZMM1,%ZMM1

0x317d5 VPADDD	0xaa0(%RSP),%YMM4,%YMM4    [38]

0x317de VPMOVSXDQ	%YMM9,%ZMM9

0x317e4 VMULPD	%ZMM1,%ZMM1,%ZMM2

0x317ea VEXTRACTI128	$0x1,%YMM3,%XMM5

0x317f0 VPEXTRQ	$0x1,%XMM3,%R14

0x317f6 VMOVQ	%XMM3,%R15

0x317fb VEXTRACTI32X4	$0x2,%ZMM3,%XMM6

0x31802 VEXTRACTI32X4	$0x3,%ZMM3,%XMM3

0x31809 VMOVQ	%XMM3,%R13

0x3180e VMOVQ	%XMM5,%R12

0x31813 VEXTRACTI32X4	$0x2,%ZMM9,%XMM10

0x3181a VMOVSD	(%RCX,%R13,8),%XMM7    [32]

0x31820 VMOVQ	%XMM6,%R13

0x31825 VMOVSD	(%RCX,%R13,8),%XMM8    [6]

0x3182b VPEXTRQ	$0x1,%XMM3,%R13

0x31831 VMULPD	%ZMM1,%ZMM2,%ZMM3

0x31837 VMOVHPD	(%RCX,%R13,8),%XMM7,%XMM7    [23]

0x3183d VPEXTRQ	$0x1,%XMM6,%R13

0x31843 VPMOVSXDQ	%YMM4,%ZMM4

0x31849 VMOVHPD	(%RCX,%R13,8),%XMM8,%XMM6    [22]

0x3184f VMOVSD	(%RCX,%R15,8),%XMM8    [1]

0x31855 VPEXTRQ	$0x1,%XMM5,%R13

0x3185b VMOVSD	(%RCX,%R12,8),%XMM5    [3]

0x31861 VPEXTRQ	$0x1,%XMM9,%R15

0x31867 VMOVHPD	(%RCX,%R14,8),%XMM8,%XMM8    [15]

0x3186d VMOVHPD	(%RCX,%R13,8),%XMM5,%XMM5    [21]

0x31873 VMOVQ	%XMM9,%R14

0x31878 VINSERTF128	$0x1,%XMM7,%YMM6,%YMM6

0x3187e VEXTRACTI128	$0x1,%YMM9,%XMM7

0x31884 VEXTRACTI32X4	$0x3,%ZMM9,%XMM9

0x3188b VMOVQ	%XMM9,%R12

0x31890 VPEXTRQ	$0x1,%XMM9,%R13

0x31896 VINSERTF128	$0x1,%XMM5,%YMM8,%YMM5

0x3189c VMOVSD	(%RCX,%R12,8),%XMM9    [8]

0x318a2 VMOVQ	%XMM10,%R12

0x318a7 VMOVHPD	(%RCX,%R13,8),%XMM9,%XMM9    [20]

0x318ad VPEXTRQ	$0x1,%XMM10,%R13

0x318b3 VMOVSD	(%RCX,%R12,8),%XMM10    [4]

0x318b9 VMOVQ	%XMM7,%R12

0x318be VINSERTF64X4	$0x1,%YMM6,%ZMM5,%ZMM5

0x318c5 VMOVHPD	(%RCX,%R13,8),%XMM10,%XMM8    [19]

0x318cb VPEXTRQ	$0x1,%XMM7,%R13

0x318d1 VMOVSD	(%RCX,%R12,8),%XMM7    [24]

0x318d7 VMOVHPD	(%RCX,%R13,8),%XMM7,%XMM10    [18]

0x318dd VINSERTF128	$0x1,%XMM9,%YMM8,%YMM7

0x318e3 VMOVSD	(%RCX,%R14,8),%XMM8    [26]

0x318e9 VPMOVSXDQ	%YMM11,%ZMM9

0x318ef VMOVAPD	0x240(%RSP),%ZMM11    [38]

0x318f7 VMOVHPD	(%RCX,%R15,8),%XMM8,%XMM8    [28]

0x318fd VMOVQ	%XMM9,%R14

0x31902 VPEXTRQ	$0x1,%XMM9,%R15

0x31908 VEXTRACTI128	$0x1,%YMM9,%XMM6

0x3190e VINSERTF128	$0x1,%XMM10,%YMM8,%YMM8

0x31914 VEXTRACTI32X4	$0x2,%ZMM9,%XMM10

0x3191b VEXTRACTI32X4	$0x3,%ZMM9,%XMM9

0x31922 VMOVQ	%XMM9,%R12

0x31927 VPEXTRQ	$0x1,%XMM9,%R13

0x3192d VMOVSD	(%RCX,%R12,8),%XMM9    [7]

0x31933 VMOVQ	%XMM10,%R12

0x31938 VINSERTF64X4	$0x1,%YMM7,%ZMM8,%ZMM7

0x3193f VMOVAPD	%ZMM1,%ZMM8

0x31945 VFMADD213PD	%ZMM14,%ZMM0,%ZMM8

0x3194b VMOVHPD	(%RCX,%R13,8),%XMM9,%XMM9    [17]

0x31951 VPEXTRQ	$0x1,%XMM10,%R13

0x31957 VMOVSD	(%RCX,%R12,8),%XMM10    [2]

0x3195d VPEXTRQ	$0x1,%XMM6,%R12

0x31963 VMOVHPD	(%RCX,%R13,8),%XMM10,%XMM10    [13]

0x31969 VMOVQ	%XMM6,%R13

0x3196e VMULPD	%ZMM5,%ZMM8,%ZMM8

0x31974 VINSERTF128	$0x1,%XMM9,%YMM10,%YMM6

0x3197a VMOVAPD	%ZMM1,%ZMM9

0x31980 VFMADD132PD	0x280(%RSP),%ZMM11,%ZMM9    [38]

0x31988 VMOVAPD	%ZMM2,%ZMM10

0x3198e VFMADD132PD	0x980(%RSP),%ZMM13,%ZMM10    [38]

0x31996 VMOVAPD	0x840(%RSP),%ZMM13    [38]

0x3199e VMOVAPD	%ZMM3,%ZMM11

0x319a4 VFMADD231PD	0x940(%RSP),%ZMM1,%ZMM10    [38]

0x319ac VFMADD213PD	%ZMM8,%ZMM7,%ZMM9

0x319b2 VMOVAPD	%ZMM2,%ZMM8

0x319b8 VFMADD132PD	0x8c0(%RSP),%ZMM13,%ZMM8    [38]

0x319c0 VMOVAPD	0x5c0(%RSP),%ZMM13    [38]

0x319c8 VFMADD231PD	0x880(%RSP),%ZMM1,%ZMM8    [38]

0x319d0 VMULPD	%ZMM5,%ZMM10,%ZMM10

0x319d6 VFMADD132PD	0x680(%RSP),%ZMM13,%ZMM11    [38]

0x319de VMOVAPD	0x4c0(%RSP),%ZMM13    [38]

0x319e6 VFMADD231PD	0x640(%RSP),%ZMM2,%ZMM11    [38]

0x319ee VFMADD213PD	%ZMM10,%ZMM7,%ZMM8

0x319f4 VMOVAPD	%ZMM3,%ZMM10

0x319fa VFMADD132PD	0x580(%RSP),%ZMM13,%ZMM10    [38]

0x31a02 VFMADD231PD	0x600(%RSP),%ZMM1,%ZMM11    [38]

0x31a0a VFMADD231PD	0x540(%RSP),%ZMM2,%ZMM10    [38]

0x31a12 VFMADD231PD	0x500(%RSP),%ZMM1,%ZMM10    [38]

0x31a1a VMULPD	%ZMM5,%ZMM11,%ZMM5

0x31a20 VMOVAPD	0x1c0(%RSP),%ZMM11    [38]

0x31a28 VFMADD213PD	%ZMM5,%ZMM7,%ZMM10

0x31a2e VMOVSD	(%RCX,%R14,8),%XMM7    [16]

0x31a34 VMOVSD	(%RCX,%R13,8),%XMM5    [5]

0x31a3a VPEXTRQ	$0x1,%XMM4,%R14

0x31a40 VMOVHPD	(%RCX,%R15,8),%XMM7,%XMM7    [27]

0x31a46 VMOVHPD	(%RCX,%R12,8),%XMM5,%XMM5    [11]

0x31a4c VMOVQ	%XMM4,%R15

0x31a51 VINSERTF128	$0x1,%XMM5,%YMM7,%YMM5

0x31a57 VMOVAPD	%ZMM2,%ZMM7

0x31a5d VINSERTF64X4	$0x1,%YMM6,%ZMM5,%ZMM5

0x31a64 VMOVAPD	%ZMM1,%ZMM6

0x31a6a VFMADD132PD	0x200(%RSP),%ZMM11,%ZMM6    [38]

0x31a72 VMOVAPD	0x780(%RSP),%ZMM11    [38]

0x31a7a VFMADD132PD	0x800(%RSP),%ZMM11,%ZMM7    [38]

0x31a82 VMOVAPD	%ZMM3,%ZMM11

0x31a88 VFMADD213PD	%ZMM9,%ZMM5,%ZMM6

0x31a8e VMOVAPD	0x3c0(%RSP),%ZMM9    [38]

0x31a96 VFMADD231PD	0x7c0(%RSP),%ZMM1,%ZMM7    [38]

0x31a9e VFMADD132PD	0x480(%RSP),%ZMM9,%ZMM11    [38]

0x31aa6 VEXTRACTI32X4	$0x2,%ZMM4,%XMM9

0x31aad VFMADD231PD	0x440(%RSP),%ZMM2,%ZMM11    [38]

0x31ab5 VFMADD213PD	%ZMM8,%ZMM5,%ZMM7

0x31abb VFMADD231PD	0x400(%RSP),%ZMM1,%ZMM11    [38]

0x31ac3 VFMADD213PD	%ZMM10,%ZMM5,%ZMM11

0x31ac9 VEXTRACTI128	$0x1,%YMM4,%XMM5

0x31acf VEXTRACTI32X4	$0x3,%ZMM4,%XMM4

0x31ad6 VMOVAPD	0x2c0(%RSP),%ZMM10    [38]

0x31ade VMOVQ	%XMM4,%R12

0x31ae3 VPEXTRQ	$0x1,%XMM4,%R13

0x31ae9 VMOVSD	(%RCX,%R12,8),%XMM4    [33]

0x31aef VPEXTRQ	$0x1,%XMM9,%R12

0x31af5 VMOVHPD	(%RCX,%R13,8),%XMM4,%XMM4    [12]

0x31afb VMOVQ	%XMM9,%R13

0x31b00 VMOVSD	(%RCX,%R13,8),%XMM9    [36]

0x31b06 VMOVQ	%XMM5,%R13

0x31b0b VMOVHPD	(%RCX,%R12,8),%XMM9,%XMM9    [10]

0x31b11 VPEXTRQ	$0x1,%XMM5,%R12

0x31b17 VMOVSD	(%RCX,%R13,8),%XMM5    [34]

0x31b1d VMOVHPD	(%RCX,%R12,8),%XMM5,%XMM5    [9]

0x31b23 VFMADD132PD	0x380(%RSP),%ZMM10,%ZMM3    [38]

0x31b2b VFMADD231PD	0x340(%RSP),%ZMM2,%ZMM3    [38]

0x31b33 VINSERTF128	$0x1,%XMM4,%YMM9,%YMM4

0x31b39 VMOVSD	(%RCX,%R15,8),%XMM9    [35]

0x31b3f VMOVHPD	(%RCX,%R14,8),%XMM9,%XMM9    [14]

0x31b45 VFMADD231PD	0x300(%RSP),%ZMM1,%ZMM3    [38]

0x31b4d VINSERTF128	$0x1,%XMM5,%YMM9,%YMM5

0x31b53 VMOVAPD	0x6c0(%RSP),%ZMM9    [38]

0x31b5b VINSERTF64X4	$0x1,%YMM4,%ZMM5,%ZMM4

0x31b62 VMOVAPD	0xa00(%RSP),%ZMM5    [38]

0x31b6a VFMADD213PD	%ZMM11,%ZMM4,%ZMM3

0x31b70 VFMADD132PD	0x740(%RSP),%ZMM9,%ZMM2    [38]

0x31b78 VFMADD231PD	0x700(%RSP),%ZMM1,%ZMM2    [38]

0x31b80 VFMADD132PD	0xa40(%RSP),%ZMM5,%ZMM1    [38]

0x31b88 VFMADD213PD	%ZMM7,%ZMM4,%ZMM2

0x31b8e VFMADD213PD	%ZMM6,%ZMM4,%ZMM1

0x31b94 VMULPD	0x9c0(%RSP),%ZMM1,%ZMM1    [38]

0x31b9c VMOVAPD	(%RAX,%RBX,2),%YMM4    [31]

0x31ba1 ADD	$0x10,%RBX

0x31ba5 VMULPD	%ZMM30,%ZMM2,%ZMM2

0x31bab VDIVPD	%ZMM31,%ZMM2,%ZMM2

0x31bb1 VSCATTERDPD	%ZMM1,(%RDX,%YMM4,8){%K1}    [37]

0x31bb8 KXNORW	%K0,%K0,%K1

0x31bbc VSCATTERDPD	%ZMM2,(%R11,%YMM4,8){%K1}    [30]

0x31bc3 KXNORW	%K0,%K0,%K1

0x31bc7 VSCATTERDPD	%ZMM3,(%R8,%YMM4,8){%K1}    [29]

0x31bce CMP	%RBX,%R9

0x31bd1 JNE	31790

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1064 - 1064

--------------------------------------------------------------------------------

1064: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 302 - 336

--------------------------------------------------------------------------------

302:   #pragma omp simd

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Path /

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P8,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source	stl_vector.h:1064-1064,BsplineFunctor.h:302-336
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	59.50
CQA cycles if no scalar integer	58.75
CQA cycles if FP arith vectorized	59.50
CQA cycles if fully vectorized	47.00
Front-end cycles	54.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	35.67
P5 cycles	35.67
P6 cycles	35.67
P7 cycles	59.50
P8 cycles	49.58
P9 cycles	33.83
P10 cycles	34.08
P11 cycles	43.00
P12 cycles	43.00
P13 cycles	9.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	172.00
Nb uops	329.00
Nb loads	71.00
Nb stores	3.00
Nb stack references	37.00
FLOP/cycle	10.22
Nb FLOP add-sub	8.00
Nb FLOP mul	64.00
Nb FLOP fma	264.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	47.87
Bytes prefetched	0.00
Bytes loaded	2656.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	61.45
Vectorization ratio load	54.93
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	55.56
Vector-efficiency ratio all	53.31
Vector-efficiency ratio load	58.45
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	34.03

Metric	Value
CQA speedup if no scalar integer	1.01
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.27
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.09
Bottlenecks	P8,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source	stl_vector.h:1064-1064,BsplineFunctor.h:302-336
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	high
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	59.50
CQA cycles if no scalar integer	58.75
CQA cycles if FP arith vectorized	59.50
CQA cycles if fully vectorized	47.00
Front-end cycles	54.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	35.67
P5 cycles	35.67
P6 cycles	35.67
P7 cycles	59.50
P8 cycles	49.58
P9 cycles	33.83
P10 cycles	34.08
P11 cycles	43.00
P12 cycles	43.00
P13 cycles	9.00
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	172.00
Nb uops	329.00
Nb loads	71.00
Nb stores	3.00
Nb stack references	37.00
FLOP/cycle	10.22
Nb FLOP add-sub	8.00
Nb FLOP mul	64.00
Nb FLOP fma	264.00
Nb FLOP div	8.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	47.87
Bytes prefetched	0.00
Bytes loaded	2656.00
Bytes stored	192.00
Stride 0	1.00
Stride 1	2.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	7.00
Vectorization ratio all	61.45
Vectorization ratio load	54.93
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	55.56
Vector-efficiency ratio all	53.31
Vector-efficiency ratio load	58.45
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	62.50
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	34.03

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source file and lines	BsplineFunctor.h:302-336
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:302-336

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 53% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 59.50 to 47.00 cycles (1.27x speedup).

Details

61% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

54% of SSE/AVX loads are used in vector version.
55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by execution of FP multiply or FMA (fused multiply-add) operations (the FP multiply/FMA unit is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 59.50 to 54.83 cycles (1.09x speedup).

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 264 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences
VPEXTRQ: 16 occurrences
VSCATTERDPD: 3 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 8 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERDPD: 3 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

44 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 608 FP arithmetical operations:

272: addition or subtraction (264 inside FMA instructions)
328: multiply (264 inside FMA instructions)
8: divide

The binary loop is loading 2656 bytes (332 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	329
loop length	1095
used x86 registers	13
used mmx registers	0
used xmm registers	8
used ymm registers	9
used zmm registers	16
nb stack references	37
ADD-SUB / MUL ratio	0.13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	54.83 cycles
front end	54.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	23.67	23.67	23.67	33.50	33.58	33.33	33.58	43.00	43.00
cycles	0.50	0.50	0.25	0.25	0.50	35.67	35.67	35.67	59.50	49.58	33.83	34.08	43.00	43.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	9.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	54.83
Dispatch	59.50
DIV/SQRT	9.00
Data deps.	1.00
Overall L1	59.50

Vectorization ratios

INT

all	38%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	71%
load	53%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	61%
load	54%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	55%

Vector efficiency ratios

INT

all	21%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	67%
load	58%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

INT+FP

all	53%
load	58%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.50 cycles. At this rate:

46% of peak load performance is reached (44.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.23 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 31790

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVAPD (%R10,%RBX,4),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VPCMPEQD %YMM9,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVAPD 0x900(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VMULPD %ZMM30,%ZMM31,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VCVTTPD2DQ %ZMM1,%YMM4	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33
VPADDD 0x180(%RSP),%YMM4,%YMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VRNDSCALEPD $0xb,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPMOVSXDQ %YMM4,%ZMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VPSUBD %YMM9,%YMM4,%YMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VSUBPD %ZMM2,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPADDD 0xaa0(%RSP),%YMM4,%YMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPMOVSXDQ %YMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMULPD %ZMM1,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VEXTRACTI128 $0x1,%YMM3,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPEXTRQ $0x1,%XMM3,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM3,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI32X4 $0x2,%ZMM3,%XMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X4 $0x3,%ZMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVQ %XMM3,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM5,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVSD (%RCX,%R13,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RCX,%R13,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM3,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMULPD %ZMM1,%ZMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVHPD (%RCX,%R13,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM6,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVHPD (%RCX,%R13,8),%XMM8,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RCX,%R15,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM5,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM9,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R14,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RCX,%R13,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM7,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI128 $0x1,%YMM9,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VEXTRACTI32X4 $0x3,%ZMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVQ %XMM9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VINSERTF128 $0x1,%XMM5,%YMM8,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RCX,%R12,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RCX,%R13,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM10,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM7,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF64X4 $0x1,%YMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVHPD (%RCX,%R13,8),%XMM10,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM7,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R13,8),%XMM7,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM9,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RCX,%R14,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPMOVSXDQ %YMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVAPD 0x240(%RSP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVHPD (%RCX,%R15,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM9,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VINSERTF128 $0x1,%XMM10,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X4 $0x3,%ZMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVQ %XMM9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF64X4 $0x1,%YMM7,%ZMM8,%ZMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD %ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %ZMM14,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVHPD (%RCX,%R13,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM10,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM6,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R13,8),%XMM10,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM6,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD %ZMM5,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VINSERTF128 $0x1,%XMM9,%YMM10,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %ZMM1,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x280(%RSP),%ZMM11,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM2,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x980(%RSP),%ZMM13,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x840(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD %ZMM3,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD 0x940(%RSP),%ZMM1,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM8,%ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x8c0(%RSP),%ZMM13,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x5c0(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD 0x880(%RSP),%ZMM1,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM5,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD 0x680(%RSP),%ZMM13,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x4c0(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD 0x640(%RSP),%ZMM2,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM10,%ZMM7,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x580(%RSP),%ZMM13,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x600(%RSP),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x540(%RSP),%ZMM2,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x500(%RSP),%ZMM1,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM5,%ZMM11,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVAPD 0x1c0(%RSP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD213PD %ZMM5,%ZMM7,%ZMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVSD (%RCX,%R14,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RCX,%R13,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM4,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R15,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RCX,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM5,%YMM7,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %ZMM2,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VINSERTF64X4 $0x1,%YMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD %ZMM1,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x200(%RSP),%ZMM11,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x780(%RSP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD132PD 0x800(%RSP),%ZMM11,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM3,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %ZMM9,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x3c0(%RSP),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD 0x7c0(%RSP),%ZMM1,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x480(%RSP),%ZMM9,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VEXTRACTI32X4 $0x2,%ZMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VFMADD231PD 0x440(%RSP),%ZMM2,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM8,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x400(%RSP),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM10,%ZMM5,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VEXTRACTI128 $0x1,%YMM4,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VEXTRACTI32X4 $0x3,%ZMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVAPD 0x2c0(%RSP),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM9,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RCX,%R13,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM5,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RCX,%R12,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM5,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R13,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VFMADD132PD 0x380(%RSP),%ZMM10,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x340(%RSP),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VINSERTF128 $0x1,%XMM4,%YMM9,%YMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RCX,%R15,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R14,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VFMADD231PD 0x300(%RSP),%ZMM1,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VINSERTF128 $0x1,%XMM5,%YMM9,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD 0x6c0(%RSP),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VINSERTF64X4 $0x1,%YMM4,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD 0xa00(%RSP),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD213PD %ZMM11,%ZMM4,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x740(%RSP),%ZMM9,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x700(%RSP),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0xa40(%RSP),%ZMM5,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM7,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM6,%ZMM4,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD 0x9c0(%RSP),%ZMM1,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVAPD (%RAX,%RBX,2),%YMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADD $0x10,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULPD %ZMM30,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VDIVPD %ZMM31,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VSCATTERDPD %ZMM1,(%RDX,%YMM4,8){%K1}	48	0	0	0	0	0	0	0	0	0	2.17	3.17	1.67	9	9	4-35	9
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VSCATTERDPD %ZMM2,(%R11,%YMM4,8){%K1}	48	0	0	0	0	0	0	0	0	0	2.17	3.17	1.67	9	9	4-35	9
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VSCATTERDPD %ZMM3,(%R8,%YMM4,8){%K1}	48	0	0	0	0	0	0	0	0	0	2.17	3.17	1.67	9	9	4-35	9
CMP %RBX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 31790 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi
Source file and lines	BsplineFunctor.h:302-336
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:302-336

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

61% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

54% of SSE/AVX loads are used in vector version.
55% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Workaround

Reduce the number of FP multiply/FMA instructions

FMA

Detected 264 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 1 occurrences
VPEXTRQ: 16 occurrences
VSCATTERDPD: 3 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 7 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 8 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Gather/scatter instructions

Detected gather/scatter instructions (typically caused by indirect accesses).

Details

VSCATTERDPD: 3 occurrences

Workaround

Try to simplify your code and/or replace indirect accesses with unit-stride ones.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 1 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

44 AVX-512 instructions are processing arithmetic or math operations on double precision FP elements in vector mode (eight at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 608 FP arithmetical operations:

272: addition or subtraction (264 inside FMA instructions)
328: multiply (264 inside FMA instructions)
8: divide

The binary loop is loading 2656 bytes (332 double precision FP elements). The binary loop is storing 192 bytes (24 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.21 FP operations per loaded or stored byte.

General properties

nb instructions	172
nb uops	329
loop length	1095
used x86 registers	13
used mmx registers	0
used xmm registers	8
used ymm registers	9
used zmm registers	16
nb stack references	37
ADD-SUB / MUL ratio	0.13

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	54.83 cycles
front end	54.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	23.67	23.67	23.67	33.50	33.58	33.33	33.58	43.00	43.00
cycles	0.50	0.50	0.25	0.25	0.50	35.67	35.67	35.67	59.50	49.58	33.83	34.08	43.00	43.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	9.00
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	54.83
Dispatch	59.50
DIV/SQRT	9.00
Data deps.	1.00
Overall L1	59.50

Vectorization ratios

INT

all	38%
load	100%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	71%
load	53%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	61%
load	54%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	55%

Vector efficiency ratios

INT

all	21%
load	50%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
other	19%

all	67%
load	58%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	65%

INT+FP

all	53%
load	58%
store	100%
mul	100%
add-sub	62%
fma	100%
div/sqrt	100%
other	34%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 59.50 cycles. At this rate:

46% of peak load performance is reached (44.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
5% of peak store performance is reached (3.23 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the loop is: 31790

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMOVAPD (%R10,%RBX,4),%ZMM31	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VPCMPEQD %YMM9,%YMM9,%YMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVAPD 0x900(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VMULPD %ZMM30,%ZMM31,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VCVTTPD2DQ %ZMM1,%YMM4	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	7	1.33
VPADDD 0x180(%RSP),%YMM4,%YMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VRNDSCALEPD $0xb,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPMOVSXDQ %YMM4,%ZMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VPSUBD %YMM9,%YMM4,%YMM9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VSUBPD %ZMM2,%ZMM1,%ZMM1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	1
VPADDD 0xaa0(%RSP),%YMM4,%YMM4	1	0	0	0	0	0	0.33	0.33	0.33	0.25	0.25	0.25	0.25	0	0	1	0.50
VPMOVSXDQ %YMM9,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMULPD %ZMM1,%ZMM1,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VEXTRACTI128 $0x1,%YMM3,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPEXTRQ $0x1,%XMM3,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM3,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI32X4 $0x2,%ZMM3,%XMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X4 $0x3,%ZMM3,%XMM3	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVQ %XMM3,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVQ %XMM5,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVSD (%RCX,%R13,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM6,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RCX,%R13,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM3,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMULPD %ZMM1,%ZMM2,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVHPD (%RCX,%R13,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM6,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VPMOVSXDQ %YMM4,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVHPD (%RCX,%R13,8),%XMM8,%XMM6	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RCX,%R15,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM5,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM9,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R14,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RCX,%R13,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM7,%YMM6,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI128 $0x1,%YMM9,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VEXTRACTI32X4 $0x3,%ZMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVQ %XMM9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VINSERTF128 $0x1,%XMM5,%YMM8,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RCX,%R12,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RCX,%R13,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM10,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM7,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF64X4 $0x1,%YMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVHPD (%RCX,%R13,8),%XMM10,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM7,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R13,8),%XMM7,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM9,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RCX,%R14,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPMOVSXDQ %YMM11,%ZMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVAPD 0x240(%RSP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVHPD (%RCX,%R15,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM9,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM9,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VINSERTF128 $0x1,%XMM10,%YMM8,%YMM8	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VEXTRACTI32X4 $0x2,%ZMM9,%XMM10	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VEXTRACTI32X4 $0x3,%ZMM9,%XMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVQ %XMM9,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM9,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM10,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF64X4 $0x1,%YMM7,%ZMM8,%ZMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD %ZMM1,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %ZMM14,%ZMM0,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVHPD (%RCX,%R13,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM10,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM6,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R13,8),%XMM10,%XMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM6,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMULPD %ZMM5,%ZMM8,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VINSERTF128 $0x1,%XMM9,%YMM10,%YMM6	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %ZMM1,%ZMM9	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x280(%RSP),%ZMM11,%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM2,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x980(%RSP),%ZMM13,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x840(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVAPD %ZMM3,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD231PD 0x940(%RSP),%ZMM1,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM8,%ZMM7,%ZMM9	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM2,%ZMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x8c0(%RSP),%ZMM13,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x5c0(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD 0x880(%RSP),%ZMM1,%ZMM8	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM5,%ZMM10,%ZMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VFMADD132PD 0x680(%RSP),%ZMM13,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x4c0(%RSP),%ZMM13	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD 0x640(%RSP),%ZMM2,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM10,%ZMM7,%ZMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM3,%ZMM10	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x580(%RSP),%ZMM13,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x600(%RSP),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x540(%RSP),%ZMM2,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x500(%RSP),%ZMM1,%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMULPD %ZMM5,%ZMM11,%ZMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VMOVAPD 0x1c0(%RSP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD213PD %ZMM5,%ZMM7,%ZMM10	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVSD (%RCX,%R14,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RCX,%R13,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM4,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R15,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RCX,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM4,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VINSERTF128 $0x1,%XMM5,%YMM7,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %ZMM2,%ZMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VINSERTF64X4 $0x1,%YMM6,%ZMM5,%ZMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD %ZMM1,%ZMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD132PD 0x200(%RSP),%ZMM11,%ZMM6	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x780(%RSP),%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD132PD 0x800(%RSP),%ZMM11,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VMOVAPD %ZMM3,%ZMM11	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %ZMM9,%ZMM5,%ZMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMOVAPD 0x3c0(%RSP),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD231PD 0x7c0(%RSP),%ZMM1,%ZMM7	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x480(%RSP),%ZMM9,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VEXTRACTI32X4 $0x2,%ZMM4,%XMM9	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VFMADD231PD 0x440(%RSP),%ZMM2,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM8,%ZMM5,%ZMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x400(%RSP),%ZMM1,%ZMM11	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM10,%ZMM5,%ZMM11	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VEXTRACTI128 $0x1,%YMM4,%XMM5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VEXTRACTI32X4 $0x3,%ZMM4,%XMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	4	1
VMOVAPD 0x2c0(%RSP),%ZMM10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VMOVQ %XMM4,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM4,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R12,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VPEXTRQ $0x1,%XMM9,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RCX,%R13,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVQ %XMM9,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVSD (%RCX,%R13,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM5,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RCX,%R12,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM5,%R12	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RCX,%R13,8),%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R12,8),%XMM5,%XMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VFMADD132PD 0x380(%RSP),%ZMM10,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x340(%RSP),%ZMM2,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VINSERTF128 $0x1,%XMM4,%YMM9,%YMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVSD (%RCX,%R15,8),%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RCX,%R14,8),%XMM9,%XMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VFMADD231PD 0x300(%RSP),%ZMM1,%ZMM3	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VINSERTF128 $0x1,%XMM5,%YMM9,%YMM5	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD 0x6c0(%RSP),%ZMM9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VINSERTF64X4 $0x1,%YMM4,%ZMM5,%ZMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	1
VMOVAPD 0xa00(%RSP),%ZMM5	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	1
VFMADD213PD %ZMM11,%ZMM4,%ZMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0x740(%RSP),%ZMM9,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD231PD 0x700(%RSP),%ZMM1,%ZMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD132PD 0xa40(%RSP),%ZMM5,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM7,%ZMM4,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VFMADD213PD %ZMM6,%ZMM4,%ZMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	1
VMULPD 0x9c0(%RSP),%ZMM1,%ZMM1	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	1
VMOVAPD (%RAX,%RBX,2),%YMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
ADD $0x10,%RBX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMULPD %ZMM30,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	1
VDIVPD %ZMM31,%ZMM2,%ZMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	13	9
VSCATTERDPD %ZMM1,(%RDX,%YMM4,8){%K1}	48	0	0	0	0	0	0	0	0	0	2.17	3.17	1.67	9	9	4-35	9
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VSCATTERDPD %ZMM2,(%R11,%YMM4,8){%K1}	48	0	0	0	0	0	0	0	0	0	2.17	3.17	1.67	9	9	4-35	9
KXNORW %K0,%K0,%K1	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	1	0.50
VSCATTERDPD %ZMM3,(%R8,%YMM4,8){%K1}	48	0	0	0	0	0	0	0	0	0	2.17	3.17	1.67	9	9	4-35	9
CMP %RBX,%R9	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 31790 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x610>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Gather/scatter instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code