OV - exec - Loop 447 - libqmcwfs.so

	Loop Id: 447	Module: libqmcwfs.so	Source: BsplineFunctor.h:246-260 [...]	Coverage: 0.02%

0x30cc0 VMULPD	(%R9,%RDI,1),%YMM0,%YMM2    [20]

0x30cc6 VMULPD	0x20(%R9,%RDI,1),%YMM0,%YMM5    [20]

0x30ccd ADD	$0x40,%RDI

0x30cd1 VCVTTPD2DQ	%YMM2,%XMM10

0x30cd5 VCVTTPD2DQ	%YMM5,%XMM4

0x30cd9 VROUNDPD	$0xb,%YMM2,%YMM6

0x30cdf VROUNDPD	$0xb,%YMM5,%YMM13

0x30ce5 VPMOVSXDQ	%XMM10,%YMM7

0x30cea VPMOVSXDQ	%XMM4,%YMM8

0x30cef VSUBPD	%YMM6,%YMM2,%YMM16

0x30cf5 VSUBPD	%YMM13,%YMM5,%YMM13

0x30cfa VPCMPEQD	%XMM6,%XMM6,%XMM6

0x30cfe VMOVQ	%XMM7,%R10

0x30d03 VPEXTRQ	$0x1,%XMM7,%R11

0x30d09 VEXTRACTI128	$0x1,%YMM7,%XMM7

0x30d0f VMOVQ	%XMM8,%R8

0x30d14 VPEXTRQ	$0x1,%XMM8,%R15

0x30d1a VPEXTRQ	$0x1,%XMM7,%RBX

0x30d20 VMOVQ	%XMM7,%R14

0x30d25 VEXTRACTI128	$0x1,%YMM8,%XMM7

0x30d2b VMOVSD	(%RAX,%R10,8),%XMM8    [8]

0x30d31 VMULPD	%YMM16,%YMM16,%YMM2

0x30d37 VMULPD	%YMM13,%YMM13,%YMM14

0x30d3c VMOVQ	%XMM7,%R12

0x30d41 VPEXTRQ	$0x1,%XMM7,%R13

0x30d47 VMOVSD	(%RAX,%R14,8),%XMM7    [7]

0x30d4d VMOVHPD	(%RAX,%R11,8),%XMM8,%XMM8    [12]

0x30d53 VMOVHPD	(%RAX,%RBX,8),%XMM7,%XMM7    [32]

0x30d58 VMULPD	%YMM16,%YMM2,%YMM5

0x30d5e VMULPD	%YMM13,%YMM14,%YMM3

0x30d63 VINSERTF128	$0x1,%XMM7,%YMM8,%YMM7

0x30d69 VMOVAPD	%YMM18,%YMM8

0x30d6f VFMADD213PD	%YMM20,%YMM2,%YMM8

0x30d75 VFMADD231PD	%YMM16,%YMM19,%YMM8

0x30d7b VFMADD231PD	%YMM17,%YMM5,%YMM8

0x30d81 VFMADD213PD	%YMM1,%YMM7,%YMM8

0x30d86 VMOVSD	(%RAX,%R12,8),%XMM1    [6]

0x30d8c VMOVSD	(%RAX,%R8,8),%XMM7    [2]

0x30d92 VMOVHPD	(%RAX,%R13,8),%XMM1,%XMM1    [19]

0x30d98 VMOVHPD	(%RAX,%R15,8),%XMM7,%XMM7    [26]

0x30d9e VINSERTF128	$0x1,%XMM1,%YMM7,%YMM1

0x30da4 VMOVAPD	%YMM18,%YMM7

0x30daa VFMADD213PD	%YMM20,%YMM14,%YMM7

0x30db0 VFMADD231PD	%YMM13,%YMM19,%YMM7

0x30db6 VFMADD231PD	%YMM17,%YMM3,%YMM7

0x30dbc VFMADD213PD	%YMM15,%YMM1,%YMM7

0x30dc1 VPSUBD	%XMM6,%XMM10,%XMM1

0x30dc5 VPSUBD	%XMM6,%XMM4,%XMM15

0x30dc9 VMOVAPD	%YMM3,%YMM6

0x30dcd VFMADD213PD	%YMM28,%YMM25,%YMM6

0x30dd3 VPMOVSXDQ	%XMM1,%YMM1

0x30dd8 VPMOVSXDQ	%XMM15,%YMM15

0x30ddd VMOVQ	%XMM1,%R10

0x30de2 VPEXTRQ	$0x1,%XMM1,%R11

0x30de8 VEXTRACTI128	$0x1,%YMM1,%XMM1

0x30dee VMOVQ	%XMM15,%R8

0x30df3 VPEXTRQ	$0x1,%XMM15,%R15

0x30df9 VMOVQ	%XMM1,%RBX

0x30dfe VPEXTRQ	$0x1,%XMM1,%R14

0x30e04 VEXTRACTI128	$0x1,%YMM15,%XMM1

0x30e0a VMOVSD	(%RAX,%R10,8),%XMM15    [29]

0x30e10 VFMADD231PD	%YMM14,%YMM26,%YMM6

0x30e16 VMOVQ	%XMM1,%R12

0x30e1b VPEXTRQ	$0x1,%XMM1,%R13

0x30e21 VMOVSD	(%RAX,%RBX,8),%XMM1    [28]

0x30e26 VMOVHPD	(%RAX,%R11,8),%XMM15,%XMM15    [11]

0x30e2c VMOVHPD	(%RAX,%R14,8),%XMM1,%XMM1    [23]

0x30e32 VFMADD231PD	%YMM13,%YMM27,%YMM6

0x30e38 VINSERTF128	$0x1,%XMM1,%YMM15,%YMM1

0x30e3e VMOVAPD	%YMM5,%YMM15

0x30e42 VFMADD213PD	%YMM24,%YMM21,%YMM15

0x30e48 VFMADD231PD	%YMM2,%YMM22,%YMM15

0x30e4e VFMADD231PD	%YMM16,%YMM23,%YMM15

0x30e54 VFMADD213PD	%YMM8,%YMM1,%YMM15

0x30e59 VMOVSD	(%RAX,%R12,8),%XMM1    [27]

0x30e5f VMOVSD	(%RAX,%R8,8),%XMM8    [30]

0x30e65 VMOVHPD	(%RAX,%R13,8),%XMM1,%XMM1    [18]

0x30e6b VMOVHPD	(%RAX,%R15,8),%XMM8,%XMM8    [25]

0x30e71 VINSERTF128	$0x1,%XMM1,%YMM8,%YMM1

0x30e77 VMOVAPD	%YMM3,%YMM8

0x30e7b VFMADD213PD	%YMM24,%YMM21,%YMM8

0x30e81 VFMADD213PD	%YMM9,%YMM29,%YMM3

0x30e87 VFMADD231PD	%YMM14,%YMM22,%YMM8

0x30e8d VFMADD231PD	%YMM14,%YMM30,%YMM3

0x30e93 VFMADD231PD	%YMM13,%YMM23,%YMM8

0x30e99 VFMADD231PD	%YMM13,%YMM31,%YMM3

0x30e9f VFMADD213PD	%YMM7,%YMM1,%YMM8

0x30ea4 VPADDD	%XMM11,%XMM10,%XMM1

0x30ea9 VPADDD	%XMM4,%XMM11,%XMM7

0x30ead VPADDD	%XMM4,%XMM12,%XMM4

0x30eb1 VPMOVSXDQ	%XMM1,%YMM1

0x30eb6 VPMOVSXDQ	%XMM7,%YMM7

0x30ebb VPMOVSXDQ	%XMM4,%YMM4

0x30ec0 VPEXTRQ	$0x1,%XMM1,%R10

0x30ec6 VMOVQ	%XMM1,%R11

0x30ecb VEXTRACTI128	$0x1,%YMM1,%XMM1

0x30ed1 VMOVQ	%XMM7,%R8

0x30ed6 VPEXTRQ	$0x1,%XMM7,%R15

0x30edc VMOVQ	%XMM1,%RBX

0x30ee1 VPEXTRQ	$0x1,%XMM1,%R14

0x30ee7 VEXTRACTI128	$0x1,%YMM7,%XMM1

0x30eed VMOVSD	(%RAX,%R11,8),%XMM7    [15]

0x30ef3 VMOVQ	%XMM1,%R12

0x30ef8 VPEXTRQ	$0x1,%XMM1,%R13

0x30efe VMOVSD	(%RAX,%RBX,8),%XMM1    [14]

0x30f03 VMOVHPD	(%RAX,%R10,8),%XMM7,%XMM7    [10]

0x30f09 VPEXTRQ	$0x1,%XMM4,%R10

0x30f0f VMOVHPD	(%RAX,%R14,8),%XMM1,%XMM1    [22]

0x30f15 VINSERTF128	$0x1,%XMM1,%YMM7,%YMM1

0x30f1b VMOVAPD	%YMM5,%YMM7

0x30f1f VFMADD213PD	%YMM28,%YMM25,%YMM7

0x30f25 VFMADD213PD	%YMM9,%YMM29,%YMM5

0x30f2b VFMADD231PD	%YMM2,%YMM26,%YMM7

0x30f31 VFMADD231PD	%YMM2,%YMM30,%YMM5

0x30f37 VFMADD231PD	%YMM16,%YMM27,%YMM7

0x30f3d VFMADD231PD	%YMM16,%YMM31,%YMM5

0x30f43 VFMADD213PD	%YMM15,%YMM1,%YMM7

0x30f48 VMOVSD	(%RAX,%R8,8),%XMM15    [33]

0x30f4e VMOVSD	(%RAX,%R12,8),%XMM1    [13]

0x30f54 VMOVQ	%XMM4,%R8

0x30f59 VMOVHPD	(%RAX,%R13,8),%XMM1,%XMM1    [17]

0x30f5f VMOVHPD	(%RAX,%R15,8),%XMM15,%XMM15    [24]

0x30f65 VINSERTF128	$0x1,%XMM1,%YMM15,%YMM1

0x30f6b VMOVAPD	%YMM3,%YMM15

0x30f6f VFMADD213PD	%YMM8,%YMM1,%YMM6

0x30f74 VPADDD	%XMM12,%XMM10,%XMM1

0x30f79 VPMOVSXDQ	%XMM1,%YMM1

0x30f7e VMOVQ	%XMM1,%R11

0x30f83 VPEXTRQ	$0x1,%XMM1,%RBX

0x30f89 VEXTRACTI128	$0x1,%YMM1,%XMM1

0x30f8f VPEXTRQ	$0x1,%XMM1,%R14

0x30f95 VMOVQ	%XMM1,%R15

0x30f9a VEXTRACTI128	$0x1,%YMM4,%XMM1

0x30fa0 VMOVSD	(%RAX,%R11,8),%XMM4    [5]

0x30fa6 VMOVQ	%XMM1,%R12

0x30fab VPEXTRQ	$0x1,%XMM1,%R13

0x30fb1 VMOVSD	(%RAX,%R15,8),%XMM1    [4]

0x30fb7 VMOVHPD	(%RAX,%RBX,8),%XMM4,%XMM4    [31]

0x30fbc VMOVHPD	(%RAX,%R14,8),%XMM1,%XMM1    [21]

0x30fc2 VMOVSD	(%RAX,%R12,8),%XMM2    [3]

0x30fc8 VMOVHPD	(%RAX,%R13,8),%XMM2,%XMM2    [16]

0x30fce VINSERTF128	$0x1,%XMM1,%YMM4,%YMM4

0x30fd4 VMOVAPD	%YMM5,%YMM1

0x30fd8 VFMADD213PD	%YMM7,%YMM4,%YMM1

0x30fdd VMOVSD	(%RAX,%R8,8),%XMM4    [1]

0x30fe3 VMOVHPD	(%RAX,%R10,8),%XMM4,%XMM4    [9]

0x30fe9 VINSERTF128	$0x1,%XMM2,%YMM4,%YMM2

0x30fef VFMADD213PD	%YMM6,%YMM2,%YMM15

0x30ff4 CMP	%RDI,%RSI

0x30ff7 JNE	30cc0

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1064 - 1064

--------------------------------------------------------------------------------

1064: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 246 - 260

--------------------------------------------------------------------------------

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	0.84
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source	stl_vector.h:1064-1064,BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.83
CQA cycles if no scalar integer	27.83
CQA cycles if FP arith vectorized	33.00
CQA cycles if fully vectorized	20.00
Front-end cycles	27.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	11.33
P5 cycles	11.33
P6 cycles	11.33
P7 cycles	27.25
P8 cycles	27.25
P9 cycles	27.25
P10 cycles	27.25
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	150.00
Nb uops	167.00
Nb loads	34.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.35
Nb FLOP add-sub	8.00
Nb FLOP mul	24.00
Nb FLOP fma	128.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.50
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	56.46
Vectorization ratio load	5.88
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.62
Vector-efficiency ratio all	28.40
Vector-efficiency ratio load	14.71
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.55

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	0.84
CQA speedup if fully vectorized	1.39
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.02
Bottlenecks	micro-operation queue,
Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source	stl_vector.h:1064-1064,BsplineFunctor.h:246-260
Source loop unroll info	unrolled by 8
Source loop unroll confidence level	medium
Unroll/vectorization loop type	main
Unroll factor	8
CQA cycles	27.83
CQA cycles if no scalar integer	27.83
CQA cycles if FP arith vectorized	33.00
CQA cycles if fully vectorized	20.00
Front-end cycles	27.83
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	0.25
P2 cycles	0.25
P3 cycles	0.50
P4 cycles	11.33
P5 cycles	11.33
P6 cycles	11.33
P7 cycles	27.25
P8 cycles	27.25
P9 cycles	27.25
P10 cycles	27.25
P11 cycles	16.00
P12 cycles	16.00
P13 cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	150.00
Nb uops	167.00
Nb loads	34.00
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	10.35
Nb FLOP add-sub	8.00
Nb FLOP mul	24.00
Nb FLOP fma	128.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	11.50
Bytes prefetched	0.00
Bytes loaded	320.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	1.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	8.00
Vectorization ratio all	56.46
Vectorization ratio load	5.88
Vectorization ratio store	NA
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	NA
Vectorization ratio other	53.62
Vector-efficiency ratio all	28.40
Vector-efficiency ratio load	14.71
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	50.00
Vector-efficiency ratio add_sub	31.25
Vector-efficiency ratio fma	50.00
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	23.55

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source file and lines	BsplineFunctor.h:246-260
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. Only 28% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 27.83 to 20.00 cycles (1.39x speedup).

Details

56% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 128 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences
VPEXTRQ: 16 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 8 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (128 inside FMA instructions)
152: multiply (128 inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	150
nb uops	167
loop length	829
used x86 registers	12
used mmx registers	0
used xmm registers	10
used ymm registers	29
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	27.83 cycles
front end	27.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	11.33	11.33	11.33	27.25	27.25	27.25	27.25	16.00	16.00
cycles	0.50	0.50	0.25	0.25	0.50	11.33	11.33	11.33	27.25	27.25	27.25	27.25	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	27.83
Dispatch	27.25
Data deps.	16.00
Overall L1	27.83

Vectorization ratios

INT

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	65%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	56%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	34%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	28%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	31%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.83 cycles. At this rate:

11% of peak load performance is reached (11.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 30cc0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMULPD (%R9,%RDI,1),%YMM0,%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMULPD 0x20(%R9,%RDI,1),%YMM0,%YMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADD $0x40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTTPD2DQ %YMM2,%XMM10	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67
VCVTTPD2DQ %YMM5,%XMM4	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67
VROUNDPD $0xb,%YMM2,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VROUNDPD $0xb,%YMM5,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPMOVSXDQ %XMM10,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM4,%YMM8	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VSUBPD %YMM6,%YMM2,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %YMM13,%YMM5,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPCMPEQD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM7,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM7,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM7,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM8,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VPEXTRQ $0x1,%XMM7,%RBX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM7,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI128 $0x1,%YMM8,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R10,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULPD %YMM16,%YMM16,%YMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULPD %YMM13,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVQ %XMM7,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM7,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R14,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RBX,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %YMM16,%YMM2,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULPD %YMM13,%YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VINSERTF128 $0x1,%XMM7,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM18,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM20,%YMM2,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM19,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM17,%YMM5,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM1,%YMM7,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R15,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM7,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM18,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM20,%YMM14,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM13,%YMM19,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM17,%YMM3,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM15,%YMM1,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPSUBD %XMM6,%XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPSUBD %XMM6,%XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVAPD %YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM28,%YMM25,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VMOVQ %XMM1,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM15,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM15,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231PD %YMM14,%YMM26,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%RBX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM15,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R14,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VFMADD231PD %YMM13,%YMM27,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM5,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM24,%YMM21,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM2,%YMM22,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM23,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM8,%YMM1,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R15,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM8,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM3,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM24,%YMM21,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM9,%YMM29,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM14,%YMM22,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM14,%YMM30,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM13,%YMM23,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM13,%YMM31,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM7,%YMM1,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPADDD %XMM11,%XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPADDD %XMM4,%XMM11,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPADDD %XMM4,%XMM12,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPEXTRQ $0x1,%XMM1,%R10	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM7,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM7,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM7,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R11,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%RBX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R10,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM4,%R10	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RAX,%R14,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM7,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM5,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM28,%YMM25,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM9,%YMM29,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM2,%YMM26,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM2,%YMM30,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM27,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM31,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM15,%YMM1,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R8,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R15,8),%XMM15,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM3,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM8,%YMM1,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPADDD %XMM12,%XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VMOVQ %XMM1,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%RBX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPEXTRQ $0x1,%XMM1,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI128 $0x1,%YMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R11,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R15,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RBX,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R14,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R12,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R13,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM5,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM7,%YMM4,%YMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R8,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R10,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VFMADD213PD %YMM6,%YMM2,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
CMP %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 30cc0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x200>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Function	_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd
Source file and lines	BsplineFunctor.h:246-260
Module	libqmcwfs.so

The loop is defined in:

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1064
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:246-260

It is main loop of related source loop which is unrolled by 8 (including vectorization).

gain
potential
hint
expert

Vectorization

Details

56% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

5% of SSE/AVX loads are used in vector version.
53% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

FMA

Detected 128 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Complex instructions

Detected COMPLEX INSTRUCTIONS.

Details

These instructions generate more than one micro-operation and only one of them can be decoded during a cycle and the extra micro-operations increase pressure on execution units.

VCVTTPD2DQ: 2 occurrences
VPEXTRQ: 16 occurrences

Slow data structures access

Detected data structures (typically arrays) that cannot be efficiently read/written

Details

Irregular (variable stride) or indirect: 8 occurrence(s)

Non-unit stride (uncontiguous) accesses are not efficiently using data caches

Workaround

Try to remove indirect accesses. If applicable, precompute elements out of the innermost loop.

Vector unaligned load/store instructions

Detected 8 suboptimal vector unaligned load/store instructions.

Details

VINSERTF128: 8 occurrences

Workaround

Pass to your compiler a micro-architecture specialization option:
- use march=native
Use vector aligned instructions:
1. align your arrays on 64 bytes boundaries: replace { void *p = malloc (size); } with { void *p; posix_memalign (&p, 64, size); }.
2. inform your compiler that your arrays are vector aligned: if array 'foo' is 64 bytes-aligned, define a pointer 'p_foo' as __builtin_assume_aligned (foo, 64) and use it instead of 'foo' in the loop.

Conversion instructions

Detected expensive conversion instructions.

Details

VCVTTPD2DQ (FP64 to INT32, SIMD): 2 occurrences

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Type of elements and instruction set

42 AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (four at a time).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 288 FP arithmetical operations:

136: addition or subtraction (128 inside FMA instructions)
152: multiply (128 inside FMA instructions)

The binary loop is loading 320 bytes (40 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.90 FP operations per loaded or stored byte.

General properties

nb instructions	150
nb uops	167
loop length	829
used x86 registers	12
used mmx registers	0
used xmm registers	10
used ymm registers	29
used zmm registers	0
nb stack references	0
ADD-SUB / MUL ratio	0.33

Front-end

ASSUMED MACRO FUSION FIT IN UOP CACHE

micro-operation queue	27.83 cycles
front end	27.83 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	0.50	0.50	0.25	0.25	0.50	11.33	11.33	11.33	27.25	27.25	27.25	27.25	16.00	16.00
cycles	0.50	0.50	0.25	0.25	0.50	11.33	11.33	11.33	27.25	27.25	27.25	27.25	16.00	16.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	27.83
Dispatch	27.25
Data deps.	16.00
Overall L1	27.83

Vectorization ratios

INT

all	41%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	34%

all	65%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	100%

INT+FP

all	56%
load	5%
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	53%

Vector efficiency ratios

INT

all	17%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	25%
fma	NA (no fma vectorizable/vectorized instructions)
other	16%

all	34%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	50%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	40%

INT+FP

all	28%
load	14%
store	NA (no store vectorizable/vectorized instructions)
mul	50%
add-sub	31%
fma	50%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	23%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 27.83 cycles. At this rate:

11% of peak load performance is reached (11.50 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck).

ASM code

In the binary file, the address of the loop is: 30cc0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
VMULPD (%R9,%RDI,1),%YMM0,%YMM2	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
VMULPD 0x20(%R9,%RDI,1),%YMM0,%YMM5	1	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	0	0	0	0	3	0.50
ADD $0x40,%RDI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VCVTTPD2DQ %YMM2,%XMM10	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67
VCVTTPD2DQ %YMM5,%XMM4	2	0	0	0	0	0	0	0	0	0	0.50	1	0.50	0	0	6	0.67
VROUNDPD $0xb,%YMM2,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VROUNDPD $0xb,%YMM5,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPMOVSXDQ %XMM10,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM4,%YMM8	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VSUBPD %YMM6,%YMM2,%YMM16	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VSUBPD %YMM13,%YMM5,%YMM13	1	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	3	0.50
VPCMPEQD %XMM6,%XMM6,%XMM6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM7,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM7,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM7,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM8,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM8,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VPEXTRQ $0x1,%XMM7,%RBX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM7,%R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI128 $0x1,%YMM8,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R10,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMULPD %YMM16,%YMM16,%YMM2	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULPD %YMM13,%YMM13,%YMM14	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMOVQ %XMM7,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM7,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R14,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%RBX,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMULPD %YMM16,%YMM2,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VMULPD %YMM13,%YMM14,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	3	0.50
VINSERTF128 $0x1,%XMM7,%YMM8,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM18,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM20,%YMM2,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM19,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM17,%YMM5,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM1,%YMM7,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R15,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM7,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM18,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM20,%YMM14,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM13,%YMM19,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM17,%YMM3,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM15,%YMM1,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPSUBD %XMM6,%XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPSUBD %XMM6,%XMM4,%XMM15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVAPD %YMM3,%YMM6	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM28,%YMM25,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM15,%YMM15	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VMOVQ %XMM1,%R10	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R11	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM15,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM15,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM15,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R10,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VFMADD231PD %YMM14,%YMM26,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%RBX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R11,8),%XMM15,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R14,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VFMADD231PD %YMM13,%YMM27,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM5,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM24,%YMM21,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM2,%YMM22,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM23,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM8,%YMM1,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R8,8),%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R15,8),%XMM8,%XMM8	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM8,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM3,%YMM8	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM24,%YMM21,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM9,%YMM29,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM14,%YMM22,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM14,%YMM30,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM13,%YMM23,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM13,%YMM31,%YMM3	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM7,%YMM1,%YMM8	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPADDD %XMM11,%XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPADDD %XMM4,%XMM11,%XMM7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPADDD %XMM4,%XMM12,%XMM4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM7,%YMM7	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPMOVSXDQ %XMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VPEXTRQ $0x1,%XMM1,%R10	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVQ %XMM7,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM7,%R15	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM7,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R11,8),%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%RBX,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R10,8),%XMM7,%XMM7	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VPEXTRQ $0x1,%XMM4,%R10	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVHPD (%RAX,%R14,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM7,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM5,%YMM7	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM28,%YMM25,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM9,%YMM29,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM2,%YMM26,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM2,%YMM30,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM27,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD231PD %YMM16,%YMM31,%YMM5	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VFMADD213PD %YMM15,%YMM1,%YMM7	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R8,8),%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD (%RAX,%R12,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM4,%R8	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VMOVHPD (%RAX,%R13,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R15,8),%XMM15,%XMM15	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM15,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM3,%YMM15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM8,%YMM1,%YMM6	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VPADDD %XMM12,%XMM10,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPMOVSXDQ %XMM1,%YMM1	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	2	0.50
VMOVQ %XMM1,%R11	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%RBX	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VEXTRACTI128 $0x1,%YMM1,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VPEXTRQ $0x1,%XMM1,%R14	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVQ %XMM1,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VEXTRACTI128 $0x1,%YMM4,%XMM1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	1	0.25
VMOVSD (%RAX,%R11,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVQ %XMM1,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	1	1
VPEXTRQ $0x1,%XMM1,%R13	2	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0.50	0.50	6	1
VMOVSD (%RAX,%R15,8),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%RBX,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVHPD (%RAX,%R14,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VMOVSD (%RAX,%R12,8),%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R13,8),%XMM2,%XMM2	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM1,%YMM4,%YMM4	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VMOVAPD %YMM5,%YMM1	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VFMADD213PD %YMM7,%YMM4,%YMM1	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
VMOVSD (%RAX,%R8,8),%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVHPD (%RAX,%R10,8),%XMM4,%XMM4	1	0	0	0	0	0	0.33	0.33	0.33	0	0.33	0.33	0.33	0	0	9	0.50
VINSERTF128 $0x1,%XMM2,%YMM4,%YMM2	1	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	1	0.50
VFMADD213PD %YMM6,%YMM2,%YMM15	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	4	0.50
CMP %RDI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
JNE 30cc0 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x200>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

FMA

Workaround

Complex instructions

Details

Slow data structures access

Details

Workaround

Vector unaligned load/store instructions

Details

Workaround

Conversion instructions

Details

Workaround

Type of elements and instruction set

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code