OV - exec - Function _ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5

	Function: _ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEER ...	Module: libqmcwfs.so	Source: SPOSet.h:81-88 [...]	Coverage: 0.4%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 83

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 178

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h: 1046 - 1046

--------------------------------------------------------------------------------

1046: 	return *(this->_M_impl._M_start + __n);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 81 - 88

--------------------------------------------------------------------------------

81:   {

82:     assert(psi.size() == psiinv.size());

83:     for (int iat = 0; iat < VP.getTotalNum(); ++iat)

84:     {

85:       evaluate(VP, iat, psi);

86:       ratios[iat] = simd::dot(psi.data(), psiinv.data(), psi.size());

87:     }

88:   }

0x11ac0 PUSH	%RBP

0x11ac1 MOV	%RSP,%RBP

0x11ac4 PUSH	%R15

0x11ac6 PUSH	%R14

0x11ac8 PUSH	%R13

0x11aca PUSH	%R12

0x11acc PUSH	%RBX

0x11acd PUSH	%RAX

0x11ace CMPQ	$0,0x260(%RSI)

0x11ad6 MOV	%RCX,-0x30(%RBP)

0x11ada JE	11c88

0x11ae0 MOV	%R8,%RBX

0x11ae3 MOV	%RDX,%R15

0x11ae6 MOV	%RSI,%R12

0x11ae9 MOV	%RDI,%R13

0x11aec XOR	%R14D,%R14D

0x11aef JMP	11b1e

0x11af1 NOPW	%CS:(%RAX,%RAX,1)

(7) 0x11b00 VXORPD	%XMM0,%XMM0,%XMM0

(7) 0x11b04 MOV	(%RBX),%RAX

(7) 0x11b07 VMOVSD	%XMM0,(%RAX,%R14,8)

(7) 0x11b0d INC	%R14

(7) 0x11b10 CMP	%R14,0x260(%R12)

(7) 0x11b18 JBE	11c88

(7) 0x11b1e MOV	(%R13),%RAX

(7) 0x11b22 MOV	%R13,%RDI

(7) 0x11b25 MOV	%R12,%RSI

(7) 0x11b28 MOV	%R14D,%EDX

(7) 0x11b2b MOV	%R15,%RCX

(7) 0x11b2e VZEROUPPER

(7) 0x11b31 CALLQ	0x10(%RAX)

(7) 0x11b34 MOV	0x8(%R15),%RDX

(7) 0x11b38 TEST	%EDX,%EDX

(7) 0x11b3a JLE	11b00

(7) 0x11b3c MOV	-0x30(%RBP),%RCX

(7) 0x11b40 MOV	0x18(%R15),%RAX

(7) 0x11b44 MOV	%EDX,%EDX

(7) 0x11b46 MOV	0x18(%RCX),%RCX

(7) 0x11b4a CMP	$0x4,%EDX

(7) 0x11b4d JAE	11b60

(7) 0x11b4f VXORPD	%XMM0,%XMM0,%XMM0

(7) 0x11b53 XOR	%ESI,%ESI

(7) 0x11b55 JMP	11c70

0x11b5a NOPW	(%RAX,%RAX,1)

(7) 0x11b60 CMP	$0x20,%EDX

(7) 0x11b63 JAE	11b70

(7) 0x11b65 VXORPD	%XMM0,%XMM0,%XMM0

(7) 0x11b69 XOR	%ESI,%ESI

(7) 0x11b6b JMP	11c18

(7) 0x11b70 MOV	%EDX,%EDI

(7) 0x11b72 MOV	%EDX,%ESI

(7) 0x11b74 AND	$0x1f,%EDI

(7) 0x11b77 AND	$-0x20,%ESI

(7) 0x11b7a VXORPD	%XMM0,%XMM0,%XMM0

(7) 0x11b7e VXORPD	%XMM1,%XMM1,%XMM1

(7) 0x11b82 VXORPD	%XMM2,%XMM2,%XMM2

(7) 0x11b86 VXORPD	%XMM3,%XMM3,%XMM3

(7) 0x11b8a XOR	%R8D,%R8D

(7) 0x11b8d NOPL	(%RAX)

  (8) 0x11b90 VMOVUPD	(%RCX,%R8,8),%ZMM4

  (8) 0x11b97 VMOVUPD	0x40(%RCX,%R8,8),%ZMM5

  (8) 0x11b9f VMOVUPD	0x80(%RCX,%R8,8),%ZMM6

  (8) 0x11ba7 VMOVUPD	0xc0(%RCX,%R8,8),%ZMM7

  (8) 0x11baf VFMADD231PD	(%RAX,%R8,8),%ZMM4,%ZMM0

  (8) 0x11bb6 VFMADD231PD	0x40(%RAX,%R8,8),%ZMM5,%ZMM1

  (8) 0x11bbe VFMADD231PD	0x80(%RAX,%R8,8),%ZMM6,%ZMM2

  (8) 0x11bc6 VFMADD231PD	0xc0(%RAX,%R8,8),%ZMM7,%ZMM3

  (8) 0x11bce ADD	$0x20,%R8

  (8) 0x11bd2 CMP	%R8,%RSI

  (8) 0x11bd5 JNE	11b90

(7) 0x11bd7 VADDPD	%ZMM0,%ZMM1,%ZMM0

(7) 0x11bdd VADDPD	%ZMM2,%ZMM3,%ZMM2

(7) 0x11be3 VADDPD	%ZMM0,%ZMM2,%ZMM0

(7) 0x11be9 VEXTRACTF64X4	$0x1,%ZMM0,%YMM1

(7) 0x11bf0 VADDPD	%ZMM1,%ZMM0,%ZMM0

(7) 0x11bf6 VEXTRACTF128	$0x1,%YMM0,%XMM1

(7) 0x11bfc VADDPD	%XMM1,%XMM0,%XMM0

(7) 0x11c00 VPERMILPD	$0x1,%XMM0,%XMM1

(7) 0x11c06 VADDSD	%XMM1,%XMM0,%XMM0

(7) 0x11c0a TEST	%RDI,%RDI

(7) 0x11c0d JE	11b04

(7) 0x11c13 CMP	$0x4,%EDI

(7) 0x11c16 JB	11c70

(7) 0x11c18 MOV	%EDX,%EDI

(7) 0x11c1a MOV	%RSI,%R8

(7) 0x11c1d MOV	%EDX,%ESI

(7) 0x11c1f AND	$0x3,%EDI

(7) 0x11c22 AND	$-0x4,%ESI

(7) 0x11c25 VMOVQ	%XMM0,%XMM0

(7) 0x11c29 NOPL	(%RAX)

  (10) 0x11c30 VMOVUPD	(%RCX,%R8,8),%YMM1

  (10) 0x11c36 VFMADD231PD	(%RAX,%R8,8),%YMM1,%YMM0

  (10) 0x11c3c ADD	$0x4,%R8

  (10) 0x11c40 CMP	%R8,%RSI

  (10) 0x11c43 JNE	11c30

(7) 0x11c45 VEXTRACTF128	$0x1,%YMM0,%XMM1

(7) 0x11c4b VADDPD	%XMM1,%XMM0,%XMM0

(7) 0x11c4f VPERMILPD	$0x1,%XMM0,%XMM1

(7) 0x11c55 VADDSD	%XMM1,%XMM0,%XMM0

(7) 0x11c59 TEST	%RDI,%RDI

(7) 0x11c5c JE	11b04

(7) 0x11c62 NOPW	%CS:(%RAX,%RAX,1)

  (9) 0x11c70 VMOVSD	(%RCX,%RSI,8),%XMM1

  (9) 0x11c75 VFMADD231SD	(%RAX,%RSI,8),%XMM1,%XMM0

  (9) 0x11c7b INC	%RSI

  (9) 0x11c7e CMP	%RSI,%RDX

  (9) 0x11c81 JNE	11c70

(7) 0x11c83 JMP	11b04

0x11c88 ADD	$0x8,%RSP

0x11c8c POP	%RBX

0x11c8d POP	%R12

0x11c8f POP	%R13

0x11c91 POP	%R14

0x11c93 POP	%R15

0x11c95 POP	%RBP

0x11c96 VZEROUPPER

0x11c99 RET

0x11c9a INT	$0x3

0x11c9b INT	$0x3

0x11c9c INT	$0x3

0x11c9d INT	$0x3

0x11c9e INT	$0x3

0x11c9f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	SPOSet.h:81-88
Module	libqmcwfs.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:81-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is probably not vectorized. Only 13% of vector register length is used (average across all SSE/AVX instructions). By vectorizing your function, you can lower the cost of an iteration from 4.33 to 0.31 cycles (13.95x speedup).

Details

Store and arithmetical SSE/AVX instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	34
nb uops	26
loop length	94
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.33
Dispatch	1.50
Overall L1	4.33

Vectorization ratios

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.33 cycles. At this rate:

1% of peak load performance is reached (1.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.85 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Performance is limited by instruction throughput (loading/decoding program instructions to execution core) (front-end is a bottleneck). By removing all these bottlenecks, you can lower the cost of an iteration from 4.33 to 1.50 cycles (2.89x speedup).

ASM code

In the binary file, the address of the function is: 11ac0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMPQ $0,0x260(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 11c88 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 11b1e <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x5e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Source file and lines	SPOSet.h:81-88
Module	libqmcwfs.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178
/usr/lib/gcc/x86_64-redhat-linux/11/../../../../include/c++/11/bits/stl_vector.h:1046
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:81-88

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Found no such bottlenecks but see expert reports for more complex bottlenecks.

No data for this section

Type of elements and instruction set

No instructions are processing arithmetic or math operations on FP elements. This function is probably writing/copying data or processing integer elements.

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 8 bytes. The binary function is storing 8 bytes.

General properties

nb instructions	34
nb uops	26
loop length	94
used x86 registers	13
used mmx registers	0
used xmm registers	0
used ymm registers	0
used zmm registers	0
nb stack references	1

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	4.33 cycles
front end	4.33 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00
cycles	1.50	0.75	0.75	0.50	1.50	0.67	0.67	0.67	0.00	0.00	0.00	0.00	0.00	0.00

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.33
Dispatch	1.50
Overall L1	4.33

Vectorization ratios

all	12%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	14%

Vector efficiency ratios

all	13%
load	12%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	13%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.33 cycles. At this rate:

1% of peak load performance is reached (1.85 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
2% of peak store performance is reached (1.85 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

ASM code

In the binary file, the address of the function is: 11ac0

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
PUSH %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
PUSH %RAX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
CMPQ $0,0x260(%RSI)	1	0.25	0.25	0.25	0.25	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.33
MOV %RCX,-0x30(%RBP)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
JE 11c88 <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x1c8>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50-1
MOV %R8,%RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDX,%R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RSI,%R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %RDI,%R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
XOR %R14D,%R14D	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.25
JMP 11b1e <_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E+0x5e>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
NOPW %CS:(%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
NOPW (%RAX,%RAX,1)	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.09
ADD $0x8,%RSP	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
POP %RBX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R12	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R13	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R14	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %R15	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
VZEROUPPER	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1
RET	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	1	0.50
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3
INT $0x3

Name	Coverage (%)	Time (s)
▼_ZN11qmcplusplus6SPOSet17evaluateDetRatiosERKNS_18VirtualParticleSetERNS_6VectorIdSaIdEEERKS6_RSt6vectorIdS5_E–	0.4	0.81
▼Loop 7 - inner_product.hpp:82-83 - libqmcwfs.so–	0.04	0.07
○Loop 8 - inner_product.hpp:82-83 - libqmcwfs.so	0.36	0.67
○Loop 9 - inner_product.hpp:82-83 - libqmcwfs.so	0	0
○Loop 10 - inner_product.hpp:82-83 - libqmcwfs.so	0	0

Report Configuration

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Vectorization

Details

Workaround

Execution units bottlenecks

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code