OV - exec - Function _ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS

	Function: _ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb	Module: libqmcparticle.so	Source: ParticleSet.cpp:264-268 [...]	Coverage: 0.01%

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

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223:     return X[i];

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp: 264 - 268

--------------------------------------------------------------------------------

264: {

265:   active_ptcl_     = iat;

266:   active_pos_      = R[iat] + displ;

267:   active_spin_val_ = spins[iat];

268:   computeNewPosDistTables(iat, active_pos_, maybe_accept);

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 43 - 43

--------------------------------------------------------------------------------

43:     return (a + b);

0x3dc40 PUSH	%RBP

0x3dc41 MOV	%RSP,%RBP

0x3dc44 MOV	%ESI,0x124(%RDI)

0x3dc4a MOVSXD	%ESI,%RSI

0x3dc4d LEA	0x128(%RDI),%RAX

0x3dc54 MOV	0x40(%RDI),%R9

0x3dc58 LEA	(%RSI,%RSI,2),%R8

0x3dc5c VMOVSD	0x10(%RDX),%XMM0

0x3dc61 VMOVUPD	(%RDX),%XMM1

0x3dc65 MOV	0x68(%RDI),%R10

0x3dc69 MOV	%RAX,%RDX

0x3dc6c VADDSD	0x10(%R9,%R8,8),%XMM0,%XMM0

0x3dc73 VADDPD	(%R9,%R8,8),%XMM1,%XMM1

0x3dc79 VMOVUPD	%XMM1,0x128(%RDI)

0x3dc81 VMOVSD	%XMM0,0x138(%RDI)

0x3dc89 VMOVSD	(%R10,%RSI,8),%XMM0

0x3dc8f VMOVSD	%XMM0,0x140(%RDI)

0x3dc97 POP	%RBP

0x3dc98 JMP	40de0

0x3dc9d INT	$0x3

0x3dc9e INT	$0x3

0x3dc9f INT	$0x3

Path /

Average path: Display a virtual path defined by average values of all real paths

Source file and lines	ParticleSet.cpp:264-268
Module	libqmcparticle.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:264-268
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.67 to 2.67 cycles (1.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 14% of vector register length is used (average across all SSE/AVX instructions). By fully vectorizing your function, you can lower the cost of an iteration from 3.67 to 0.94 cycles (3.91x speedup).

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.67 to 3.17 cycles (1.16x speedup).

Workaround

Read less array elements
Write less array elements

No data for this section

Type of elements and instruction set

1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in scalar mode (one at a time). 1 SSE or AVX instructions are processing arithmetic or math operations on double precision FP elements in vector mode (two at a time).

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 72 bytes (9 double precision FP elements). The binary function is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	19
loop length	96
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	3.67	3.67	3.67	0.00	0.00	1.00	1.00	1.50	1.50
cycles	1.00	1.00	0.75	0.75	0.50	3.67	3.67	3.67	0.00	0.00	1.00	1.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.17
Dispatch	3.67
Overall L1	3.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	21%
load	28%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	17%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	16%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.67 cycles. At this rate:

20% of peak load performance is reached (19.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.82 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 3dc40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %ESI,0x124(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVSXD %ESI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x128(%RDI),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x40(%RDI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RSI,%RSI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x10(%RDX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVUPD (%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV 0x68(%RDI),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD 0x10(%R9,%R8,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDPD (%R9,%R8,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVUPD %XMM1,0x128(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVSD %XMM0,0x138(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R10,%RSI,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM0,0x140(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 40de0 <@plt_start@+0x480>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
INT $0x3
INT $0x3
INT $0x3

Source file and lines	ParticleSet.cpp:264-268
Module	libqmcparticle.so

The function is defined in:

/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.cpp:264-268
/beegfs/hackathon/users/eoseret/qaas_runs/170-855-3059/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:43

Warnings:

Ignoring paths for analysis
Failed to get the number of paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.67 to 2.67 cycles (1.38x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

21% of SSE/AVX instructions are used in vector version (process two or more data elements in vector registers):

28% of SSE/AVX loads are used in vector version.
25% of SSE/AVX stores are used in vector version.
50% of SSE/AVX addition or subtraction instructions are used in vector version.
0% of SSE/AVX instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Execution units bottlenecks

Performance is limited by:

reading data from caches/RAM (load units are a bottleneck)
writing data to caches/RAM (the store unit is a bottleneck)

By removing all these bottlenecks, you can lower the cost of an iteration from 3.67 to 3.17 cycles (1.16x speedup).

Workaround

Read less array elements
Write less array elements

No data for this section

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

The binary function is composed of 3 FP arithmetical operations:

3: addition or subtraction

The binary function is loading 72 bytes (9 double precision FP elements). The binary function is storing 36 bytes (4 double precision FP elements).

Arithmetic intensity

Arithmetic intensity is 0.03 FP operations per loaded or stored byte.

General properties

nb instructions	22
nb uops	19
loop length	96
used x86 registers	9
used mmx registers	0
used xmm registers	2
used ymm registers	0
used zmm registers	0
nb stack references	0

Front-end

MACRO FUSION NOT POSSIBLE FIT IN UOP CACHE

micro-operation queue	3.17 cycles
front end	3.17 cycles

Back-end

	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5
uops	1.00	1.00	0.75	0.75	0.50	3.67	3.67	3.67	0.00	0.00	1.00	1.00	1.50	1.50
cycles	1.00	1.00	0.75	0.75	0.50	3.67	3.67	3.67	0.00	0.00	1.00	1.00	1.50	1.50

Execution ports to units layout:

ALU0/BRU0: ALU
ALU1: ALU
ALU2: ALU
ALU3: ALU
BRU1:
AGU0 (256 bits): store address, load
AGU1 (256 bits): store address, load
AGU2 (256 bits): store address, load
FP0 (256 bits): VPU, DIV/SQRT
FP1 (256 bits): VPU, DIV/SQRT
FP2 (256 bits): VPU
FP3 (256 bits): VPU
FP4 (256 bits): FP store data
FP5 (256 bits): FP store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.17
Dispatch	3.67
Overall L1	3.67

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	37%
load	40%
store	33%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	21%
load	28%
store	25%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	50%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Vector efficiency ratios

INT

all	11%
load	12%
store	6%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	12%

all	17%
load	17%
store	16%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	16%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	18%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	12%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.67 cycles. At this rate:

20% of peak load performance is reached (19.64 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
15% of peak store performance is reached (9.82 out of 64.00 bytes stored per cycle (GB/s @ 1GHz))

Front-end bottlenecks

Found no such bottlenecks.

ASM code

In the binary file, the address of the function is: 3dc40

Instruction	Nb FU	ALU0/BRU0	ALU1	ALU2	ALU3	BRU1	AGU0	AGU1	AGU2	FP0	FP1	FP2	FP3	FP4	FP5	Latency	Recip. throughput
PUSH %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50
MOV %RSP,%RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
MOV %ESI,0x124(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	4	0.50
MOVSXD %ESI,%RSI	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
LEA 0x128(%RDI),%RAX	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
MOV 0x40(%RDI),%R9	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
LEA (%RSI,%RSI,2),%R8	1	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	0	0	0	1	0.25
VMOVSD 0x10(%RDX),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVUPD (%RDX),%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.50
MOV 0x68(%RDI),%R10	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	3	0.33
MOV %RAX,%RDX	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0.17
VADDSD 0x10(%R9,%R8,8),%XMM0,%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VADDPD (%R9,%R8,8),%XMM1,%XMM1	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0.50	0.50	0	0	3	0.50
VMOVUPD %XMM1,0x128(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	4	1
VMOVSD %XMM0,0x138(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
VMOVSD (%R10,%RSI,8),%XMM0	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0	0	1	0.50
VMOVSD %XMM0,0x140(%RDI)	1	0	0	0	0	0	0.33	0.33	0.33	0	0	0	0	0.50	0.50	1	1
POP %RBP	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.33
JMP 40de0 <@plt_start@+0x480>	1	0.50	0	0	0	0.50	0	0	0	0	0	0	0	0	0	0	1
INT $0x3
INT $0x3
INT $0x3

Name	Coverage (%)	Time (s)
○_ZN11qmcplusplus11ParticleSet8makeMoveEiRKNS_10TinyVectorIdLj3EEEb	0.01	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Execution units bottlenecks

Workaround

Type of elements and instruction set

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Vector efficiency ratios

Cycles and memory resources usage

Front-end bottlenecks

ASM code