Function: _intel_fast_memset | Module: exec | Source: :0-0 | Coverage: 0.01% |
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Function: _intel_fast_memset | Module: exec | Source: :0-0 | Coverage: 0.01% |
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*** This Panel is Intentionally Left Blank. *** It is due to a lack of debug symbols in the given object |
0x4e63c0 ENDBR64 |
0x4e63c4 MOV 0x89a85(%RIP),%RAX |
0x4e63cb TEST %RAX,%RAX |
0x4e63ce JE 4e63e0 |
0x4e63d4 JMP %RAX |
0x4e63d6 NOPW %CS:(%RAX,%RAX,1) |
Path / |
Source file and lines | |
Module | exec |
nb instructions | 5 |
nb uops | 4 |
loop length | 22 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 0.67 cycles |
front end | 0.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 0.33 | 0.33 | 0.00 | 0.40 | 1.00 | 0.00 | 0.00 | 0.00 | 0.20 | 0.33 |
cycles | 1.00 | 0.40 | 0.33 | 0.33 | 0.00 | 0.40 | 1.00 | 0.00 | 0.00 | 0.00 | 0.20 | 0.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 1.07 |
Stall cycles | 0.00 |
Front-end | 0.67 |
Dispatch | 1.00 |
Overall L1 | 1.00 |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
MOV 0x89a85(%RIP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4e63e0 <__real_memset_impl_setup> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP %RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1.75 |
Source file and lines | |
Module | exec |
nb instructions | 5 |
nb uops | 4 |
loop length | 22 |
used x86 registers | 1 |
used mmx registers | 0 |
used xmm registers | 0 |
used ymm registers | 0 |
used zmm registers | 0 |
nb stack references | 0 |
micro-operation queue | 0.67 cycles |
front end | 0.67 cycles |
P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | |
---|---|---|---|---|---|---|---|---|---|---|---|---|
uops | 1.00 | 0.40 | 0.33 | 0.33 | 0.00 | 0.40 | 1.00 | 0.00 | 0.00 | 0.00 | 0.20 | 0.33 |
cycles | 1.00 | 0.40 | 0.33 | 0.33 | 0.00 | 0.40 | 1.00 | 0.00 | 0.00 | 0.00 | 0.20 | 0.33 |
Cycles executing div or sqrt instructions | NA |
FE+BE cycles | 1.07 |
Stall cycles | 0.00 |
Front-end | 0.67 |
Dispatch | 1.00 |
Overall L1 | 1.00 |
Instruction | Nb FU | P0 | P1 | P2 | P3 | P4 | P5 | P6 | P7 | P8 | P9 | P10 | P11 | Latency | Recip. throughput |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
ENDBR64 | |||||||||||||||
MOV 0x89a85(%RIP),%RAX | 1 | 0 | 0 | 0.33 | 0.33 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0.33 | 1 | 0.33 |
TEST %RAX,%RAX | 1 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0.20 | 0 | 0 | 0 | 0.20 | 0 | 2 | 0.20 |
JE 4e63e0 <__real_memset_impl_setup> | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 0.50 |
JMP %RAX | 1 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0.50 | 0 | 0 | 0 | 0 | 0 | 0 | 1.75 |
Name | Coverage (%) | Time (s) |
---|---|---|
○_intel_fast_memset | 0.01 | 0 |