OV - exec - Function void qmcplusplus::DelayedUpdate<double, double>::acceptRow<qmcplusplus::Vector<double, std::allocator<double> > >(qmcplusplus::Matrix<double, std::allocator<double> >&, int, qmcplusplus::Vector<double, std::allocator<double>

	Function: void qmcplusplus::DelayedUpdate<double, double>::acceptRow<qmcplusplus::Vector<double, std ...	Module: exec	Source: DelayedUpdate.h:125-153 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h: 413 - 452

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

450: 	  const ptrdiff_t _Num = __last - __first;

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

249:   inline const_pointer data() const { return X; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h: 1131 - 1131

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 125 - 153

--------------------------------------------------------------------------------

125:   {

126:     const T cminusone(-1);

127:     const T czero(0);

128:     const int norb     = Ainv.rows();

129:     const int lda_Binv = Binv.cols();

130:     std::copy_n(Ainv[rowchanged], norb, V[delay_count]);

131:     std::copy_n(psiV.data(), norb, U[delay_count]);

132:     delay_list[delay_count] = rowchanged;

133:     // the new Binv is [[X Y] [Z x]]

134:     BLAS::gemv('T', norb, delay_count + 1, cminusone, V.data(), norb, psiV.data(), 1, czero, p.data(), 1);

135:     // x

136:     T y = -p[delay_count];

137:     for (int i = 0; i < delay_count; i++)

138:       y += Binv[delay_count][i] * p[i];

139:     Binv[delay_count][delay_count] = y = T(1) / y;

140:     // Y

141:     BLAS::gemv('T', delay_count, delay_count, y, Binv.data(), lda_Binv, p.data(), 1, czero, Binv.data() + delay_count,

142:                lda_Binv);

143:     // X

144:     BLAS::ger(delay_count, delay_count, cminusone, Binv[delay_count], 1, Binv.data() + delay_count, lda_Binv,

145:               Binv.data(), lda_Binv);

146:     // Z

147:     for (int i = 0; i < delay_count; i++)

148:       Binv[delay_count][i] *= -y;

149:     delay_count++;

150:     // update Ainv when maximal delay is reached

151:     if (delay_count == lda_Binv)

152:       updateInvMat(Ainv);

153:   }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algo.h: 709 - 709

--------------------------------------------------------------------------------

709:       if (__n2 <= 0)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 447

--------------------------------------------------------------------------------

187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

[...]

447:     dger(&m, &n, &alpha, x, &incx, y, &incy, a, &lda);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 217

--------------------------------------------------------------------------------

77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

0x4366e0 SUB	SP, SP, #160

0x4366e4 STR	D8, [SP, #64]

0x4366e8 STP	X29, X30, [SP, #80]

0x4366ec STP	X26, X25, [SP, #96]

0x4366f0 STP	X24, X23, [SP, #112]

0x4366f4 STP	X22, X21, [SP, #128]

0x4366f8 STP	X20, X19, [SP, #144]

0x4366fc ADD	X29, SP, #80

0x436700 LDR	X26, [X1]

0x436704 LDR	W24, [X0, #136]

0x436708 LDRSW	X8, [X0, #360]

0x43670c ORR	X21, XZR, X3

0x436710 ORR	W22, WZR, W2

0x436714 ORR	X19, XZR, X1

0x436718 ORR	X20, XZR, X0

0x43671c CMP	W26, #1

0x436720 B.LT	436780

0x436724 LDR	X11, [X19, #8]

0x436728 LDR	X12, [X20, #72]

0x43672c SBFM	X10, X22, #0, #31

0x436730 LDR	X9, [X19, #48]

0x436734 MADD	X10, X11, X10, XZR

0x436738 LDR	X11, [X20, #112]

0x43673c MADD	X12, X12, X8, XZR

0x436740 B.EQ	436a10

0x436744 UBFM	X23, X26, #61, #30

0x436748 ADD	X0, X11, X12,LSL #3

0x43674c ADD	X1, X9, X10,LSL #3

0x436750 ORR	X2, XZR, X23

0x436754 BL	404b70

0x436758 LDRSW	X8, [X20, #360]

0x43675c LDR	X10, [X20, #8]

0x436760 LDR	X9, [X20, #48]

0x436764 ORR	X2, XZR, X23

0x436768 MADD	X8, X10, X8, XZR

0x43676c LDR	X1, [X21, #24]!

0x436770 ADD	X0, X9, X8,LSL #3

0x436774 BL	404b70

0x436778 LDRSW	X8, [X20, #360]

0x43677c B	436784

0x436780 ADD	X21, X21, #24

(913) 0x436784 LDR	X9, [X20, #336]

(913) 0x436788 MOVZ	W25, #84

(913) 0x43678c ADD	X23, SP, #32

(913) 0x436790 SUB	X0, X29, #36

(913) 0x436794 SUB	X1, X29, #4

(913) 0x436798 SUB	X2, X29, #8

(913) 0x43679c SUB	X3, X29, #24

(913) 0x4367a0 STR	W22, [X9, X8,LSL #2]

(913) 0x4367a4 MOVZ	W22, #1

(913) 0x4367a8 SUB	X5, X29, #28

(913) 0x4367ac SUB	X7, X29, #32

(913) 0x4367b0 STURB	W25, [X29, #476]

(913) 0x4367b4 STR	XZR, [SP, #32]

(913) 0x4367b8 LDR	W8, [X20, #360]

(913) 0x4367bc LDR	X4, [X20, #112]

(913) 0x4367c0 LDR	X6, [X21]

(913) 0x4367c4 MOVZ	X21, #49136

(913) 0x4367c8 STP	W22, W26, [X29, #480]

(913) 0x4367cc STR	W22, [SP, #28]

(913) 0x4367d0 STUR	X21, [X29, #488]

(913) 0x4367d4 ADD	W8, W8, #1

(913) 0x4367d8 STP	W8, W26, [X29, #504]

(913) 0x4367dc LDR	X8, [X20, #320]

(913) 0x4367e0 ADD	X26, SP, #28

(913) 0x4367e4 STR	X23, [SP]

(913) 0x4367e8 STP	X8, X26, [SP, #8]

(913) 0x4367ec BL	404740

(913) 0x4367f0 LDR	W8, [X20, #360]

(913) 0x4367f4 LDR	X6, [X20, #320]

(913) 0x4367f8 LDR	X10, [X20, #136]

(913) 0x4367fc SBFM	X9, X8, #0, #31

(913) 0x436800 LDR	D0, [X6, X8,SXTW #3]

(913) 0x436804 LDR	X4, [X20, #176]

(913) 0x436808 MADD	X10, X10, X9, XZR

(913) 0x43680c FNEG	D0, D0

(913) 0x436810 CMP	W8, #1

(913) 0x436814 B.LT	4368a0

(913) 0x436818 CMP	W8, #3

(913) 0x43681c B.HI	436828

(913) 0x436820 ORR	X11, XZR, XZR

(913) 0x436824 B	436878

(913) 0x436828 MOVI	V2.2D, #0

(913) 0x43682c MOV	V2.D[0], V0.D[0]

(913) 0x436830 ADD	X12, X4, X10,LSL #3

(913) 0x436834 AND	X11, X8, #5950

(913) 0x436838 ADD	X13, X6, #16

(913) 0x43683c MOVI	V1.2D, #0

(913) 0x436840 ADD	X12, X12, #16

(913) 0x436844 ORR	X14, XZR, X11

  (916) 0x436848 LDP	Q0, Q3, [X12, #2032]

  (916) 0x43684c LDP	Q4, Q5, [X13, #2032]

  (916) 0x436850 ADD	X12, X12, #32

  (916) 0x436854 ADD	X13, X13, #32

  (916) 0x436858 SUBS	X14, X14, #4

  (916) 0x43685c FMLA	V1.2D, V5.2D, V3.2D

  (916) 0x436860 FMLA	V2.2D, V4.2D, V0.2D

  (916) 0x436864 B.NE	436848

(913) 0x436868 FADD	V0.2D, V1.2D, V2.2D

(913) 0x43686c FADDP	D0, V0.2D

(913) 0x436870 CMP	X11, X8

(913) 0x436874 B.EQ	4368a0

(913) 0x436878 UBFM	X12, X10, #61, #60

(913) 0x43687c ADD	X13, X6, X11,LSL #3

(913) 0x436880 ADD	X12, X12, X11,LSL #3

(913) 0x436884 SUB	X11, X8, X11

(913) 0x436888 ADD	X12, X4, X12

  (917) 0x43688c LDR	D1, [X12], #8

  (917) 0x436890 LDR	D2, [X13], #8

  (917) 0x436894 SUBS	X11, X11, #1

  (917) 0x436898 FMADD	D0, D2, D1, D0

  (917) 0x43689c B.NE	43688c

(913) 0x4368a0 FMOV	D1, #1.0000000

(913) 0x4368a4 ADD	X9, X4, X9,LSL #3

(913) 0x4368a8 SUB	X0, X29, #36

(913) 0x4368ac SUB	X1, X29, #4

(913) 0x4368b0 SUB	X2, X29, #8

(913) 0x4368b4 SUB	X3, X29, #24

(913) 0x4368b8 SUB	X5, X29, #28

(913) 0x4368bc STURB	W25, [X29, #476]

(913) 0x4368c0 STP	W8, W8, [X29, #504]

(913) 0x4368c4 STP	W22, W24, [X29, #480]

(913) 0x4368c8 SUB	X7, X29, #32

(913) 0x4368cc SUB	X25, X29, #32

(913) 0x4368d0 FDIV	D8, D1, D0

(913) 0x4368d4 STR	W24, [SP, #28]

(913) 0x4368d8 STR	D8, [X9, X10,LSL #3]

(913) 0x4368dc STUR	D8, [X29, #488]

(913) 0x4368e0 STR	XZR, [SP, #32]

(913) 0x4368e4 STP	X9, X26, [SP, #8]

(913) 0x4368e8 STR	X23, [SP]

(913) 0x4368ec BL	404740

(913) 0x4368f0 LDRSW	X8, [X20, #360]

(913) 0x4368f4 LDR	X9, [X20, #136]

(913) 0x4368f8 LDR	X7, [X20, #176]

(913) 0x4368fc ADD	X0, SP, #32

(913) 0x436900 SUB	X1, X29, #4

(913) 0x436904 SUB	X2, X29, #24

(913) 0x436908 SUB	X4, X29, #8

(913) 0x43690c SUB	X6, X29, #28

(913) 0x436910 MADD	X9, X9, X8, XZR

(913) 0x436914 ADD	X5, X7, X8,LSL #3

(913) 0x436918 STR	W8, [SP, #32]

(913) 0x43691c STP	W22, W8, [X29, #504]

(913) 0x436920 STUR	X21, [X29, #488]

(913) 0x436924 STP	W24, W24, [X29, #480]

(913) 0x436928 STR	X25, [SP]

(913) 0x43692c ADD	X3, X7, X9,LSL #3

(913) 0x436930 BL	404530

(913) 0x436934 LDR	W8, [X20, #360]

(913) 0x436938 CMP	W8, #1

(913) 0x43693c B.LT	4369d4

(913) 0x436940 LDR	X9, [X20, #176]

(913) 0x436944 LDR	X10, [X20, #136]

(913) 0x436948 FNEG	D0, D8

(913) 0x43694c CMP	W8, #3

(913) 0x436950 B.HI	43695c

(913) 0x436954 ORR	X11, XZR, XZR

(913) 0x436958 B	4369a4

(913) 0x43695c MADD	X12, X10, X8, XZR

(913) 0x436960 AND	X11, X8, #5950

(913) 0x436964 ORR	X13, XZR, X11

(913) 0x436968 ADD	X12, X9, X12,LSL #3

(913) 0x43696c ADD	X12, X12, #16

(913) 0x436970 HINT	#0

(913) 0x436974 HINT	#0

(913) 0x436978 HINT	#0

(913) 0x43697c HINT	#0

  (914) 0x436980 LDP	Q1, Q2, [X12, #2032]

  (914) 0x436984 SUBS	X13, X13, #4

  (914) 0x436988 FMUL	V2.2D, V2.2D, V0.D[0]

  (914) 0x43698c FMUL	V1.2D, V1.2D, V0.D[0]

  (914) 0x436990 STP	Q1, Q2, [X12, #2032]

  (914) 0x436994 ADD	X12, X12, #32

  (914) 0x436998 B.NE	436980

(913) 0x43699c CMP	X11, X8

(913) 0x4369a0 B.EQ	4369d4

(913) 0x4369a4 MADD	X10, X10, X8, XZR

(913) 0x4369a8 UBFM	X10, X10, #61, #60

(913) 0x4369ac ADD	X10, X10, X11,LSL #3

(913) 0x4369b0 ADD	X9, X9, X10

(913) 0x4369b4 SUB	X10, X8, X11

(913) 0x4369b8 HINT	#0

(913) 0x4369bc HINT	#0

  (915) 0x4369c0 LDR	D1, [X9]

  (915) 0x4369c4 SUBS	X10, X10, #1

  (915) 0x4369c8 FMUL	D1, D1, D0

  (915) 0x4369cc STR	D1, [X9], #8

  (915) 0x4369d0 B.NE	4369c0

(913) 0x4369d4 ADD	W8, W8, #1

(913) 0x4369d8 STR	W8, [X20, #360]

(913) 0x4369dc CMP	W8, W24

(913) 0x4369e0 B.NE	4369f0

(913) 0x4369e4 ORR	X0, XZR, X20

(913) 0x4369e8 ORR	X1, XZR, X19

(913) 0x4369ec BL	436a40

(913) 0x4369f0 LDR	D8, [SP, #64]

(913) 0x4369f4 LDP	X20, X19, [SP, #144]

(913) 0x4369f8 LDP	X22, X21, [SP, #128]

(913) 0x4369fc LDP	X24, X23, [SP, #112]

(913) 0x436a00 LDP	X26, X25, [SP, #96]

(913) 0x436a04 LDP	X29, X30, [SP, #80]

(913) 0x436a08 ADD	SP, SP, #160

(913) 0x436a0c RET

(913) 0x436a10 LDR	D0, [X9, X10,LSL #3]

(913) 0x436a14 STR	D0, [X11, X12,LSL #3]

(913) 0x436a18 LDR	X9, [X21, #24]!

(913) 0x436a1c LDR	X11, [X20, #8]

(913) 0x436a20 LDR	X10, [X20, #48]

(913) 0x436a24 LDR	D0, [X9]

(913) 0x436a28 MADD	X11, X11, X8, XZR

(913) 0x436a2c STR	D0, [X10, X11,LSL #3]

(913) 0x436a30 B	436784

0x436a34 HINT	#0

0x436a38 HINT	#0

0x436a3c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:129	exec
○	qmcplusplus::WaveFunction::acc[...]	stl_vector.h:993	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	DelayedUpdate.h:125-153
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:413,450-452
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248-249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:125-153
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algo.h:709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187,447
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.50 cycles (12.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 55% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.00 to 3.73 cycles (1.61x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.00 to 1.00 cycles (6.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.50	3.50	3.50	3.50	3.50	3.50	0.50	0.50	0.00	0.00	6.00	6.00	6.00	2.50	2.50
cycles	2.50	2.50	3.50	3.50	3.50	3.50	3.50	3.50	0.50	0.50	0.00	0.00	6.00	6.00	6.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4366e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X26, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W24, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDRSW X8, [X0, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W22, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W26, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 436780 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X10, X22, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR X9, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X10, X11, X10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X11, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X12, X12, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 436a10 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X23, X26, #61, #30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 404b70 <@plt_start@+0x750>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X8, [X20, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X2, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X8, X10, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X1, [X21, #24]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404b70 <@plt_start@+0x750>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X8, [X20, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 436784 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X21, X21, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run 1x1

Source file and lines	DelayedUpdate.h:125-153
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:413,450-452
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248-249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:125-153
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algo.h:709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187,447
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.00 to 0.50 cycles (12.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.00 to 1.00 cycles (6.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 80 bytes. The binary function is storing 88 bytes.

General properties

nb instructions	44
loop length	176
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.50	3.50	3.50	3.50	3.50	3.50	0.50	0.50	0.00	0.00	6.00	6.00	6.00	2.50	2.50
cycles	2.50	2.50	3.50	3.50	3.50	3.50	3.50	3.50	0.50	0.50	0.00	0.00	6.00	6.00	6.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.13
Overall L1	6.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.00 cycles. At this rate:

13% of peak load performance is reached (13.33 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4366e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #160	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X26, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W24, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDRSW X8, [X0, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W22, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W26, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 436780 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_+0xa0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X19, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X20, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X10, X22, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
LDR X9, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X10, X11, X10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X11, [X20, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X12, X12, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
B.EQ 436a10 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_+0x330>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X23, X26, #61, #30	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X11, X12,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X9, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 404b70 <@plt_start@+0x750>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X8, [X20, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X10, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X2, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MADD X8, X10, X8, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X1, [X21, #24]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X0, X9, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404b70 <@plt_start@+0x750>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDRSW X8, [X20, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
B 436784 <_ZN11qmcplusplus13DelayedUpdateIddE9acceptRowINS_6VectorIdSaIdEEEEEvRNS_6MatrixIdS4_EEiRKT_+0xa4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X21, X21, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	2	0			2.66	0	1.77	0	1.33	0	1.87	0	1.37	0	0.9	0	0.93	0	0.79	0	0.7	0	0.62	0	0.59	0	0.52	0

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.0049999998882413	0.011618477292359
1x2	1	2	2	2	0.00499999942258	0.0057191462256014
1x4
1x8	3	2.66	2.66	8	0.00499999942258	0.0039083585143089
1x16	8	1.77	1.77	16	0.00999999884516	0.0049722888506949
1x24	11	1.33	1.33	24	0.014999996870756	0.0059969779103994
1x32	12	1.87	1.87	32	0.014999998733401	0.003738876665011
1x40	22	1.37	1.37	40	0.01999999769032	0.0046290275640786
1x48	31	0.9	0.9	48	0.024999996647239	0.0064855478703976
1x56	37	0.93	0.93	56	0.01999999769032	0.005772088188678
1x64	45	0.79	0.79	64	0.019999995827675	0.0062458892352879
1x72	54	0.7	0.7	72	0.029999999329448	0.0064496477134526
1x80	65	0.62	0.62	80	0.024999994784594	0.0067791007459164
1x88	66	0.59	0.59	88	0.029999995604157	0.0066429562866688
1x96	80	0.52	0.52	96	0.034999996423721	0.0070323306135833

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DelayedUpdate::acceptRow > >(qmcplusplus::Matrix >&, int, qmcplusplus::Vector > const&)–	0.01	0.00
▼Loop 913 - stl_algobase.h:413-413 - exec–	0.01	0.00
○Loop 915 - DelayedUpdate.h:147-148 - exec	0.00	0.00
○Loop 916 - DelayedUpdate.h:137-138 - exec	0.00	0.00
○Loop 917 - DelayedUpdate.h:137-138 - exec	0.00	0.00
○Loop 914 - DelayedUpdate.h:147-148 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency