OV - exec - Function qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const*, double*, double*, double*, double*, int*) const

	Function: qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const, double, do ...	Module: exec	Source: BsplineFunctor.h:284-339 [...]	Coverage (incl. loops): 0.58% \| (excl. loops): 0.01%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 284 - 339

--------------------------------------------------------------------------------

284:   int iLimit                 = iEnd - iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

299:     }

300:   }

301:

302:   #pragma omp simd

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

337:     // clang-format on

338:   }

339: }

0x416a40 SUB	W11, W3, W2

0x416a44 CMP	W11, #1

0x416a48 B.LT	417104

0x416a4c STP	D15, D14, [SP, #944]!

0x416a50 STP	D13, D12, [SP, #16]

0x416a54 STP	D11, D10, [SP, #32]

0x416a58 STP	D9, D8, [SP, #48]

0x416a5c STR	X29, [SP, #64]

0x416a60 ADDVL	SP, SP, #32

0x416a64 ADDVL	SP, SP, #40

0x416a68 ADDVL	X8, SP, #31

0x416a6c LDR	D4, [X0, #568]

0x416a70 LDR	D1, [X0, #8]

0x416a74 SBFM	X10, X2, #61, #31

0x416a78 SUB	W14, W1, W2

0x416a7c ORR	X12, XZR, XZR

0x416a80 ORR	W17, WZR, WZR

0x416a84 ADD	X13, X4, X10

0x416a88 ADD	X9, X6, X10

0x416a8c ADDVL	X8, X8, #25

0x416a90 LDR	X16, [X8, #88]

0x416a94 ADDVL	X8, SP, #31

0x416a98 ADDVL	X8, X8, #25

0x416a9c FMUL	D7, D4, D4

0x416aa0 LDR	X15, [X8, #80]

0x416aa4 ADD	X8, X5, X10

0x416aa8 ADD	X10, X7, X10

0x416aac B	416acc

0x416ab0 HINT	#0

0x416ab4 HINT	#0

0x416ab8 HINT	#0

0x416abc HINT	#0

(264) 0x416ac0 ADD	X12, X12, #1

(264) 0x416ac4 CMP	X11, X12

(264) 0x416ac8 B.EQ	416aec

(264) 0x416acc LDR	D2, [X13, X12,LSL #3]

(264) 0x416ad0 FCMP	D2, D1

(264) 0x416ad4 CCMP	W14, W12, #4, #11

(264) 0x416ad8 B.EQ	416ac0

(264) 0x416adc STR	W12, [X16, X17,SXTW #2]

(264) 0x416ae0 STR	D2, [X15, X17,SXTW #3]

(264) 0x416ae4 ADD	W17, W17, #1

(264) 0x416ae8 B	416ac0

0x416aec CMP	W17, #1

0x416af0 B.LT	4170e8

0x416af4 LDR	D0, [X0, #296]

0x416af8 LDP	D15, D14, [X0, #360]

0x416afc LDP	D13, D11, [X0, #160]

0x416b00 CNTD	X18, ALL

0x416b04 ORR	W17, WZR, W17

0x416b08 LDR	D19, [X0, #176]

0x416b0c LDP	D25, D24, [X0, #192]

0x416b10 LDR	D26, [X0, #208]

0x416b14 LDP	D12, D9, [X0, #224]

0x416b18 LDR	D10, [X0, #240]

0x416b1c LDP	D21, D20, [X0, #256]

0x416b20 LDR	D23, [X0, #272]

0x416b24 LDP	D22, D18, [X0, #24]

0x416b28 LDP	D2, D3, [X0, #56]

0x416b2c LDP	D5, D6, [X0, #72]

0x416b30 LDP	D16, D17, [X0, #88]

0x416b34 LDP	D8, D31, [X0, #104]

0x416b38 LDP	D30, D28, [X0, #120]

0x416b3c LDP	D29, D27, [X0, #136]

0x416b40 LDR	X11, [X0, #536]

0x416b44 ADD	X12, X11, #8

0x416b48 ADD	X13, X11, #16

0x416b4c ADD	X14, X11, #24

0x416b50 STR	Z4, [SP, #49, MUL VL]

0x416b54 STR	Z14, [SP, #47, MUL VL]

0x416b58 STR	Z9, [SP, #45, MUL VL]

0x416b5c STR	Z18, [SP, #43, MUL VL]

0x416b60 STR	Z0, [SP, #55, MUL VL]

0x416b64 LDR	D0, [X0, #304]

0x416b68 STR	Z8, [SP, #48, MUL VL]

0x416b6c STR	Z12, [SP, #46, MUL VL]

0x416b70 STR	Z10, [SP, #44, MUL VL]

0x416b74 STR	Z2, [SP, #40, MUL VL]

0x416b78 STR	Z0, [SP, #54, MUL VL]

0x416b7c LDR	D0, [X0, #328]

0x416b80 STR	Z0, [SP, #53, MUL VL]

0x416b84 LDR	D0, [X0, #336]

0x416b88 STR	Z0, [SP, #52, MUL VL]

0x416b8c LDR	D0, [X0, #392]

0x416b90 STR	Z0, [SP, #51, MUL VL]

0x416b94 LDR	D0, [X0, #400]

0x416b98 STR	Z0, [SP, #50, MUL VL]

0x416b9c LDP	D0, D1, [X0, #40]

0x416ba0 STR	Z1, [SP, #41, MUL VL]

0x416ba4 STR	Z0, [SP, #42, MUL VL]

0x416ba8 CMP	X18, X17

0x416bac B.LS	416bd8

0x416bb0 ORR	Z18.D, Z15.D, Z15.D

0x416bb4 ORR	Z0.D, Z13.D, Z13.D

0x416bb8 ORR	Z13.D, Z3.D, Z3.D

0x416bbc ORR	Z12.D, Z5.D, Z5.D

0x416bc0 ORR	X0, XZR, XZR

0x416bc4 ORR	Z14.D, Z11.D, Z11.D

0x416bc8 ORR	Z11.D, Z6.D, Z6.D

0x416bcc ORR	Z10.D, Z16.D, Z16.D

0x416bd0 ORR	Z9.D, Z17.D, Z17.D

0x416bd4 B	416f04

0x416bd8 ORR	Z8.D, Z7.D, Z7.D

0x416bdc DUP	Z7.D, Z4.D[0]

0x416be0 LDR	Z4, [SP, #55, MUL VL]

0x416be4 STR	Z15, [SP, #21, MUL VL]

0x416be8 RDVL	X0, #1

0x416bec STR	Z5, [SP, #9, MUL VL]

0x416bf0 ORR	W1, WZR, #1887

0x416bf4 DUP	Z1.D, Z1.D[0]

0x416bf8 PTRUE	P0.D, ALL

0x416bfc ORR	X18, XZR, XZR

0x416c00 UBFM	X0, X0, #4, #63

0x416c04 STR	Z6, [SP, #8, MUL VL]

0x416c08 DUP	Z2.D, Z2.D[0]

0x416c0c STR	Z16, [SP, #7, MUL VL]

0x416c10 STR	Z17, [SP, #6, MUL VL]

0x416c14 STR	Z13, [SP, #20, MUL VL]

0x416c18 MADD	X0, X0, X1, XZR

0x416c1c STR	Z11, [SP, #19, MUL VL]

0x416c20 STR	Z19, [SP, #18, MUL VL]

0x416c24 AND	X0, X0, X17

0x416c28 STR	Z21, [SP, #14, MUL VL]

0x416c2c STR	Z20, [SP, #13, MUL VL]

0x416c30 STR	Z22, [SP, #11, MUL VL]

0x416c34 STR	Z3, [SP, #10, MUL VL]

0x416c38 DUP	Z3.D, Z3.D[0]

0x416c3c DUP	Z4.D, Z4.D[0]

0x416c40 STR	Z8, [SP, #22, MUL VL]

0x416c44 STR	Z25, [SP, #17, MUL VL]

0x416c48 STR	Z24, [SP, #16, MUL VL]

0x416c4c STR	Z26, [SP, #15, MUL VL]

0x416c50 STR	Z23, [SP, #12, MUL VL]

0x416c54 STR	Z31, [SP, #5, MUL VL]

0x416c58 STR	Z30, [SP, #4, MUL VL]

0x416c5c STR	Z28, [SP, #3, MUL VL]

0x416c60 STR	Z29, [SP, #2, MUL VL]

0x416c64 STR	Z27, [SP, #1, MUL VL]

0x416c68 STR	Z4, [SP, MUL VL]

0x416c6c LDR	Z4, [SP, #54, MUL VL]

0x416c70 DUP	Z4.D, Z4.D[0]

0x416c74 STR	Z4, [SP, #39, MUL VL]

0x416c78 LDR	Z4, [SP, #53, MUL VL]

0x416c7c DUP	Z4.D, Z4.D[0]

0x416c80 STR	Z4, [SP, #38, MUL VL]

0x416c84 LDR	Z4, [SP, #52, MUL VL]

0x416c88 DUP	Z4.D, Z4.D[0]

0x416c8c STR	Z4, [SP, #37, MUL VL]

0x416c90 DUP	Z4.D, Z15.D[0]

0x416c94 DUP	Z15.D, Z0.D[0]

0x416c98 LDR	Z0, [SP, #48, MUL VL]

0x416c9c STR	Z4, [SP, #36, MUL VL]

0x416ca0 DUP	Z4.D, Z14.D[0]

0x416ca4 DUP	Z14.D, Z18.D[0]

0x416ca8 DUP	Z18.D, Z31.D[0]

0x416cac STR	Z4, [SP, #35, MUL VL]

0x416cb0 LDR	Z4, [SP, #51, MUL VL]

0x416cb4 DUP	Z4.D, Z4.D[0]

0x416cb8 STR	Z4, [SP, #34, MUL VL]

0x416cbc LDR	Z4, [SP, #50, MUL VL]

0x416cc0 DUP	Z4.D, Z4.D[0]

0x416cc4 STR	Z4, [SP, #33, MUL VL]

0x416cc8 DUP	Z4.D, Z8.D[0]

0x416ccc STR	Z4, [SP, #32, MUL VL]

0x416cd0 DUP	Z4.D, Z13.D[0]

0x416cd4 DUP	Z13.D, Z22.D[0]

0x416cd8 DUP	Z22.D, Z27.D[0]

0x416cdc STR	Z4, [SP, #31, MUL VL]

0x416ce0 DUP	Z4.D, Z11.D[0]

0x416ce4 DUP	Z11.D, Z20.D[0]

0x416ce8 DUP	Z20.D, Z28.D[0]

0x416cec STR	Z4, [SP, #30, MUL VL]

0x416cf0 DUP	Z4.D, Z19.D[0]

0x416cf4 DUP	Z19.D, Z30.D[0]

0x416cf8 STR	Z4, [SP, #29, MUL VL]

0x416cfc DUP	Z4.D, Z25.D[0]

0x416d00 STR	Z4, [SP, #28, MUL VL]

0x416d04 DUP	Z4.D, Z24.D[0]

0x416d08 STR	Z4, [SP, #27, MUL VL]

0x416d0c DUP	Z4.D, Z26.D[0]

0x416d10 STR	Z4, [SP, #26, MUL VL]

0x416d14 DUP	Z4.D, Z12.D[0]

0x416d18 DUP	Z12.D, Z23.D[0]

0x416d1c STR	Z4, [SP, #25, MUL VL]

0x416d20 DUP	Z4.D, Z9.D[0]

0x416d24 STR	Z4, [SP, #24, MUL VL]

0x416d28 DUP	Z4.D, Z10.D[0]

0x416d2c DUP	Z10.D, Z21.D[0]

0x416d30 DUP	Z21.D, Z29.D[0]

0x416d34 STR	Z4, [SP, #23, MUL VL]

0x416d38 DUP	Z4.D, Z5.D[0]

0x416d3c DUP	Z5.D, Z6.D[0]

0x416d40 DUP	Z6.D, Z16.D[0]

0x416d44 DUP	Z16.D, Z17.D[0]

0x416d48 DUP	Z17.D, Z0.D[0]

0x416d4c LDR	Z0, [SP, MUL VL]

0x416d50 HINT	#0

0x416d54 HINT	#0

0x416d58 HINT	#0

0x416d5c HINT	#0

(262) 0x416d60 LD1D	{Z23.D}, P0/Z, [X15, X18,LSL #3]

(262) 0x416d64 LDR	Z30, [SP, #39, MUL VL]

(262) 0x416d68 LDR	Z31, [SP, #38, MUL VL]

(262) 0x416d6c FMUL	Z24.D, Z23.D, Z7.D

(262) 0x416d70 LDR	Z8, [SP, #37, MUL VL]

(262) 0x416d74 LDR	Z9, [SP, #26, MUL VL]

(262) 0x416d78 MOVPRFX	Z25, Z24

(262) 0x416d7c FCVTZS	Z25.D, P0/M, Z24.D

(262) 0x416d80 LD1D	{Z27.D}, P0/Z, [X11, Z25.D,LSL #3]

(262) 0x416d84 MOVPRFX	Z26, Z25

(262) 0x416d88 SCVTF	Z26.D, P0/M, Z25.D

(262) 0x416d8c FSUB	Z24.D, Z24.D, Z26.D

(262) 0x416d90 FMLA	Z30.D, P0/M, Z0.D, Z24.D

(262) 0x416d94 FMAD	Z31.D, P0/M, Z24.D, Z8.D

(262) 0x416d98 LD1D	{Z28.D}, P0/Z, [X12, Z25.D,LSL #3]

(262) 0x416d9c LDR	Z8, [SP, #29, MUL VL]

(262) 0x416da0 FMUL	Z26.D, Z24.D, Z24.D

(262) 0x416da4 FMUL	Z29.D, Z26.D, Z24.D

(262) 0x416da8 FMUL	Z30.D, Z30.D, Z27.D

(262) 0x416dac FMLA	Z30.D, P0/M, Z31.D, Z28.D

(262) 0x416db0 LDR	Z31, [SP, #31, MUL VL]

(262) 0x416db4 FMAD	Z31.D, P0/M, Z26.D, Z8.D

(262) 0x416db8 LDR	Z8, [SP, #30, MUL VL]

(262) 0x416dbc FMLA	Z31.D, P0/M, Z8.D, Z24.D

(262) 0x416dc0 LDR	Z8, [SP, #28, MUL VL]

(262) 0x416dc4 FMUL	Z31.D, Z31.D, Z27.D

(262) 0x416dc8 FMAD	Z8.D, P0/M, Z26.D, Z9.D

(262) 0x416dcc LDR	Z9, [SP, #27, MUL VL]

(262) 0x416dd0 FMLA	Z8.D, P0/M, Z9.D, Z24.D

(262) 0x416dd4 LDR	Z9, [SP, #35, MUL VL]

(262) 0x416dd8 FMLA	Z31.D, P0/M, Z8.D, Z28.D

(262) 0x416ddc MOVPRFX	Z8, Z1

(262) 0x416de0 FMLA	Z8.D, P0/M, Z13.D, Z29.D

(262) 0x416de4 FMLA	Z8.D, P0/M, Z14.D, Z26.D

(262) 0x416de8 FMLA	Z8.D, P0/M, Z15.D, Z24.D

(262) 0x416dec FMUL	Z27.D, Z8.D, Z27.D

(262) 0x416df0 MOVPRFX	Z8, Z5

(262) 0x416df4 FMLA	Z8.D, P0/M, Z2.D, Z29.D

(262) 0x416df8 FMLA	Z8.D, P0/M, Z3.D, Z26.D

(262) 0x416dfc FMLA	Z8.D, P0/M, Z4.D, Z24.D

(262) 0x416e00 FMLA	Z27.D, P0/M, Z8.D, Z28.D

(262) 0x416e04 LDR	Z8, [SP, #36, MUL VL]

(262) 0x416e08 FMAD	Z8.D, P0/M, Z24.D, Z9.D

(262) 0x416e0c LDR	Z9, [SP, #23, MUL VL]

(262) 0x416e10 LD1D	{Z28.D}, P0/Z, [X13, Z25.D,LSL #3]

(262) 0x416e14 LD1D	{Z25.D}, P0/Z, [X14, Z25.D,LSL #3]

(262) 0x416e18 FMLA	Z30.D, P0/M, Z8.D, Z28.D

(262) 0x416e1c LDR	Z8, [SP, #25, MUL VL]

(262) 0x416e20 FMAD	Z8.D, P0/M, Z26.D, Z9.D

(262) 0x416e24 LDR	Z9, [SP, #24, MUL VL]

(262) 0x416e28 FMLA	Z8.D, P0/M, Z9.D, Z24.D

(262) 0x416e2c FMLA	Z31.D, P0/M, Z8.D, Z28.D

(262) 0x416e30 MOVPRFX	Z8, Z18

(262) 0x416e34 FMLA	Z8.D, P0/M, Z6.D, Z29.D

(262) 0x416e38 FMAD	Z29.D, P0/M, Z19.D, Z22.D

(262) 0x416e3c FMLA	Z8.D, P0/M, Z16.D, Z26.D

(262) 0x416e40 FMLA	Z8.D, P0/M, Z17.D, Z24.D

(262) 0x416e44 FMLA	Z27.D, P0/M, Z8.D, Z28.D

(262) 0x416e48 LDR	Z28, [SP, #34, MUL VL]

(262) 0x416e4c LDR	Z8, [SP, #33, MUL VL]

(262) 0x416e50 FMAD	Z28.D, P0/M, Z24.D, Z8.D

(262) 0x416e54 FMAD	Z28.D, P0/M, Z25.D, Z30.D

(262) 0x416e58 MOVPRFX	Z30, Z12

(262) 0x416e5c FMLA	Z30.D, P0/M, Z10.D, Z26.D

(262) 0x416e60 FMAD	Z26.D, P0/M, Z20.D, Z29.D

(262) 0x416e64 FMLA	Z30.D, P0/M, Z11.D, Z24.D

(262) 0x416e68 FMAD	Z24.D, P0/M, Z21.D, Z26.D

(262) 0x416e6c LDR	Z26, [SP, #32, MUL VL]

(262) 0x416e70 FMAD	Z30.D, P0/M, Z25.D, Z31.D

(262) 0x416e74 FMAD	Z24.D, P0/M, Z25.D, Z27.D

(262) 0x416e78 LD1SW	{Z25.D}, P0/Z, [X16, X18,LSL #2]

(262) 0x416e7c INCD	X18, ALL

(262) 0x416e80 FMUL	Z26.D, Z26.D, Z28.D

(262) 0x416e84 ST1D	{Z26.D}, P0, [X10, Z25.D,LSL #3]

(262) 0x416e88 FMUL	Z26.D, Z30.D, Z7.D

(262) 0x416e8c FDIVR	Z23.D, P0/M, Z23.D, Z26.D

(262) 0x416e90 ST1D	{Z23.D}, P0, [X9, Z25.D,LSL #3]

(262) 0x416e94 ST1D	{Z24.D}, P0, [X8, Z25.D,LSL #3]

(262) 0x416e98 CMP	X0, X18

(262) 0x416e9c B.NE	416d60

0x416ea0 LDR	Z7, [SP, #22, MUL VL]

0x416ea4 LDR	Z18, [SP, #21, MUL VL]

0x416ea8 LDR	Z0, [SP, #20, MUL VL]

0x416eac LDR	Z14, [SP, #19, MUL VL]

0x416eb0 LDR	Z19, [SP, #18, MUL VL]

0x416eb4 LDR	Z25, [SP, #17, MUL VL]

0x416eb8 LDR	Z24, [SP, #16, MUL VL]

0x416ebc LDR	Z26, [SP, #15, MUL VL]

0x416ec0 LDR	Z21, [SP, #14, MUL VL]

0x416ec4 LDR	Z20, [SP, #13, MUL VL]

0x416ec8 LDR	Z23, [SP, #12, MUL VL]

0x416ecc LDR	Z22, [SP, #11, MUL VL]

0x416ed0 LDR	Z4, [SP, #49, MUL VL]

0x416ed4 LDR	Z13, [SP, #10, MUL VL]

0x416ed8 LDR	Z12, [SP, #9, MUL VL]

0x416edc LDR	Z11, [SP, #8, MUL VL]

0x416ee0 LDR	Z10, [SP, #7, MUL VL]

0x416ee4 LDR	Z9, [SP, #6, MUL VL]

0x416ee8 LDR	Z31, [SP, #5, MUL VL]

0x416eec LDR	Z30, [SP, #4, MUL VL]

0x416ef0 LDR	Z28, [SP, #3, MUL VL]

0x416ef4 LDR	Z29, [SP, #2, MUL VL]

0x416ef8 LDR	Z27, [SP, #1, MUL VL]

0x416efc CMP	X0, X17

0x416f00 B.EQ	4170e8

0x416f04 ADD	X16, X16, X0,LSL #2

0x416f08 ADD	X15, X15, X0,LSL #3

0x416f0c SUB	X17, X17, X0

0x416f10 HINT	#0

0x416f14 HINT	#0

0x416f18 HINT	#0

0x416f1c HINT	#0

(263) 0x416f20 LDR	D1, [X15], #8

(263) 0x416f24 ORR	Z8.D, Z7.D, Z7.D

(263) 0x416f28 LDR	Z7, [SP, #54, MUL VL]

(263) 0x416f2c LDR	Z16, [SP, #55, MUL VL]

(263) 0x416f30 SUBS	X17, X17, #1

(263) 0x416f34 FMUL	D2, D1, D4

(263) 0x416f38 LDR	Z17, [SP, #53, MUL VL]

(263) 0x416f3c LDR	Z15, [SP, #43, MUL VL]

(263) 0x416f40 FRINTZ	D3, D2

(263) 0x416f44 FCVTZS	W18, D2

(263) 0x416f48 FSUB	D2, D2, S3

(263) 0x416f4c LDR	D5, [X11, X18,SXTW #3]

(263) 0x416f50 LDR	D6, [X12, X18,SXTW #3]

(263) 0x416f54 FMADD	D7, D16, D2, D7

(263) 0x416f58 LDR	Z16, [SP, #52, MUL VL]

(263) 0x416f5c FMUL	D3, D2, D2

(263) 0x416f60 FMUL	D4, D3, D2

(263) 0x416f64 FMUL	D7, D7, D5

(263) 0x416f68 FMADD	D16, D17, D2, D16

(263) 0x416f6c FMUL	D17, D25, D3

(263) 0x416f70 FMADD	D17, D24, D2, D17

(263) 0x416f74 FMADD	D7, D16, D6, D7

(263) 0x416f78 FMUL	D16, D0, D3

(263) 0x416f7c FMADD	D16, D14, D2, D16

(263) 0x416f80 FADD	D17, D17, D26

(263) 0x416f84 FADD	D16, D16, D19

(263) 0x416f88 FMUL	D16, D16, D5

(263) 0x416f8c FMADD	D16, D17, D6, D16

(263) 0x416f90 FMUL	D17, D22, D4

(263) 0x416f94 FMADD	D17, D15, D3, D17

(263) 0x416f98 LDR	Z15, [SP, #42, MUL VL]

(263) 0x416f9c FMADD	D17, D15, D2, D17

(263) 0x416fa0 LDR	Z15, [SP, #41, MUL VL]

(263) 0x416fa4 FADD	D17, D17, D15

(263) 0x416fa8 ORR	Z15.D, Z14.D, Z14.D

(263) 0x416fac ORR	Z14.D, Z0.D, Z0.D

(263) 0x416fb0 LDR	Z0, [SP, #47, MUL VL]

(263) 0x416fb4 FMUL	D5, D17, D5

(263) 0x416fb8 LDR	Z17, [SP, #40, MUL VL]

(263) 0x416fbc FMUL	D17, D17, D4

(263) 0x416fc0 FMADD	D17, D13, D3, D17

(263) 0x416fc4 FMADD	D17, D12, D2, D17

(263) 0x416fc8 FADD	D17, D17, D11

(263) 0x416fcc FMADD	D5, D17, D6, D5

(263) 0x416fd0 LDR	D6, [X13, X18,SXTW #3]

(263) 0x416fd4 FMADD	D17, D18, D2, D0

(263) 0x416fd8 LDR	Z0, [SP, #46, MUL VL]

(263) 0x416fdc FMADD	D7, D17, D6, D7

(263) 0x416fe0 FMUL	D17, D0, D3

(263) 0x416fe4 LDR	Z0, [SP, #45, MUL VL]

(263) 0x416fe8 FMADD	D17, D0, D2, D17

(263) 0x416fec LDR	Z0, [SP, #44, MUL VL]

(263) 0x416ff0 FADD	D17, D17, D0

(263) 0x416ff4 ORR	Z0.D, Z18.D, Z18.D

(263) 0x416ff8 ORR	Z18.D, Z19.D, Z19.D

(263) 0x416ffc ORR	Z19.D, Z20.D, Z20.D

(263) 0x417000 ORR	Z20.D, Z21.D, Z21.D

(263) 0x417004 ORR	Z21.D, Z25.D, Z25.D

(263) 0x417008 ORR	Z25.D, Z22.D, Z22.D

(263) 0x41700c ORR	Z22.D, Z23.D, Z23.D

(263) 0x417010 ORR	Z23.D, Z26.D, Z26.D

(263) 0x417014 ORR	Z26.D, Z24.D, Z24.D

(263) 0x417018 ORR	Z24.D, Z27.D, Z27.D

(263) 0x41701c ORR	Z27.D, Z28.D, Z28.D

(263) 0x417020 ORR	Z28.D, Z29.D, Z29.D

(263) 0x417024 ORR	Z29.D, Z30.D, Z30.D

(263) 0x417028 ORR	Z30.D, Z31.D, Z31.D

(263) 0x41702c LDR	Z31, [SP, #48, MUL VL]

(263) 0x417030 FMADD	D16, D17, D6, D16

(263) 0x417034 FMUL	D17, D10, D4

(263) 0x417038 FMADD	D17, D9, D3, D17

(263) 0x41703c FMADD	D17, D31, D2, D17

(263) 0x417040 ORR	Z31.D, Z30.D, Z30.D

(263) 0x417044 ORR	Z30.D, Z29.D, Z29.D

(263) 0x417048 ORR	Z29.D, Z28.D, Z28.D

(263) 0x41704c ORR	Z28.D, Z27.D, Z27.D

(263) 0x417050 ORR	Z27.D, Z24.D, Z24.D

(263) 0x417054 ORR	Z24.D, Z26.D, Z26.D

(263) 0x417058 ORR	Z26.D, Z23.D, Z23.D

(263) 0x41705c ORR	Z23.D, Z22.D, Z22.D

(263) 0x417060 ORR	Z22.D, Z25.D, Z25.D

(263) 0x417064 ORR	Z25.D, Z21.D, Z21.D

(263) 0x417068 ORR	Z21.D, Z20.D, Z20.D

(263) 0x41706c ORR	Z20.D, Z19.D, Z19.D

(263) 0x417070 ORR	Z19.D, Z18.D, Z18.D

(263) 0x417074 LDR	Z18, [SP, #51, MUL VL]

(263) 0x417078 FMUL	D4, D30, D4

(263) 0x41707c FADD	D17, D17, D31

(263) 0x417080 FMADD	D5, D17, D6, D5

(263) 0x417084 LDR	Z17, [SP, #50, MUL VL]

(263) 0x417088 LDR	D6, [X14, X18,SXTW #3]

(263) 0x41708c LDRSW	X18, [X16], #4

(263) 0x417090 FMADD	D17, D18, D2, D17

(263) 0x417094 ORR	Z18.D, Z0.D, Z0.D

(263) 0x417098 ORR	Z0.D, Z14.D, Z14.D

(263) 0x41709c ORR	Z14.D, Z15.D, Z15.D

(263) 0x4170a0 FMADD	D7, D17, D6, D7

(263) 0x4170a4 FMUL	D17, D21, D3

(263) 0x4170a8 FMADD	D3, D28, D3, D4

(263) 0x4170ac LDR	Z4, [SP, #49, MUL VL]

(263) 0x4170b0 FMADD	D17, D20, D2, D17

(263) 0x4170b4 FMADD	D2, D29, D2, D3

(263) 0x4170b8 FMUL	D3, D8, D7

(263) 0x4170bc ORR	Z7.D, Z8.D, Z8.D

(263) 0x4170c0 FADD	D17, D17, D23

(263) 0x4170c4 FADD	D2, D2, D27

(263) 0x4170c8 FMADD	D16, D17, D6, D16

(263) 0x4170cc STR	D3, [X10, X18,LSL #3]

(263) 0x4170d0 FMADD	D2, D2, D6, D5

(263) 0x4170d4 FMUL	D3, D16, D4

(263) 0x4170d8 STR	D2, [X8, X18,LSL #3]

(263) 0x4170dc FDIV	D1, D3, D1

(263) 0x4170e0 STR	D1, [X9, X18,LSL #3]

(263) 0x4170e4 B.NE	416f20

0x4170e8 ADDVL	SP, SP, #31

0x4170ec ADDVL	SP, SP, #25

0x4170f0 LDP	D9, D8, [SP, #48]

0x4170f4 LDP	D11, D10, [SP, #32]

0x4170f8 LDP	D13, D12, [SP, #16]

0x4170fc LDR	X29, [SP, #64]

0x417100 LDP	D15, D14, [SP], #80

0x417104 RET

0x417108 HINT	#0

0x41710c HINT	#0

Coverage (%)	Name	Source Location	Module
►54.00+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►42.00+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►4.00+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►65.45+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►25.45+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►9.09+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►59.49+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►29.54+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►9.70+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►57.40+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►33.11+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►8.61+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►57.43+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►33.90+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►7.55+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►1.13+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►53.25+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►37.31+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►7.93+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►1.38+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►52.99+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►38.36+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►6.90+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►1.65+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►54.75+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►36.85+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►6.46+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►1.89+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►55.30+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►35.85+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►7.12+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►1.66+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►55.65+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►35.73+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►6.42+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►2.17+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►57.99+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►33.53+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►6.29+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►2.11+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►56.86+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►34.51+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►6.07+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►2.46+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►58.59+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►33.64+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►5.55+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►2.16+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►58.09+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►34.37+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►5.25+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►2.25+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

Coverage (%)	Name	Source Location	Module
►57.40+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►35.81+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►4.81+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►1.94+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run 1x1

Source file and lines	BsplineFunctor.h:284-339
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:284,291-339.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. 89% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 41.83 to 38.92 cycles (1.07x speedup).

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.
98% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
79% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 896 bytes. The binary function is storing 968 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	231
loop length	924
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

27.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	6.50	6.50	6.50	6.50	6.50	6.50	30.00	30.00	24.00	24.00	41.83	41.50	41.67	0.50	0.50
cycles	3.50	3.50	6.50	6.50	6.50	6.50	6.50	6.50	30.00	30.00	24.00	24.00	41.83	41.50	41.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.13
Overall L1	41.83

Vectorization ratios

INT

all	79%
load	75%
store	98%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	79%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	79%
load	75%
store	98%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	79%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 41.83 cycles. At this rate:

22% of peak load performance is reached (21.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
48% of peak store performance is reached (23.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 416a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB W11, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417104 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADDVL SP, SP, #32	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL SP, SP, #40	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X8, SP, #31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR D4, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SBFM X10, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W14, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W17, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X4, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X6, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADDVL X8, X8, #25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [X8, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADDVL X8, SP, #31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X8, X8, #25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMUL D7, D4, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X15, [X8, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X5, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X7, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 416acc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP W17, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4170e8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X0, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D15, D14, [X0, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D11, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CNTD X18, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ORR W17, WZR, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D19, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D25, D24, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D26, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D12, D9, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D10, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D21, D20, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D23, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D22, D18, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D2, D3, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D5, D6, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D16, D17, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D8, D31, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D30, D28, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D29, D27, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X11, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z4, [SP, #49, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z14, [SP, #47, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z9, [SP, #45, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z18, [SP, #43, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #55, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z8, [SP, #48, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z12, [SP, #46, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z10, [SP, #44, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z2, [SP, #40, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #54, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #53, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #52, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #51, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #50, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP D0, D1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Z1, [SP, #41, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #42, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X18, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 416bd8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR Z18.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z0.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z13.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z12.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR Z14.D, Z11.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z11.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z10.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z9.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
B 416f04 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR Z8.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z7.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z4, [SP, #55, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Z15, [SP, #21, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
RDVL X0, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR Z5, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR W1, WZR, #1887	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z1.D, Z1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR X18, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X0, X0, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z6, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z16, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z17, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z13, [SP, #20, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MADD X0, X0, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR Z11, [SP, #19, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z19, [SP, #18, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
AND X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z21, [SP, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z20, [SP, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z22, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z3, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z8, [SP, #22, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z25, [SP, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z24, [SP, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z26, [SP, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z23, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z31, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z30, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z28, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z29, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z27, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z4, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #54, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #39, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #53, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #38, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #52, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #37, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z15.D, Z0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [SP, #48, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Z4, [SP, #36, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z14.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z14.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z18.D, Z31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #35, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #51, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #34, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #50, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #33, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z8.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #32, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z13.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z13.D, Z22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z22.D, Z27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #31, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z11.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z11.D, Z20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z20.D, Z28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #30, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z19.D, Z30.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #29, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #28, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z24.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #27, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z26.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #26, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z12.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z12.D, Z23.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #25, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #24, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z10.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z10.D, Z21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z21.D, Z29.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #23, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z5.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z5.D, Z6.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z6.D, Z16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z16.D, Z17.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z17.D, Z0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR Z7, [SP, #22, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z18, [SP, #21, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z0, [SP, #20, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z14, [SP, #19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z19, [SP, #18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z25, [SP, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z24, [SP, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z26, [SP, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z21, [SP, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z20, [SP, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z23, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z22, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z4, [SP, #49, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z13, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z12, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z11, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z10, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z9, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z31, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z30, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z28, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z29, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z27, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMP X0, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4170e8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X16, X0,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X15, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X17, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADDVL SP, SP, #31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL SP, SP, #25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP D15, D14, [SP], #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run 1x1

Source file and lines	BsplineFunctor.h:284-339
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:284,291-339.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

79% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.
98% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
79% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 896 bytes. The binary function is storing 968 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	231
loop length	924
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

27.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	6.50	6.50	6.50	6.50	6.50	6.50	30.00	30.00	24.00	24.00	41.83	41.50	41.67	0.50	0.50
cycles	3.50	3.50	6.50	6.50	6.50	6.50	6.50	6.50	30.00	30.00	24.00	24.00	41.83	41.50	41.67	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	27.13
Overall L1	41.83

Vectorization ratios

INT

all	79%
load	75%
store	98%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	79%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	79%
load	75%
store	98%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	79%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 41.83 cycles. At this rate:

22% of peak load performance is reached (21.42 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
48% of peak store performance is reached (23.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 416a40

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB W11, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417104 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADDVL SP, SP, #32	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL SP, SP, #40	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X8, SP, #31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR D4, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
SBFM X10, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W14, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W17, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X4, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X6, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADDVL X8, X8, #25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDR X16, [X8, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADDVL X8, SP, #31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL X8, X8, #25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
FMUL D7, D4, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR X15, [X8, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X5, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X10, X7, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
B 416acc <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x8c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
CMP W17, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 4170e8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D0, [X0, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D15, D14, [X0, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D11, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CNTD X18, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ORR W17, WZR, W17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR D19, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D25, D24, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D26, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D12, D9, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D10, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D21, D20, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D23, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D22, D18, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D2, D3, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D5, D6, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D16, D17, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D8, D31, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D30, D28, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D29, D27, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X11, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR Z4, [SP, #49, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z14, [SP, #47, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z9, [SP, #45, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z18, [SP, #43, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #55, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z8, [SP, #48, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z12, [SP, #46, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z10, [SP, #44, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z2, [SP, #40, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #54, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #53, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #52, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #51, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X0, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Z0, [SP, #50, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP D0, D1, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Z1, [SP, #41, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z0, [SP, #42, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
CMP X18, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 416bd8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x198>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR Z18.D, Z15.D, Z15.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z0.D, Z13.D, Z13.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z13.D, Z3.D, Z3.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z12.D, Z5.D, Z5.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X0, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR Z14.D, Z11.D, Z11.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z11.D, Z6.D, Z6.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z10.D, Z16.D, Z16.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR Z9.D, Z17.D, Z17.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
B 416f04 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x4c4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR Z8.D, Z7.D, Z7.D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z7.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z4, [SP, #55, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Z15, [SP, #21, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
RDVL X0, #1	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STR Z5, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR W1, WZR, #1887	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP Z1.D, Z1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
PTRUE P0.D, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ORR X18, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X0, X0, #4, #63	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z6, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z2.D, Z2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z16, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z17, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z13, [SP, #20, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MADD X0, X0, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR Z11, [SP, #19, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z19, [SP, #18, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
AND X0, X0, X17	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR Z21, [SP, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z20, [SP, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z22, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z3, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z3.D, Z3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z8, [SP, #22, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z25, [SP, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z24, [SP, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z26, [SP, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z23, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z31, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z30, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z28, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z29, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z27, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Z4, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #54, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #39, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #53, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #38, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #52, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #37, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z15.D, Z0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [SP, #48, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Z4, [SP, #36, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z14.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z14.D, Z18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z18.D, Z31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #35, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #51, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #34, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Z4, [SP, #50, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP Z4.D, Z4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #33, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z8.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #32, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z13.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z13.D, Z22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z22.D, Z27.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #31, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z11.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z11.D, Z20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z20.D, Z28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #30, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z19.D, Z30.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #29, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #28, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z24.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #27, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z26.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #26, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z12.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z12.D, Z23.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #25, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #24, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z10.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z10.D, Z21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z21.D, Z29.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STR Z4, [SP, #23, MUL VL]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP Z4.D, Z5.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z5.D, Z6.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z6.D, Z16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z16.D, Z17.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP Z17.D, Z0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Z0, [SP, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR Z7, [SP, #22, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z18, [SP, #21, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z0, [SP, #20, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z14, [SP, #19, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z19, [SP, #18, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z25, [SP, #17, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z24, [SP, #16, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z26, [SP, #15, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z21, [SP, #14, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z20, [SP, #13, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z23, [SP, #12, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z22, [SP, #11, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z4, [SP, #49, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z13, [SP, #10, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z12, [SP, #9, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z11, [SP, #8, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z10, [SP, #7, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z9, [SP, #6, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z31, [SP, #5, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z30, [SP, #4, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z28, [SP, #3, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z29, [SP, #2, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Z27, [SP, #1, MUL VL]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
CMP X0, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 4170e8 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6a8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X16, X0,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X15, X0,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X17, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
ADDVL SP, SP, #31	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
ADDVL SP, SP, #25	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP D15, D14, [SP], #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

▶Scalability Runs Description

Run 1x1	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_NUM_THREADS: 1OMP_PLACES: threads
Run 1x2	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 2OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x4	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 4OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x8	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 8OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x16	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 16OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x24	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 24OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x32	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 32OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x40	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 40OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x48	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 48OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x56	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 56OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x64	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 64OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x72	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 72OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x80	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 80OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x88	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 88OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads
Run 1x96	Number processes: 1Number nodes: 1Run Command: <executable> -g "4 2 2" -bMPI Command: mpirun -n <number_processes> --bind-to core --map-by package:PE=96 --rank-by fill --report-bindings Dataset: Run Directory: /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/run/oneview_runs/multicore/armclang/oneview_run_1741388363OMP_NUM_THREADS: 96OMP_PROC_BIND: spreadOMP_DISPLAY_AFFINITY: TRUEOMP_AFFINITY_FORMAT: 'OMP: pid %P tid %i thread %n bound to OS proc set {%A}'OMP_DISPLAY_ENV: TRUEOMP_PLACES: threads

(1x1) Efficiency	(1x1) Potential Speed-Up (%)	(1x2) Efficiency	(1x2) Potential Speed-Up (%)	(1x4) Efficiency	(1x4) Potential Speed-Up (%)	(1x8) Efficiency	(1x8) Potential Speed-Up (%)	(1x16) Efficiency	(1x16) Potential Speed-Up (%)	(1x24) Efficiency	(1x24) Potential Speed-Up (%)	(1x32) Efficiency	(1x32) Potential Speed-Up (%)	(1x40) Efficiency	(1x40) Potential Speed-Up (%)	(1x48) Efficiency	(1x48) Potential Speed-Up (%)	(1x56) Efficiency	(1x56) Potential Speed-Up (%)	(1x64) Efficiency	(1x64) Potential Speed-Up (%)	(1x72) Efficiency	(1x72) Potential Speed-Up (%)	(1x80) Efficiency	(1x80) Potential Speed-Up (%)	(1x88) Efficiency	(1x88) Potential Speed-Up (%)	(1x96) Efficiency	(1x96) Potential Speed-Up (%)
1	0	0.91	0.06	0.84	0.1	0.88	0.07	0.9	0.05	0.78	0.11	0.73	0.13	0.63	0.18	0.57	0.22	0.54	0.23	0.49	0.26	0.45	0.27	0.43	0.28	0.39	0.31	0.35	0.34

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency

Run	Number of threads	Efficiency (ideal is 1)	Speedup	Ideal Speedup	Time (s)	Coverage (%)
1x1	1	1	1	1	0.24999997019768	0.58092385530472
1x2	2	0.91	0.91	2	0.27999997138977	0.62910610437393
1x4	4	0.84	0.84	4	0.34499993920326	0.65996491909027
1x8	8	0.88	0.88	8	0.32000005245209	0.59016215801239
1x16	16	0.9	0.9	16	0.3400000333786	0.49059918522835
1x24	24	0.78	0.78	24	0.42999991774559	0.50807726383209
1x32	32	0.73	0.73	32	0.43000000715256	0.48099553585052
1x40	40	0.63	0.63	40	0.45499995350838	0.49945610761642
1x48	48	0.57	0.57	48	0.54999995231628	0.50893187522888
1x56	56	0.54	0.54	56	0.54999989271164	0.49303245544434
1x64	64	0.49	0.49	64	0.61999988555908	0.50021082162857
1x72	72	0.45	0.45	72	0.70500022172928	0.49788752198219
1x80	80	0.43	0.43	80	0.70999962091446	0.48883086442947
1x88	88	0.39	0.39	88	0.79999971389771	0.50885933637619
1x96	96	0.35	0.35	96	0.95000022649765	0.51916950941086

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const–	0.58	0.25
○Loop 264 - BsplineFunctor.h:291-298 - exec	0.49	0.21
○Loop 262 - BsplineFunctor.h:303-336 - exec	0.08	0.04
○Loop 263 - BsplineFunctor.h:302-336 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

▶Scalability Runs Description

▼Columns Filter

Speed-Up and Efficiency

▶Detailed Speed-Up and Efficiency