OV - exec - Loop 599

	Loop Id: 599	Module: exec	Source: BsplineFunctor.h:305-336	Coverage: 0.01%

0x435864 LDP	Q18, Q15, [X10], #32    [5]

0x435868 MOVI	V20.4S, #2

0x43586c MOVI	V28.4S, #3

0x435870 MOVI	V24.4S, #1

0x435874 LDP	W2, W20, [X4, #4]    [14]

0x435878 ADD	X4, X4, #16

0x43587c SBFM	X1, X2, #61, #31

0x435880 SBFM	X5, X20, #61, #31

0x435884 ADD	X17, X9, X1

0x435888 ADD	X13, X1, X8

0x43588c FMUL	V19.2D, V6.2D, V18.2D

0x435890 ADD	X3, X1, X7

0x435894 FMUL	V31.2D, V6.2D, V15.2D

0x435898 FDIV	V23.2D, V6.2D, V15.2D

0x43589c LDR	Q15, [SP, #224]    [4]

0x4358a0 FDIV	V7.2D, V6.2D, V18.2D

0x4358a4 FCVTZS	V16.2D, V19.2D

0x4358a8 FCVTZS	V25.2D, V31.2D

0x4358ac STR	Q23, [SP, #512]    [4]

0x4358b0 FRINTZ	V26.2D, V19.2D

0x4358b4 FRINTZ	V23.2D, V31.2D

0x4358b8 UZP1	V13.4S, V16.4S, V25.4S

0x4358bc FSUB	V30.2D, V19.2D, V26.2D

0x4358c0 LDP	Q19, Q25, [SP, #352]    [4]

0x4358c4 FSUB	V31.2D, V31.2D, V23.2D

0x4358c8 ADD	V29.4S, V13.4S, V20.4S

0x4358cc ADD	V22.4S, V13.4S, V28.4S

0x4358d0 ADD	V27.4S, V13.4S, V24.4S

0x4358d4 SSHLL	V21.2D, V13.2S, #32

0x4358d8 SSHLL2	V20.2D, V13.4S, #32

0x4358dc SSHLL	V2.2D, V29.2S, #32

0x4358e0 SSHLL	V14.2D, V22.2S, #32

0x4358e4 FMOV	X6, D21

0x4358e8 SSHLL2	V4.2D, V22.4S, #32

0x4358ec MOV	X21, V21.D[1]

0x4358f0 SSHLL	V5.2D, V27.2S, #32

0x4358f4 MOV	X18, V20.D[1]

0x4358f8 MOV	X27, V2.D[1]

0x4358fc SSHLL2	V3.2D, V29.4S, #32

0x435900 FMOV	X2, D14

0x435904 SSHLL2	V29.2D, V27.4S, #32

0x435908 MOV	X26, V4.D[1]

0x43590c FMUL	V23.2D, V31.2D, V31.2D

0x435910 MOV	X1, V5.D[1]

0x435914 MOV	X12, V14.D[1]

0x435918 LDR	Q27, [SP, #640]    [4]

0x43591c MOV	X30, V3.D[1]

0x435920 LDR	D8, [X0, X27,LSL #3]    [8]

0x435924 FMOV	X27, D4

0x435928 LDR	D12, [X0, X2,LSL #3]    [8]

0x43592c FMOV	X2, D5

0x435930 LDP	Q5, Q4, [SP, #576]    [4]

0x435934 ORR	V26.16B, V27.16B, V27.16B

0x435938 FMOV	X16, D2

0x43593c LDP	Q21, Q14, [SP, #608]    [4]

0x435940 MOV	X20, V29.D[1]

0x435944 LDR	D9, [X0, X12,LSL #3]    [8]

0x435948 LDR	D18, [X0, X6,LSL #3]    [8]

0x43594c FMOV	X6, D3

0x435950 LDR	D16, [X0, X1,LSL #3]    [8]

0x435954 ORR	V24.16B, V5.16B, V5.16B

0x435958 MOV	V12.D[1], V9.D[0]

0x43595c LDR	D9, [X0, X30,LSL #3]    [8]

0x435960 FMLA	V26.2D, V30.2D, V14.2D

0x435964 FMOV	X30, D20

0x435968 ORR	V22.16B, V21.16B, V21.16B

0x43596c LDR	D10, [X0, X16,LSL #3]    [8]

0x435970 FMLA	V24.2D, V30.2D, V15.2D

0x435974 LDR	D15, [X0, X2,LSL #3]    [8]

0x435978 FMOV	X2, D29

0x43597c LDR	D13, [X0, X6,LSL #3]    [8]

0x435980 FMUL	V29.2D, V30.2D, V30.2D

0x435984 FMLA	V22.2D, V30.2D, V4.2D

0x435988 LDR	D28, [X0, X27,LSL #3]    [8]

0x43598c MOV	V10.D[1], V8.D[0]

0x435990 MOV	V15.D[1], V16.D[0]

0x435994 LDR	D16, [X0, X26,LSL #3]    [8]

0x435998 FMLA	V27.2D, V31.2D, V14.2D

0x43599c LDR	D20, [X0, X30,LSL #3]    [8]

0x4359a0 MOV	V13.D[1], V9.D[0]

0x4359a4 FMLA	V26.2D, V29.2D, V25.2D

0x4359a8 LDR	Q25, [SP, #368]    [4]

0x4359ac LDR	Q3, [SP, #352]    [4]

0x4359b0 MOV	V28.D[1], V16.D[0]

0x4359b4 FMLA	V22.2D, V29.2D, V19.2D

0x4359b8 LDR	D19, [X0, X2,LSL #3]    [8]

0x4359bc LDP	Q2, Q8, [SP, #544]    [4]

0x4359c0 FMLA	V21.2D, V31.2D, V4.2D

0x4359c4 LDURSW	X12, [X4, #496]    [13]

0x4359c8 LDUR	W16, [X4, #508]    [13]

0x4359cc FMLA	V27.2D, V23.2D, V25.2D

0x4359d0 ORR	V25.16B, V5.16B, V5.16B

0x4359d4 LDR	D4, [X0, X21,LSL #3]    [8]

0x4359d8 FMUL	V22.2D, V10.2D, V22.2D

0x4359dc UBFM	X6, X12, #61, #60

0x4359e0 LDR	Q9, [SP, #224]    [4]

0x4359e4 FMLA	V21.2D, V23.2D, V3.2D

0x4359e8 ORR	V11.16B, V8.16B, V8.16B

0x4359ec SBFM	X1, X16, #61, #31

0x4359f0 LDP	Q14, Q16, [SP, #320]    [4]

0x4359f4 ADD	X27, X9, X1

0x4359f8 ADD	X12, X1, X8

0x4359fc FMUL	V3.2D, V29.2D, V1.2D

0x435a00 ADD	X16, X1, X7

0x435a04 FMUL	V26.2D, V12.2D, V26.2D

0x435a08 LDR	Q5, [SP, #448]    [4]

0x435a0c FMLA	V11.2D, V30.2D, V2.2D

0x435a10 MOV	V18.D[1], V4.D[0]

0x435a14 LDR	Q4, [SP, #720]    [4]

0x435a18 FMLA	V25.2D, V31.2D, V9.2D

0x435a1c LDR	D9, [X0, X20,LSL #3]    [8]

0x435a20 FMLA	V16.2D, V30.2D, V14.2D

0x435a24 ORR	V14.16B, V8.16B, V8.16B

0x435a28 MOV	V19.D[1], V9.D[0]

0x435a2c LDR	Q9, [SP, #304]    [4]

0x435a30 FMUL	V8.2D, V29.2D, V30.2D

0x435a34 FMUL	V11.2D, V10.2D, V11.2D

0x435a38 FMLA	V14.2D, V31.2D, V2.2D

0x435a3c FMLA	V16.2D, V29.2D, V9.2D

0x435a40 STR	Q11, [SP, #528]    [4]

0x435a44 LDR	Q11, [SP, #256]    [4]

0x435a48 FMUL	V2.2D, V29.2D, V4.2D

0x435a4c FMUL	V4.2D, V23.2D, V4.2D

0x435a50 FMLA	V22.2D, V15.2D, V16.2D

0x435a54 LDR	Q16, [SP, #480]    [4]

0x435a58 FMLA	V2.2D, V8.2D, V5.2D

0x435a5c LDR	D5, [X0, X18,LSL #3]    [8]

0x435a60 FMLA	V3.2D, V8.2D, V16.2D

0x435a64 LDP	Q9, Q16, [SP, #272]    [4]

0x435a68 MOV	V20.D[1], V5.D[0]

0x435a6c LDR	Q5, [SP, #448]    [4]

0x435a70 FMUL	V24.2D, V12.2D, V24.2D

0x435a74 FMUL	V21.2D, V13.2D, V21.2D

0x435a78 FMUL	V14.2D, V13.2D, V14.2D

0x435a7c FMUL	V25.2D, V28.2D, V25.2D

0x435a80 FMUL	V27.2D, V28.2D, V27.2D

0x435a84 FMLA	V16.2D, V30.2D, V9.2D

0x435a88 FMUL	V9.2D, V23.2D, V31.2D

0x435a8c FMLA	V16.2D, V29.2D, V11.2D

0x435a90 FMLA	V4.2D, V9.2D, V5.2D

0x435a94 FMLA	V26.2D, V18.2D, V16.2D

0x435a98 LDP	Q16, Q11, [SP, #464]    [4]

0x435a9c FMUL	V5.2D, V23.2D, V1.2D

0x435aa0 FADD	V22.2D, V26.2D, V22.2D

0x435aa4 FMLA	V5.2D, V9.2D, V11.2D

0x435aa8 FMUL	V26.2D, V22.2D, V7.2D

0x435aac LDR	Q7, [SP, #432]    [4]

0x435ab0 ORR	V22.16B, V0.16B, V0.16B

0x435ab4 FMLA	V22.2D, V30.2D, V16.2D

0x435ab8 FMUL	V16.2D, V29.2D, V7.2D

0x435abc LDP	Q11, Q7, [SP, #192]    [4]

0x435ac0 FADD	V2.2D, V2.2D, V22.2D

0x435ac4 FMLA	V7.2D, V30.2D, V11.2D

0x435ac8 FMUL	V22.2D, V2.2D, V10.2D

0x435acc LDR	Q10, [SP, #400]    [4]

0x435ad0 LDR	Q2, [SP, #496]    [4]

0x435ad4 FMUL	V29.2D, V29.2D, V10.2D

0x435ad8 LDP	Q11, Q10, [SP, #416]    [4]

0x435adc FMLA	V16.2D, V8.2D, V11.2D

0x435ae0 LDR	Q11, [SP, #384]    [4]

0x435ae4 FMLA	V29.2D, V8.2D, V11.2D

0x435ae8 LDR	Q11, [SP, #528]    [4]

0x435aec FMLA	V11.2D, V15.2D, V7.2D

0x435af0 LDP	Q7, Q8, [SP, #160]    [4]

0x435af4 FMLA	V8.2D, V30.2D, V7.2D

0x435af8 ORR	V7.16B, V0.16B, V0.16B

0x435afc FMLA	V24.2D, V18.2D, V8.2D

0x435b00 ORR	V8.16B, V17.16B, V17.16B

0x435b04 FMLA	V8.2D, V30.2D, V2.2D

0x435b08 LDR	Q2, [SP, #464]    [4]

0x435b0c FADD	V24.2D, V24.2D, V11.2D

0x435b10 FMUL	V11.2D, V23.2D, V10.2D

0x435b14 FMLA	V7.2D, V31.2D, V2.2D

0x435b18 FADD	V3.2D, V3.2D, V8.2D

0x435b1c FMUL	V8.2D, V3.2D, V12.2D

0x435b20 LDR	Q12, [SP, #240]    [4]

0x435b24 FADD	V4.2D, V4.2D, V7.2D

0x435b28 LDP	Q10, Q7, [SP, #400]    [4]

0x435b2c FMUL	V24.2D, V24.2D, V12.2D

0x435b30 FMLA	V11.2D, V9.2D, V7.2D

0x435b34 STR	D24, [X9, X6]    [3]

0x435b38 LDR	Q12, [SP, #384]    [4]

0x435b3c FMUL	V7.2D, V13.2D, V4.2D

0x435b40 LDR	Q2, [SP, #496]    [4]

0x435b44 ST1	{V24.D[1]}, [X17]    [10]

0x435b48 LDP	Q13, Q3, [SP, #192]    [4]

0x435b4c ORR	V24.16B, V17.16B, V17.16B

0x435b50 FMUL	V10.2D, V23.2D, V10.2D

0x435b54 FMLA	V24.2D, V31.2D, V2.2D

0x435b58 FMLA	V10.2D, V9.2D, V12.2D

0x435b5c LDP	Q9, Q12, [SP, #304]    [4]

0x435b60 FMLA	V3.2D, V31.2D, V13.2D

0x435b64 LDP	Q4, Q13, [SP, #160]    [4]

0x435b68 FADD	V5.2D, V5.2D, V24.2D

0x435b6c FMLA	V14.2D, V19.2D, V3.2D

0x435b70 LDP	Q3, Q2, [SP, #656]    [4]

0x435b74 FMUL	V28.2D, V28.2D, V5.2D

0x435b78 FMLA	V13.2D, V31.2D, V4.2D

0x435b7c FMLA	V25.2D, V20.2D, V13.2D

0x435b80 LDR	Q13, [SP, #288]    [4]

0x435b84 FADD	V14.2D, V25.2D, V14.2D

0x435b88 LDR	Q25, [SP, #336]    [4]

0x435b8c FMLA	V25.2D, V31.2D, V12.2D

0x435b90 FMLA	V25.2D, V23.2D, V9.2D

0x435b94 LDP	Q12, Q9, [SP, #256]    [4]

0x435b98 FMLA	V21.2D, V19.2D, V25.2D

0x435b9c FMLA	V13.2D, V31.2D, V9.2D

0x435ba0 FMLA	V13.2D, V23.2D, V12.2D

0x435ba4 ORR	V23.16B, V2.16B, V2.16B

0x435ba8 FMLA	V23.2D, V30.2D, V3.2D

0x435bac FMLA	V27.2D, V20.2D, V13.2D

0x435bb0 FADD	V29.2D, V29.2D, V23.2D

0x435bb4 FMLA	V8.2D, V18.2D, V29.2D

0x435bb8 FADD	V18.2D, V27.2D, V21.2D

0x435bbc LDR	Q21, [SP, #512]    [4]

0x435bc0 LDP	Q27, Q13, [SP, #688]    [4]

0x435bc4 ORR	V24.16B, V13.16B, V13.16B

0x435bc8 FMLA	V13.2D, V31.2D, V27.2D

0x435bcc FMLA	V24.2D, V30.2D, V27.2D

0x435bd0 ORR	V30.16B, V2.16B, V2.16B

0x435bd4 FMLA	V30.2D, V31.2D, V3.2D

0x435bd8 FADD	V31.2D, V11.2D, V13.2D

0x435bdc LDR	Q11, [SP, #240]    [4]

0x435be0 FADD	V16.2D, V16.2D, V24.2D

0x435be4 FMLA	V7.2D, V19.2D, V31.2D

0x435be8 FMLA	V22.2D, V15.2D, V16.2D

0x435bec FADD	V15.2D, V10.2D, V30.2D

0x435bf0 FMUL	V19.2D, V18.2D, V21.2D

0x435bf4 FMLA	V28.2D, V20.2D, V15.2D

0x435bf8 FADD	V20.2D, V8.2D, V22.2D

0x435bfc FMUL	V8.2D, V14.2D, V11.2D

0x435c00 STR	D8, [X9, X5]    [3]

0x435c04 FADD	V22.2D, V28.2D, V7.2D

0x435c08 ST1	{V8.D[1]}, [X27]    [11]

0x435c0c STR	D26, [X6, X8]    [2]

0x435c10 ST1	{V26.D[1]}, [X13]    [7]

0x435c14 STR	D19, [X5, X8]    [1]

0x435c18 ST1	{V19.D[1]}, [X12]    [6]

0x435c1c STR	D20, [X6, X7]    [2]

0x435c20 ST1	{V20.D[1]}, [X3]    [12]

0x435c24 STR	D22, [X5, X7]    [1]

0x435c28 ST1	{V22.D[1]}, [X16]    [9]

0x435c2c CMP	X4, X28

0x435c30 B.NE	435864

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module
►99.49+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:315	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	miniqmc.cpp:451	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P8, P9, P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:305-336
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	42.50
CQA cycles if no scalar integer	40.50
CQA cycles if FP arith vectorized	42.50
CQA cycles if fully vectorized	40.00
Front-end cycles	30.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	42.50
P9 cycles	42.50
P10 cycles	42.50
P11 cycles	42.50
P12 cycles	25.00
P13 cycles	25.00
P14 cycles	25.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	244.00
Nb uops	244.00
Nb loads	NA
Nb stores	14.00
Nb stack references	0.00
FLOP/cycle	7.15
Nb FLOP add-sub	32.00
Nb FLOP mul	60.00
Nb FLOP fma	104.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.12
Bytes prefetched	0.00
Bytes loaded	1104.00
Bytes stored	176.00
Stride 0	2.00
Stride 1	1.00
Stride n	1.00
Stride unknown	8.00
Stride indirect	2.00
Vectorization ratio all	75.88
Vectorization ratio load	72.41
Vectorization ratio store	14.29
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	49.06
Vector-efficiency ratio all	85.86
Vector-efficiency ratio load	86.21
Vector-efficiency ratio store	57.14
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	65.57

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.39
Bottlenecks	P8, P9, P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source	BsplineFunctor.h:305-336
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	42.50
CQA cycles if no scalar integer	40.50
CQA cycles if FP arith vectorized	42.50
CQA cycles if fully vectorized	40.00
Front-end cycles	30.50
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	42.50
P9 cycles	42.50
P10 cycles	42.50
P11 cycles	42.50
P12 cycles	25.00
P13 cycles	25.00
P14 cycles	25.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	244.00
Nb uops	244.00
Nb loads	NA
Nb stores	14.00
Nb stack references	0.00
FLOP/cycle	7.15
Nb FLOP add-sub	32.00
Nb FLOP mul	60.00
Nb FLOP fma	104.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	30.12
Bytes prefetched	0.00
Bytes loaded	1104.00
Bytes stored	176.00
Stride 0	2.00
Stride 1	1.00
Stride n	1.00
Stride unknown	8.00
Stride indirect	2.00
Vectorization ratio all	75.88
Vectorization ratio load	72.41
Vectorization ratio store	14.29
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	49.06
Vector-efficiency ratio all	85.86
Vector-efficiency ratio load	86.21
Vector-efficiency ratio store	57.14
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	65.57

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 42.50 to 40.00 cycles (1.06x speedup).

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

72% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
49% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 104 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (104 inside FMA instructions)
164: multiply (104 inside FMA instructions)
4: divide

The binary loop is loading 1104 bytes. The binary loop is storing 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	244
loop length	976
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	42.50	42.50	42.50	42.50	25.00	25.00	25.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	42.50	42.50	42.50	42.50	25.00	25.00	25.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-13.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	30.50
Data deps.	1.00
Overall L1	42.50

Vectorization ratios

INT

all	59%
load	72%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	33%

INT+FP

all	75%
load	72%
store	14%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	49%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.50 cycles. At this rate:

27% of peak load performance is reached (25.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 435864

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q18, Q15, [X10], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVI V20.4S, #2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V28.4S, #3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V24.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDP W2, W20, [X4, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X1, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X20, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X9, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X1, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V19.2D, V6.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ADD X3, X1, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V31.2D, V6.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV V23.2D, V6.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR Q15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV V7.2D, V6.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FCVTZS V16.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCVTZS V25.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
STR Q23, [SP, #512]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FRINTZ V26.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FRINTZ V23.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
UZP1 V13.4S, V16.4S, V25.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V30.2D, V19.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q19, Q25, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FSUB V31.2D, V31.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V29.4S, V13.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V22.4S, V13.4S, V28.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V27.4S, V13.4S, V24.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SSHLL V21.2D, V13.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL2 V20.2D, V13.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL V2.2D, V29.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL V14.2D, V22.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X6, D21	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V4.2D, V22.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X21, V21.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
SSHLL V5.2D, V27.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X18, V20.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV X27, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
SSHLL2 V3.2D, V29.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X2, D14	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V29.2D, V27.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X26, V4.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMUL V23.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOV X1, V5.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV X12, V14.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR Q27, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOV X30, V3.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D8, [X0, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X27, D4	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D12, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X2, D5	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDP Q5, Q4, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V26.16B, V27.16B, V27.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMOV X16, D2	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDP Q21, Q14, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
MOV X20, V29.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D9, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D18, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X6, D3	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D16, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ORR V24.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOV V12.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D9, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V26.2D, V30.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMOV X30, D20	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ORR V22.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D10, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V24.2D, V30.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D15, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X2, D29	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D13, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V29.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V22.2D, V30.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D28, [X0, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV V10.D[1], V8.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MOV V15.D[1], V16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D16, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V27.2D, V31.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D20, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV V13.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V26.2D, V29.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q3, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOV V28.D[1], V16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V22.2D, V29.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D19, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP Q2, Q8, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V21.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDURSW X12, [X4, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR W16, [X4, #508]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FMLA V27.2D, V23.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V25.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D4, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V22.2D, V10.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
UBFM X6, X12, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V21.2D, V23.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V11.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SBFM X1, X16, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q14, Q16, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X27, X9, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X1, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V3.2D, V29.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ADD X16, X1, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V26.2D, V12.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q5, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V11.2D, V30.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
MOV V18.D[1], V4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q4, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V25.2D, V31.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D9, [X0, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V16.2D, V30.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V14.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOV V19.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q9, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V8.2D, V29.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V11.2D, V10.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V14.2D, V31.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V16.2D, V29.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q11, [SP, #528]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V2.2D, V29.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V4.2D, V23.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V22.2D, V15.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q16, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V2.2D, V8.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D5, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V3.2D, V8.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q9, Q16, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
MOV V20.D[1], V5.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q5, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V24.2D, V12.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V13.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V14.2D, V13.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V25.2D, V28.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V27.2D, V28.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V16.2D, V30.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V9.2D, V23.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V16.2D, V29.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V4.2D, V9.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V26.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q16, Q11, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V5.2D, V23.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V22.2D, V26.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V5.2D, V9.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V26.2D, V22.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q7, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR V22.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V22.2D, V30.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V16.2D, V29.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q11, Q7, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V2.2D, V2.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V7.2D, V30.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V22.2D, V2.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q10, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V29.2D, V29.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q11, Q10, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V16.2D, V8.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q11, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V29.2D, V8.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q11, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V11.2D, V15.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q7, Q8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V8.2D, V30.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V7.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V24.2D, V18.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V8.16B, V17.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V8.2D, V30.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q2, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V24.2D, V24.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V11.2D, V23.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V7.2D, V31.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V3.2D, V3.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V8.2D, V3.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V4.2D, V4.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q10, Q7, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V24.2D, V24.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V11.2D, V9.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR D24, [X9, X6]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR Q12, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V7.2D, V13.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q2, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ST1 {V24.D[1]}, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDP Q13, Q3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V24.16B, V17.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V10.2D, V23.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V24.2D, V31.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V10.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q9, Q12, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V3.2D, V31.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q4, Q13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V5.2D, V5.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V14.2D, V19.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q3, Q2, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V28.2D, V28.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V20.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V14.2D, V25.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V25.2D, V31.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V23.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q12, Q9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V21.2D, V19.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V23.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V23.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V23.2D, V30.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V27.2D, V20.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V29.2D, V29.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V8.2D, V18.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V18.2D, V27.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q21, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q27, Q13, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V24.16B, V13.16B, V13.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V24.2D, V30.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V30.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V30.2D, V31.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V31.2D, V11.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V16.2D, V16.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V7.2D, V19.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V22.2D, V15.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V15.2D, V10.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V18.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V28.2D, V20.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V20.2D, V8.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V8.2D, V14.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D8, [X9, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FADD V22.2D, V28.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ST1 {V8.D[1]}, [X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D26, [X6, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V26.D[1]}, [X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D19, [X5, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V19.D[1]}, [X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D20, [X6, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V20.D[1]}, [X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D22, [X5, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V22.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
CMP X4, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 435864 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

75% of VPU instructions are used in vector version (process two or more data elements in vector registers):

72% of VPU loads are used in vector version.
14% of VPU stores are used in vector version.
49% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 104 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (104 inside FMA instructions)
164: multiply (104 inside FMA instructions)
4: divide

The binary loop is loading 1104 bytes. The binary loop is storing 176 bytes.

Arithmetic intensity

Arithmetic intensity is 0.24 FP operations per loaded or stored byte.

General properties

nb instructions	244
loop length	976
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	42.50	42.50	42.50	42.50	25.00	25.00	25.00	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	42.50	42.50	42.50	42.50	25.00	25.00	25.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-13.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	30.50
Data deps.	1.00
Overall L1	42.50

Vectorization ratios

INT

all	59%
load	72%
store	14%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	53%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	33%

INT+FP

all	75%
load	72%
store	14%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	49%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 42.50 cycles. At this rate:

27% of peak load performance is reached (25.98 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
8% of peak store performance is reached (4.14 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 435864

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q18, Q15, [X10], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVI V20.4S, #2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V28.4S, #3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V24.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDP W2, W20, [X4, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X1, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X20, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X17, X9, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X13, X1, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V19.2D, V6.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ADD X3, X1, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V31.2D, V6.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV V23.2D, V6.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR Q15, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV V7.2D, V6.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
FCVTZS V16.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCVTZS V25.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
STR Q23, [SP, #512]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FRINTZ V26.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FRINTZ V23.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
UZP1 V13.4S, V16.4S, V25.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V30.2D, V19.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q19, Q25, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FSUB V31.2D, V31.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V29.4S, V13.4S, V20.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V22.4S, V13.4S, V28.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V27.4S, V13.4S, V24.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SSHLL V21.2D, V13.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL2 V20.2D, V13.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL V2.2D, V29.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL V14.2D, V22.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X6, D21	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V4.2D, V22.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X21, V21.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
SSHLL V5.2D, V27.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X18, V20.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV X27, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
SSHLL2 V3.2D, V29.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X2, D14	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V29.2D, V27.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X26, V4.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMUL V23.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOV X1, V5.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV X12, V14.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR Q27, [SP, #640]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOV X30, V3.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D8, [X0, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X27, D4	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D12, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X2, D5	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDP Q5, Q4, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V26.16B, V27.16B, V27.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMOV X16, D2	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDP Q21, Q14, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
MOV X20, V29.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D9, [X0, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D18, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X6, D3	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D16, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ORR V24.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOV V12.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D9, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V26.2D, V30.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMOV X30, D20	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ORR V22.16B, V21.16B, V21.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D10, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V24.2D, V30.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D15, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X2, D29	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D13, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V29.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V22.2D, V30.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D28, [X0, X27,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV V10.D[1], V8.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
MOV V15.D[1], V16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D16, [X0, X26,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V27.2D, V31.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D20, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV V13.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V26.2D, V29.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q3, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOV V28.D[1], V16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V22.2D, V29.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D19, [X0, X2,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP Q2, Q8, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V21.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDURSW X12, [X4, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
LDUR W16, [X4, #508]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
FMLA V27.2D, V23.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V25.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D4, [X0, X21,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V22.2D, V10.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
UBFM X6, X12, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q9, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V21.2D, V23.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V11.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SBFM X1, X16, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q14, Q16, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X27, X9, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X12, X1, X8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V3.2D, V29.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ADD X16, X1, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V26.2D, V12.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q5, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V11.2D, V30.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
MOV V18.D[1], V4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q4, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V25.2D, V31.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D9, [X0, X20,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V16.2D, V30.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V14.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOV V19.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q9, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V8.2D, V29.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V11.2D, V10.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V14.2D, V31.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V16.2D, V29.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q11, [SP, #528]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q11, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V2.2D, V29.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V4.2D, V23.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V22.2D, V15.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q16, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V2.2D, V8.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D5, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V3.2D, V8.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q9, Q16, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
MOV V20.D[1], V5.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q5, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V24.2D, V12.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V13.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V14.2D, V13.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V25.2D, V28.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V27.2D, V28.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V16.2D, V30.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V9.2D, V23.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V16.2D, V29.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V4.2D, V9.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V26.2D, V18.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q16, Q11, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V5.2D, V23.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V22.2D, V26.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V5.2D, V9.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V26.2D, V22.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q7, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ORR V22.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V22.2D, V30.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V16.2D, V29.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q11, Q7, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V2.2D, V2.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V7.2D, V30.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V22.2D, V2.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q10, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q2, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V29.2D, V29.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q11, Q10, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V16.2D, V8.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q11, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V29.2D, V8.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q11, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V11.2D, V15.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q7, Q8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V8.2D, V30.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V7.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V24.2D, V18.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V8.16B, V17.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V8.2D, V30.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q2, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V24.2D, V24.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V11.2D, V23.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V7.2D, V31.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V3.2D, V3.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V8.2D, V3.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q12, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V4.2D, V4.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q10, Q7, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V24.2D, V24.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V11.2D, V9.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR D24, [X9, X6]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
LDR Q12, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V7.2D, V13.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q2, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ST1 {V24.D[1]}, [X17]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDP Q13, Q3, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V24.16B, V17.16B, V17.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V10.2D, V23.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V24.2D, V31.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V10.2D, V9.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q9, Q12, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V3.2D, V31.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q4, Q13, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V5.2D, V5.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V14.2D, V19.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q3, Q2, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V28.2D, V28.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V20.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V14.2D, V25.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q25, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V25.2D, V31.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V23.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q12, Q9, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V21.2D, V19.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V23.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V23.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V23.2D, V30.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V27.2D, V20.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V29.2D, V29.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V8.2D, V18.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V18.2D, V27.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q21, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q27, Q13, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V24.16B, V13.16B, V13.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V24.2D, V30.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V30.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V30.2D, V31.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V31.2D, V11.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q11, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V16.2D, V16.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V7.2D, V19.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V22.2D, V15.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V15.2D, V10.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V18.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V28.2D, V20.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V20.2D, V8.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V8.2D, V14.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D8, [X9, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FADD V22.2D, V28.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ST1 {V8.D[1]}, [X27]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D26, [X6, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V26.D[1]}, [X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D19, [X5, X8]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V19.D[1]}, [X12]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D20, [X6, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V20.D[1]}, [X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D22, [X5, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V22.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
CMP X4, X28	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 435864 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x624>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code