OV - exec - Loop 3666

	Loop Id: 3666	Module: exec	Source: ParticleBConds3DSoa.h:237-255	Coverage: 0.08%

0x50b348 LDR	Q24, [X13, X21]    [4]

0x50b34c LDR	Q17, [X10, X21]    [2]

0x50b350 LDP	D25, D5, [X1, #104]    [6]

0x50b354 FSUB	V19.2D, V24.2D, V30.2D

0x50b358 LDR	Q21, [X5, X21]    [1]

0x50b35c LDP	D6, D23, [X1, #72]    [6]

0x50b360 FSUB	V27.2D, V17.2D, V31.2D

0x50b364 LDP	D22, D3, [X1, #88]    [6]

0x50b368 FMUL	V28.2D, V19.2D, V25.D[0]

0x50b36c LDP	D18, D16, [X1, #120]    [6]

0x50b370 FSUB	V26.2D, V21.2D, V29.2D

0x50b374 FMUL	V2.2D, V19.2D, V23.D[0]

0x50b378 LDR	D17, [X1, #136]    [6]

0x50b37c LDP	D0, D1, [X1, #8]    [6]

0x50b380 FMLA	V28.2D, V27.2D, V3.D[0]

0x50b384 LD1R	{V7.2D}, [X1]    [6]

0x50b388 FMLA	V2.2D, V27.2D, V6.D[0]

0x50b38c FMLA	V28.2D, V26.2D, V5.D[0]

0x50b390 FMUL	V4.2D, V19.2D, V16.D[0]

0x50b394 FMLA	V2.2D, V26.2D, V22.D[0]

0x50b398 FMLA	V4.2D, V27.2D, V18.D[0]

0x50b39c FRINTA	V20.2D, V28.2D

0x50b3a0 FMLA	V4.2D, V26.2D, V17.D[0]

0x50b3a4 FRINTA	V24.2D, V2.2D

0x50b3a8 FSUB	V27.2D, V28.2D, V20.2D

0x50b3ac FRINTA	V21.2D, V4.2D

0x50b3b0 FSUB	V25.2D, V2.2D, V24.2D

0x50b3b4 FMUL	V19.2D, V27.2D, V0.D[0]

0x50b3b8 FSUB	V5.2D, V4.2D, V21.2D

0x50b3bc FMLA	V19.2D, V7.2D, V25.2D

0x50b3c0 FMLA	V19.2D, V5.2D, V1.D[0]

0x50b3c4 STR	Q19, [X16, X21]    [5]

0x50b3c8 LDP	D28, D6, [X1, #24]    [6]

0x50b3cc LDR	D26, [X1, #40]    [6]

0x50b3d0 FMUL	V23.2D, V27.2D, V6.D[0]

0x50b3d4 FMLA	V23.2D, V25.2D, V28.D[0]

0x50b3d8 FMLA	V23.2D, V5.2D, V26.D[0]

0x50b3dc STR	Q23, [X17, X21]    [7]

0x50b3e0 LDP	D2, D22, [X1, #48]    [6]

0x50b3e4 LDR	D18, [X1, #64]    [6]

0x50b3e8 FMUL	V3.2D, V27.2D, V22.D[0]

0x50b3ec FMLA	V3.2D, V25.2D, V2.D[0]

0x50b3f0 FMLA	V3.2D, V5.2D, V18.D[0]

0x50b3f4 STR	Q3, [X18, X21]    [8]

0x50b3f8 LDR	Q16, [X17, X21]    [7]

0x50b3fc LDR	Q4, [X16, X21]    [5]

0x50b400 FMUL	V0.2D, V16.2D, V16.2D

0x50b404 FMLA	V0.2D, V4.2D, V4.2D

0x50b408 FMLA	V0.2D, V3.2D, V3.2D

0x50b40c FSQRT	V1.2D, V0.2D

0x50b410 STR	Q1, [X30, X21]    [3]

0x50b414 ADD	X21, X21, #16

0x50b418 CMP	X21, X25

0x50b41c B.NE	50b348

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 237 - 255

--------------------------------------------------------------------------------

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

Coverage (%)	Name	Source Location	Module
►98.98+	qmcplusplus::ParticleSet::make[...]	ParticleSet.cpp:343	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P8, P9, P10, P11,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	8.88
Front-end cycles	6.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.42
P3 cycles	0.42
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	6.67
P13 cycles	6.67
P14 cycles	6.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 7.52
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.33
Nb FLOP add-sub	12.00
Nb FLOP mul	14.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	92.16
Vectorization ratio load	75.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	96.08
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.01
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	NA
Bottlenecks	P8, P9, P10, P11,
Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source	ParticleBConds3DSoa.h:237-255
Source loop unroll info	multi-versionned
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	9.00
CQA cycles if no scalar integer	9.00
CQA cycles if FP arith vectorized	9.00
CQA cycles if fully vectorized	8.88
Front-end cycles	6.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.42
P3 cycles	0.42
P4 cycles	0.33
P5 cycles	0.33
P6 cycles	0.25
P7 cycles	0.25
P8 cycles	9.00
P9 cycles	9.00
P10 cycles	9.00
P11 cycles	9.00
P12 cycles	6.67
P13 cycles	6.67
P14 cycles	6.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	3.50 - 7.52
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	54.00
Nb uops	54.00
Nb loads	NA
Nb stores	4.00
Nb stack references	0.00
FLOP/cycle	9.33
Nb FLOP add-sub	12.00
Nb FLOP mul	14.00
Nb FLOP fma	28.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	2.00
Nb FLOP rsqrt	0.00
Bytes/cycle	32.00
Bytes prefetched	0.00
Bytes loaded	224.00
Bytes stored	64.00
Stride 0	1.00
Stride 1	7.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	92.16
Vectorization ratio load	75.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	100.00
Vector-efficiency ratio all	96.08
Vector-efficiency ratio load	87.50
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	100.00

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 96% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 9.00 to 8.87 cycles (1.01x speedup).

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 84 FP arithmetical operations:

40: addition or subtraction (28 inside FMA instructions)
42: multiply (28 inside FMA instructions)
2: square root

The binary loop is loading 224 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.42	0.42	0.33	0.33	0.25	0.25	9.00	9.00	9.00	9.00	6.67	6.67	6.67	0.00	0.00
cycles	0.50	0.50	0.42	0.42	0.33	0.33	0.25	0.25	9.00	9.00	9.00	9.00	6.67	6.67	6.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	3.50-7.52
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

INT

all	80%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	92%
load	75%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

25% of peak load performance is reached (24.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50b348

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q24, [X13, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q17, [X10, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D25, D5, [X1, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V19.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q21, [X5, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D6, D23, [X1, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V27.2D, V17.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP D22, D3, [X1, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V28.2D, V19.2D, V25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP D18, D16, [X1, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V26.2D, V21.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V2.2D, V19.2D, V23.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR D17, [X1, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D0, D1, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V28.2D, V27.2D, V3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1R {V7.2D}, [X1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
FMLA V2.2D, V27.2D, V6.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V28.2D, V26.2D, V5.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V4.2D, V19.2D, V16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V2.2D, V26.2D, V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V4.2D, V27.2D, V18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FRINTA V20.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA V4.2D, V26.2D, V17.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FRINTA V24.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB V27.2D, V28.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FRINTA V21.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB V25.2D, V2.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V27.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FSUB V5.2D, V4.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V19.2D, V7.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V19.2D, V5.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q19, [X16, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDP D28, D6, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D26, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V23.2D, V27.2D, V6.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V23.2D, V25.2D, V28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V23.2D, V5.2D, V26.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q23, [X17, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDP D2, D22, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D18, [X1, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V3.2D, V27.2D, V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V3.2D, V25.2D, V2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V3.2D, V5.2D, V18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q3, [X18, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q16, [X17, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q4, [X16, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V0.2D, V16.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V0.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V0.2D, V3.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FSQRT V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (100.0%)
STR Q1, [X30, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X21, X21, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 50b348 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	qmcplusplus::SoaDistanceTableABOMPTarget::move(qmcplusplus::ParticleSet const&, qmcplusplus::TinyVector const&, int, bool)
Source file and lines	ParticleBConds3DSoa.h:237-255
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:237-255.

The related source loop is multi-versionned.

gain
potential
hint
expert

Vectorization

Details

92% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Detected 28 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 84 FP arithmetical operations:

40: addition or subtraction (28 inside FMA instructions)
42: multiply (28 inside FMA instructions)
2: square root

The binary loop is loading 224 bytes. The binary loop is storing 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.29 FP operations per loaded or stored byte.

General properties

nb instructions	54
loop length	216
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.42	0.42	0.33	0.33	0.25	0.25	9.00	9.00	9.00	9.00	6.67	6.67	6.67	0.00	0.00
cycles	0.50	0.50	0.42	0.42	0.33	0.33	0.25	0.25	9.00	9.00	9.00	9.00	6.67	6.67	6.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	3.50-7.52
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	6.75
Data deps.	1.00
Overall L1	9.00

Vectorization ratios

INT

all	80%
load	75%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

INT+FP

all	92%
load	75%
store	100%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	100%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 9.00 cycles. At this rate:

25% of peak load performance is reached (24.89 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
14% of peak store performance is reached (7.11 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 50b348

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDR Q24, [X13, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q17, [X10, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D25, D5, [X1, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V19.2D, V24.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q21, [X5, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D6, D23, [X1, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V27.2D, V17.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP D22, D3, [X1, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V28.2D, V19.2D, V25.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP D18, D16, [X1, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FSUB V26.2D, V21.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V2.2D, V19.2D, V23.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR D17, [X1, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D0, D1, [X1, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V28.2D, V27.2D, V3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LD1R {V7.2D}, [X1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0.33	0.33	0.33	8	0.33	scal (50.0%)
FMLA V2.2D, V27.2D, V6.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V28.2D, V26.2D, V5.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V4.2D, V19.2D, V16.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V2.2D, V26.2D, V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V4.2D, V27.2D, V18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FRINTA V20.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FMLA V4.2D, V26.2D, V17.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FRINTA V24.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB V27.2D, V28.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FRINTA V21.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FSUB V25.2D, V2.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V19.2D, V27.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FSUB V5.2D, V4.2D, V21.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V19.2D, V7.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V19.2D, V5.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q19, [X16, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDP D28, D6, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D26, [X1, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V23.2D, V27.2D, V6.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V23.2D, V25.2D, V28.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V23.2D, V5.2D, V26.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q23, [X17, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDP D2, D22, [X1, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR D18, [X1, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V3.2D, V27.2D, V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V3.2D, V25.2D, V2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V3.2D, V5.2D, V18.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
STR Q3, [X18, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
LDR Q16, [X17, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q4, [X16, X21]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V0.2D, V16.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V0.2D, V4.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V0.2D, V3.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FSQRT V1.2D, V0.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-16	3.50-7.52	vect (100.0%)
STR Q1, [X30, X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
ADD X21, X21, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, X25	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 50b348 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE4moveERKNS_11ParticleSetERKNS_10TinyVectorIdLj3EEEib+0x388>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code