OV - exec - Loop 295

0x41a9c8 ORR	X7, XZR, X21

0x41a9cc LDR	D20, [X21, #8]    [3]

0x41a9d0 LDR	D6, [X7], #8    [1]

0x41a9d4 LDP	D4, D3, [X21, #24]    [3]

0x41a9d8 LDP	D7, D28, [X21, #40]    [3]

0x41a9dc ADD	X21, X21, #64

0x41a9e0 FADD	D26, D5, D6

0x41a9e4 LDR	D30, [X7, #8]    [1]

0x41a9e8 LDUR	D19, [X21, #504]    [2]

0x41a9ec FADD	D17, D26, D20

0x41a9f0 FADD	D29, D17, D30

0x41a9f4 FADD	D0, D29, D4

0x41a9f8 FADD	D22, D0, D3

0x41a9fc FADD	D18, D22, D7

0x41aa00 FADD	D1, D18, D28

0x41aa04 FADD	D5, D1, D19

0x41aa08 CMP	X2, X21

0x41aa0c B.NE	41a9c8

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

Coverage (%)	Name	Source Location	Module
►99.12+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.64
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	7.11
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_numeric.h:140-141
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	9.78
CQA cycles if fully vectorized	10.67
Front-end cycles	2.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.58
P7 cycles	0.58
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	33.33
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	57.14
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.64
CQA speedup if fully vectorized	1.50
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	7.11
Bottlenecks
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	stl_numeric.h:140-141
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	16.00
CQA cycles if no scalar integer	16.00
CQA cycles if FP arith vectorized	9.78
CQA cycles if fully vectorized	10.67
Front-end cycles	2.25
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	0.75
P3 cycles	0.75
P4 cycles	0.67
P5 cycles	0.67
P6 cycles	0.58
P7 cycles	0.58
P8 cycles	2.00
P9 cycles	2.00
P10 cycles	2.00
P11 cycles	2.00
P12 cycles	2.00
P13 cycles	2.00
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	16
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	18.00
Nb uops	18.00
Nb loads	NA
Nb stores	0.00
Nb stack references	0.00
FLOP/cycle	0.50
Nb FLOP add-sub	8.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	4.00
Bytes prefetched	0.00
Bytes loaded	64.00
Bytes stored	0.00
Stride 0	0.00
Stride 1	0.00
Stride n	2.00
Stride unknown	1.00
Stride indirect	0.00
Vectorization ratio all	14.29
Vectorization ratio load	33.33
Vectorization ratio store	NA
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	57.14
Vector-efficiency ratio load	66.67
Vector-efficiency ratio store	NA
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in /opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_numeric.h:140-141.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 10.67 cycles (1.50x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.75	0.75	0.67	0.67	0.58	0.58	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.67	0.67	0.58	0.58	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	2.25
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

INT

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41a9c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ORR X7, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D6, [X7], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D4, D3, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D7, D28, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X21, X21, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD D26, D5, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D30, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDUR D19, [X21, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D17, D26, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D29, D17, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D0, D29, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D22, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D18, D22, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D1, D18, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D5, D1, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
CMP X2, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41a9c8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0xf08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	stl_numeric.h:140-141
Module	exec

The loop is defined in /opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_numeric.h:140-141.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 16.00 to 10.67 cycles (1.50x speedup).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 8 FP arithmetical operations:

8: addition or subtraction

The binary loop is loading 64 bytes.

Arithmetic intensity

Arithmetic intensity is 0.12 FP operations per loaded or stored byte.

General properties

nb instructions	18
loop length	72
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	0.75	0.75	0.67	0.67	0.58	0.58	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00
cycles	0.50	0.50	0.75	0.75	0.67	0.67	0.58	0.58	2.00	2.00	2.00	2.00	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	16.00

Cycles summary

Front-end	2.25
Data deps.	16.00
Overall L1	16.00

Vectorization ratios

INT

all	33%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

FP

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	14%
load	33%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 16.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41a9c8

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
ORR X7, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR D20, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDR D6, [X7], #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDP D4, D3, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP D7, D28, [X21, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ADD X21, X21, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD D26, D5, D6	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D30, [X7, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
LDUR D19, [X21, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FADD D17, D26, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D29, D17, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D0, D29, D4	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D22, D0, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D18, D22, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D1, D18, D28	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FADD D5, D1, D19	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
CMP X2, X21	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41a9c8 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0xf08>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code