OV - exec - Function qmcplusplus::SoaDistanceTableAAOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSet&)

	Function: qmcplusplus::SoaDistanceTableAAOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSe ...	Module: exec	Source: SoaDistanceTableAAOMPTarget.h:179-187 [...]	Coverage (incl. loops): 0.08% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

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242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 1128 - 1131

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1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 248

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223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 223 - 255

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223:     const T y0 = pos[1];

224:     const T z0 = pos[2];

[...]

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 271 - 273

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271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

272:   ///return the const pointer of the i-th components

273:   inline const T* restrict data(size_t i) const { return myData + i * nGhosts; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h: 179 - 187

--------------------------------------------------------------------------------

179:   inline void evaluate(ParticleSet& P) override

180:   {

181:     ScopedTimer local_timer(evaluate_timer_);

182:

183:     constexpr T BigR = std::numeric_limits<T>::max();

184:     for (int iat = 1; iat < num_targets_; ++iat)

185:       DTD_BConds<T, D, SC>::computeDistances(P.R[iat], P.getCoordinates().getAllParticlePos(), distances_[iat].data(),

186:                                              displacements_[iat], 0, iat, iat);

187:   }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/RealSpacePositionsOMPTarget.h: 163 - 163

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163:   const PosVectorSoa& getAllParticlePos() const override { return RSoA_hostview; }

0x4ef560 STP	X29, X30, [SP, #912]!

0x4ef564 ADD	X29, SP, #0

0x4ef568 STP	X19, X20, [SP, #16]

0x4ef56c STP	X21, X22, [SP, #32]

0x4ef570 ORR	X21, XZR, X0

0x4ef574 STP	X23, X24, [SP, #48]

0x4ef578 ORR	X23, XZR, X1

0x4ef57c LDR	X19, [X0, #632]

0x4ef580 ORR	X0, XZR, X19

0x4ef584 BL	4be880

0x4ef588 LDR	X10, [X21, #24]

0x4ef58c CMP	X10, #1

0x4ef590 B.LS	4ef858

0x4ef594 ADRP	X24,

0x4ef598 MOVZ	X22, #24

0x4ef59c STP	X25, X26, [SP, #64]

0x4ef5a0 PTRUE	P7.B, ALL

0x4ef5a4 ADD	X24, X24, #2816

0x4ef5a8 MOVZ	X20, #1

0x4ef5ac ADD	X26, X23, #40

0x4ef5b0 MOVZ	W25, #40

0x4ef5b4 STR	X27, [SP, #80]

0x4ef5b8 STR	D15, [SP, #88]

0x4ef5bc STP	D13, D14, [SP, #96]

    (3202) 0x4ef5c0 LDR	X0, [X23, #632]

    (3202) 0x4ef5c4 LDR	X27, [X26, #24]

    (3202) 0x4ef5c8 LDR	X1, [X0]

    (3202) 0x4ef5cc ADD	X27, X27, X22

    (3202) 0x4ef5d0 LDR	X2, [X1, #72]

    (3202) 0x4ef5d4 CMP	X2, X24

    (3202) 0x4ef5d8 B.NE	4ef874

    (3202) 0x4ef5dc ADD	X0, X0, #64

    (3202) 0x4ef5e0 LDR	X7, [X0, #8]

    (3202) 0x4ef5e4 UMADDL	X5, W20, W25, XZR

    (3202) 0x4ef5e8 ORR	W11, WZR, W20

    (3202) 0x4ef5ec LDR	X9, [X0, #24]

    (3202) 0x4ef5f0 LDR	X0, [X21, #96]

    (3202) 0x4ef5f4 LDR	X3, [X21, #72]

    (3202) 0x4ef5f8 ADD	X16, X9, X7,LSL #3

    (3202) 0x4ef5fc LDR	D15, [X27, #16]

    (3202) 0x4ef600 ADD	X17, X9, X7,LSL #4

    (3202) 0x4ef604 ADD	X8, X0, X5

    (3202) 0x4ef608 LDR	X6, [X8, #8]

    (3202) 0x4ef60c ADD	X12, X3, X5

    (3202) 0x4ef610 LDR	X13, [X8, #24]

    (3202) 0x4ef614 LDR	X18, [X12, #24]

    (3202) 0x4ef618 LDP	D14, D13, [X27]

    (3202) 0x4ef61c ADD	X14, X13, X6,LSL #3

    (3202) 0x4ef620 ADD	X15, X13, X6,LSL #4

    (3202) 0x4ef624 CMP	X20, #1

    (3202) 0x4ef628 B.EQ	4ef884

    (3202) 0x4ef62c DUP	V31.2D, V14.D[0]

    (3202) 0x4ef630 DUP	V30.2D, V13.D[0]

    (3202) 0x4ef634 UBFM	W2, W20, #1, #31

    (3202) 0x4ef638 ADD	X1, X21, #280

    (3202) 0x4ef63c DUP	V29.2D, V15.D[0]

    (3202) 0x4ef640 MOVZ	X4, #0

    (3202) 0x4ef644 UBFM	X27, X2, #60, #59

      (3204) 0x4ef648 LDR	Q27, [X16, X4]

      (3204) 0x4ef64c LDR	Q28, [X9, X4]

      (3204) 0x4ef650 LDP	D0, D1, [X1, #104]

      (3204) 0x4ef654 FSUB	V2.2D, V27.2D, V30.2D

      (3204) 0x4ef658 LDR	Q26, [X17, X4]

      (3204) 0x4ef65c LDP	D25, D24, [X1, #72]

      (3204) 0x4ef660 FSUB	V4.2D, V28.2D, V31.2D

      (3204) 0x4ef664 LDP	D23, D3, [X1, #88]

      (3204) 0x4ef668 FMUL	V17.2D, V2.2D, V0.D[0]

      (3204) 0x4ef66c LDP	D18, D16, [X1, #120]

      (3204) 0x4ef670 FSUB	V19.2D, V26.2D, V29.2D

      (3204) 0x4ef674 FMUL	V21.2D, V2.2D, V24.D[0]

      (3204) 0x4ef678 LDP	D5, D6, [X1, #8]

      (3204) 0x4ef67c LD1R	{V7.2D}, [X1]

      (3204) 0x4ef680 FMLA	V17.2D, V4.2D, V3.D[0]

      (3204) 0x4ef684 FMUL	V27.2D, V2.2D, V16.D[0]

      (3204) 0x4ef688 FMLA	V21.2D, V4.2D, V25.D[0]

      (3204) 0x4ef68c FMLA	V17.2D, V19.2D, V1.D[0]

      (3204) 0x4ef690 FMLA	V27.2D, V4.2D, V18.D[0]

      (3204) 0x4ef694 LDR	D4, [X1, #136]

      (3204) 0x4ef698 FMLA	V21.2D, V19.2D, V23.D[0]

      (3204) 0x4ef69c FRINTA	V20.2D, V17.2D

      (3204) 0x4ef6a0 FMLA	V27.2D, V19.2D, V4.D[0]

      (3204) 0x4ef6a4 FRINTA	V22.2D, V21.2D

      (3204) 0x4ef6a8 FSUB	V28.2D, V17.2D, V20.2D

      (3204) 0x4ef6ac FRINTA	V0.2D, V27.2D

      (3204) 0x4ef6b0 FSUB	V26.2D, V21.2D, V22.2D

      (3204) 0x4ef6b4 FMUL	V2.2D, V28.2D, V5.D[0]

      (3204) 0x4ef6b8 FSUB	V17.2D, V27.2D, V0.2D

      (3204) 0x4ef6bc FMLA	V2.2D, V7.2D, V26.2D

      (3204) 0x4ef6c0 FMLA	V2.2D, V17.2D, V6.D[0]

      (3204) 0x4ef6c4 STR	Q2, [X13, X4]

      (3204) 0x4ef6c8 LDP	D1, D25, [X1, #24]

      (3204) 0x4ef6cc LDR	D19, [X1, #40]

      (3204) 0x4ef6d0 FMUL	V24.2D, V28.2D, V25.D[0]

      (3204) 0x4ef6d4 FMLA	V24.2D, V26.2D, V1.D[0]

      (3204) 0x4ef6d8 FMLA	V24.2D, V17.2D, V19.D[0]

      (3204) 0x4ef6dc STR	Q24, [X14, X4]

      (3204) 0x4ef6e0 LDP	D21, D23, [X1, #48]

      (3204) 0x4ef6e4 LDR	D18, [X1, #64]

      (3204) 0x4ef6e8 FMUL	V3.2D, V28.2D, V23.D[0]

      (3204) 0x4ef6ec FMLA	V3.2D, V26.2D, V21.D[0]

      (3204) 0x4ef6f0 FMLA	V3.2D, V17.2D, V18.D[0]

      (3204) 0x4ef6f4 STR	Q3, [X15, X4]

      (3204) 0x4ef6f8 LDR	Q16, [X14, X4]

      (3204) 0x4ef6fc LDR	Q27, [X13, X4]

      (3204) 0x4ef700 FMUL	V5.2D, V16.2D, V16.2D

      (3204) 0x4ef704 FMLA	V5.2D, V27.2D, V27.2D

      (3204) 0x4ef708 FMLA	V5.2D, V3.2D, V3.2D

      (3204) 0x4ef70c FSQRT	V6.2D, V5.2D

      (3204) 0x4ef710 STR	Q6, [X18, X4]

      (3204) 0x4ef714 ADD	X4, X4, #16

      (3204) 0x4ef718 CMP	X27, X4

      (3204) 0x4ef71c B.NE	4ef648

    (3202) 0x4ef720 AND	W30, W11, #1951

    (3202) 0x4ef724 TBZ	W11, #0, 4ef838

    (3202) 0x4ef728 LD1RD	{Z31.D}, P7/Z, [X1, #10]

    (3202) 0x4ef72c LD1RD	{Z7.D}, P7/Z, [X1, #9]

    (3202) 0x4ef730 LD1RD	{Z20.D}, P7/Z, [X1, #13]

    (3202) 0x4ef734 LD1RD	{Z4.D}, P7/Z, [X1, #12]

    (3202) 0x4ef738 SUB	W5, W11, W30

    (3202) 0x4ef73c DUP	Z13.D, Z13.D[0]

    (3202) 0x4ef740 WHILELO	P6.D, WZR, W5

    (3202) 0x4ef744 DUP	Z14.D, Z14.D[0]

    (3202) 0x4ef748 LD1D	{Z30.D}, P6/Z, [X16, X30,LSL #3]

    (3202) 0x4ef74c LD1D	{Z29.D}, P6/Z, [X9, X30,LSL #3]

    (3202) 0x4ef750 FSUB	Z22.D, Z30.D, Z13.D

    (3202) 0x4ef754 FSUB	Z28.D, Z29.D, Z14.D

    (3202) 0x4ef758 LD1D	{Z26.D}, P6/Z, [X17, X30,LSL #3]

    (3202) 0x4ef75c FMUL	Z2.D, Z31.D, Z22.D

    (3202) 0x4ef760 FMUL	Z0.D, Z20.D, Z22.D

    (3202) 0x4ef764 FMLA	Z2.D, P7/M, Z7.D, Z28.D

    (3202) 0x4ef768 FMLA	Z0.D, P7/M, Z4.D, Z28.D

    (3202) 0x4ef76c DUP	Z15.D, Z15.D[0]

    (3202) 0x4ef770 FSUB	Z1.D, Z26.D, Z15.D

    (3202) 0x4ef774 LD1RD	{Z24.D}, P7/Z, [X1, #14]

    (3202) 0x4ef778 LD1RD	{Z17.D}, P7/Z, [X1, #11]

    (3202) 0x4ef77c LD1RD	{Z25.D}, P7/Z, [X1, #16]

    (3202) 0x4ef780 LD1RD	{Z19.D}, P7/Z, [X1, #15]

    (3202) 0x4ef784 LD1RD	{Z23.D}, P7/Z, [X1, #17]

    (3202) 0x4ef788 LD1RD	{Z18.D}, P7/Z, [X1, #1]

    (3202) 0x4ef78c LD1RD	{Z13.D}, P7/Z, [X1]

    (3202) 0x4ef790 LD1RD	{Z31.D}, P7/Z, [X1, #4]

    (3202) 0x4ef794 LD1RD	{Z29.D}, P7/Z, [X1, #3]

    (3202) 0x4ef798 LD1RD	{Z26.D}, P7/Z, [X1, #5]

    (3202) 0x4ef79c LD1RD	{Z15.D}, P7/Z, [X1, #6]

    (3202) 0x4ef7a0 LD1RD	{Z20.D}, P7/Z, [X1, #8]

    (3202) 0x4ef7a4 FMAD	Z24.D, P7/M, Z1.D, Z0.D

    (3202) 0x4ef7a8 FMAD	Z17.D, P7/M, Z1.D, Z2.D

    (3202) 0x4ef7ac ADD	X11, X13, X30,LSL #3

    (3202) 0x4ef7b0 FMUL	Z21.D, Z25.D, Z22.D

    (3202) 0x4ef7b4 ADD	X7, X14, X30,LSL #3

    (3202) 0x4ef7b8 LD1RD	{Z22.D}, P7/Z, [X1, #2]

    (3202) 0x4ef7bc FMLA	Z21.D, P7/M, Z19.D, Z28.D

    (3202) 0x4ef7c0 MOVPRFX	Z3, Z24

    (3202) 0x4ef7c4 FRINTA	Z3.D, P7/M, Z24.D

    (3202) 0x4ef7c8 LD1RD	{Z28.D}, P7/Z, [X1, #7]

    (3202) 0x4ef7cc FMAD	Z23.D, P7/M, Z1.D, Z21.D

    (3202) 0x4ef7d0 FSUB	Z5.D, Z24.D, Z3.D

    (3202) 0x4ef7d4 MOVPRFX	Z16, Z17

    (3202) 0x4ef7d8 FRINTA	Z16.D, P7/M, Z17.D

    (3202) 0x4ef7dc FMUL	Z27.D, Z18.D, Z5.D

    (3202) 0x4ef7e0 FSUB	Z6.D, Z17.D, Z16.D

    (3202) 0x4ef7e4 MOVPRFX	Z14, Z23

    (3202) 0x4ef7e8 FRINTA	Z14.D, P7/M, Z23.D

    (3202) 0x4ef7ec FMLA	Z27.D, P7/M, Z13.D, Z6.D

    (3202) 0x4ef7f0 FSUB	Z30.D, Z23.D, Z14.D

    (3202) 0x4ef7f4 FMUL	Z2.D, Z31.D, Z5.D

    (3202) 0x4ef7f8 FMAD	Z22.D, P7/M, Z30.D, Z27.D

    (3202) 0x4ef7fc FMLA	Z2.D, P7/M, Z29.D, Z6.D

    (3202) 0x4ef800 FMUL	Z7.D, Z5.D, Z28.D

    (3202) 0x4ef804 FMLA	Z2.D, P7/M, Z26.D, Z30.D

    (3202) 0x4ef808 FMLA	Z7.D, P7/M, Z6.D, Z15.D

    (3202) 0x4ef80c FMLA	Z7.D, P7/M, Z30.D, Z20.D

    (3202) 0x4ef810 ST1D	{Z22.D}, P6, [X11, MUL VL]

    (3202) 0x4ef814 ST1D	{Z2.D}, P6, [X7, MUL VL]

    (3202) 0x4ef818 ST1D	{Z7.D}, P6, [X15, X30,LSL #3]

    (3202) 0x4ef81c LD1D	{Z4.D}, P6/Z, [X7, MUL VL]

    (3202) 0x4ef820 LD1D	{Z0.D}, P6/Z, [X11, MUL VL]

    (3202) 0x4ef824 FMUL	Z1.D, Z4.D, Z4.D

    (3202) 0x4ef828 FMLA	Z1.D, P7/M, Z0.D, Z0.D

    (3202) 0x4ef82c FMLA	Z1.D, P7/M, Z7.D, Z7.D

    (3202) 0x4ef830 FSQRT	Z1.D, P7/M, Z1.D

    (3202) 0x4ef834 ST1D	{Z1.D}, P6, [X18, X30,LSL #3]

    (3202) 0x4ef838 ADD	X20, X20, #1

    (3202) 0x4ef83c ADD	X22, X22, #24

    (3202) 0x4ef840 CMP	X20, X10

    (3202) 0x4ef844 B.CC	4ef5c0

(3203) 0x4ef848 LDR	D15, [SP, #88]

(3203) 0x4ef84c LDP	X25, X26, [SP, #64]

(3203) 0x4ef850 LDP	D13, D14, [SP, #96]

(3203) 0x4ef854 LDR	X27, [SP, #80]

(3203) 0x4ef858 ORR	X0, XZR, X19

(3203) 0x4ef85c BL	4beb20

(3203) 0x4ef860 LDP	X19, X20, [SP, #16]

(3203) 0x4ef864 LDP	X21, X22, [SP, #32]

(3203) 0x4ef868 LDP	X23, X24, [SP, #48]

(3203) 0x4ef86c LDP	X29, X30, [SP], #112

(3203) 0x4ef870 RET

  (3201) 0x4ef874 BLR	X2

  (3201) 0x4ef878 LDR	X10, [X21, #24]

  (3201) 0x4ef87c PTRUE	P7.B, ALL

  (3201) 0x4ef880 B	4ef5e0

    (3202) 0x4ef884 MOVZ	X30, #0

    (3202) 0x4ef888 ADD	X1, X21, #280

    (3202) 0x4ef88c PTRUE	P7.B, ALL

    (3202) 0x4ef890 B	4ef728

0x4ef894 ORR	X4, XZR, X0

0x4ef898 ORR	X0, XZR, X19

0x4ef89c ORR	X19, XZR, X4

0x4ef8a0 BL	4beb20

0x4ef8a4 ORR	X0, XZR, X19

0x4ef8a8 BL	404160

0x4ef8ac HINT	#0

0x4ef8b0 HINT	#0

0x4ef8b4 HINT	#0

0x4ef8b8 HINT	#0

0x4ef8bc HINT	#0

Coverage (%)	Name	Source Location	Module
►99.14+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	SoaDistanceTableAAOMPTarget.h:179-187
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1128-1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:223-224,234-255
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271-273
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:179-187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/RealSpacePositionsOMPTarget.h:163

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 66% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 4.00 to 3.50 cycles (1.14x speedup).

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
12% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.50 cycles (2.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	35
loop length	140
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	3.33	3.33	3.33	3.33	3.33	3.33	1.00	1.00	0.00	0.00	4.00	4.00	2.00	3.00	3.00
cycles	2.00	2.00	3.33	3.33	3.33	3.33	3.33	3.33	1.00	1.00	0.00	0.00	4.00	4.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Overall L1	4.00

Vectorization ratios

all	5%
load	0%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
58% of peak store performance is reached (28.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ef560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [X0, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4ef858 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X24, <2004bb594>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X22, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
PTRUE P7.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ADD X24, X24, #2816	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X23, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W25, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X4, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4beb20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404160 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	SoaDistanceTableAAOMPTarget.h:179-187
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1128-1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:223-224,234-255
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:271-273
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableAAOMPTarget.h:179-187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/RealSpacePositionsOMPTarget.h:163

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

5% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
12% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.50 cycles (2.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 112 bytes.

General properties

nb instructions	35
loop length	140
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	3.33	3.33	3.33	3.33	3.33	3.33	1.00	1.00	0.00	0.00	4.00	4.00	2.00	3.00	3.00
cycles	2.00	2.00	3.33	3.33	3.33	3.33	3.33	3.33	1.00	1.00	0.00	0.00	4.00	4.00	2.00	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.75
Overall L1	4.00

Vectorization ratios

all	5%
load	0%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

4% of peak load performance is reached (4.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
58% of peak store performance is reached (28.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4ef560

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #912]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X19, [X0, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X10, [X21, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP X10, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.LS 4ef858 <_ZN11qmcplusplus27SoaDistanceTableAAOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x2f8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X24, <2004bb594>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
MOVZ X22, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
PTRUE P7.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
ADD X24, X24, #2816	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X26, X23, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W25, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D13, D14, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X4, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 4beb20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404160 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::SoaDistanceTableAAOMPTarget::evaluate(qmcplusplus::ParticleSet&)–	0.08	0.12
▼Loop 3203 - SoaDistanceTableAAOMPTarget.h:184-187 - exec–	0.00	0.00
▼Loop 3201 - VectorSoAContainer.h:271-273 - exec–	0.00	0.00
▼Loop 3202 - SoaDistanceTableAAOMPTarget.h:184-185 - exec–	0.00	0.00
○Loop 3204 - ParticleBConds3DSoa.h:237-255 - exec	0.08	0.11

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code