OV - exec - Function qmcplusplus::TimerType<std::chrono::_V2::system

	Function: qmcplusplus::TimerType<std::chrono::_V2::system_clock>::stop()	Module: exec	Source: NewTimer.cpp:84-120 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h: 151 - 172

--------------------------------------------------------------------------------

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 124

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

120:       {

121:         return this->long_buckets[j] < rhs.long_buckets[j];

122:       }

123:     }

124:     return this->long_buckets[N - 1] < rhs.long_buckets[N - 1];

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/tuple: 2887 - 2888

--------------------------------------------------------------------------------

2887:       : first(std::forward<_Args1>(std::get<_Indexes1>(__tuple1))...),

2888: 	second(std::forward<_Args2>(std::get<_Indexes2>(__tuple2))...)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 84 - 120

--------------------------------------------------------------------------------

84: void TimerType<CLOCK>::stop()

85: {

86:   if (active)

[...]

98:     bool is_true_master(true);

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       std::chrono::duration<double> elapsed = CLOCK::now() - start_time;

105:       total_time += elapsed.count();

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed.count();

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_tree.h: 269 - 2459

--------------------------------------------------------------------------------

269:       _Rb_tree_iterator(_Base_ptr __x) _GLIBCXX_NOEXCEPT

[...]

283: 	_M_node = _Rb_tree_increment(_M_node);

[...]

298: 	_M_node = _Rb_tree_decrement(_M_node);

299: 	return *this;

[...]

631:       }

[...]

733:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

748:       { return &this->_M_impl._M_header; }

[...]

778:       { return static_cast<_Link_type>(__x->_M_left); }

[...]

786:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1636: 	~_Auto_node()

[...]

1947:       while (__x != 0)

1948: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

1949: 	  __y = __x, __x = _S_left(__x);

[...]

2109:       _Base_ptr __y = _M_end();

2110:       bool __comp = true;

2111:       while (__x != 0)

2112: 	{

2113: 	  __y = __x;

2114: 	  __comp = _M_impl._M_key_compare(__k, _S_key(__x));

2115: 	  __x = __comp ? _S_left(__x) : _S_right(__x);

2116: 	}

2117:       iterator __j = iterator(__y);

2118:       if (__comp)

2119: 	{

2120: 	  if (__j == begin())

2121: 	    return _Res(__x, __y);

2122: 	  else

2123: 	    --__j;

2124: 	}

2125:       if (_M_impl._M_key_compare(_S_key(__j._M_node), __k))

[...]

2217: 	      && _M_impl._M_key_compare(_S_key(_M_rightmost()), __k))

2218: 	    return _Res(0, _M_rightmost());

2219: 	  else

2220: 	    return _M_get_insert_unique_pos(__k);

2221: 	}

2222:       else if (_M_impl._M_key_compare(__k, _S_key(__pos._M_node)))

2223: 	{

2224: 	  // First, try before...

2225: 	  iterator __before = __pos;

2226: 	  if (__pos._M_node == _M_leftmost()) // begin()

2227: 	    return _Res(_M_leftmost(), _M_leftmost());

2228: 	  else if (_M_impl._M_key_compare(_S_key((--__before)._M_node), __k))

2229: 	    {

2230: 	      if (_S_right(__before._M_node) == 0)

[...]

2242: 	  if (__pos._M_node == _M_rightmost())

2243: 	    return _Res(0, _M_rightmost());

2244: 	  else if (_M_impl._M_key_compare(__k, _S_key((++__after)._M_node)))

2245: 	    {

2246: 	      if (_S_right(__pos._M_node) == 0)

[...]

2373:     _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::

2374:     _M_insert_node(_Base_ptr __x, _Base_ptr __p, _Link_type __z)

2375:     -> iterator

2376:     {

2377:       bool __insert_left = (__x != 0 || __p == _M_end()

2378: 			    || _M_impl._M_key_compare(_S_key(__z),

2379: 						      _S_key(__p)));

2380:

2381:       _Rb_tree_insert_and_rebalance(__insert_left, __z, __p,

2382: 				    this->_M_impl._M_header);

2383:       ++_M_impl._M_node_count;

[...]

2459: 	auto __res = _M_get_insert_hint_unique_pos(__pos, __z._M_key());

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_map.h: 511 - 511

--------------------------------------------------------------------------------

511: 	if (__i == end() || key_comp()(__k, (*__i).first))

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/chrono.h: 214 - 716

--------------------------------------------------------------------------------

214: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

716: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

0x4beb20 STP	X29, X30, [SP, #928]!

0x4beb24 ADD	X29, SP, #0

0x4beb28 STP	X21, X22, [SP, #32]

0x4beb2c LDRB	W21, [X0, #56]

0x4beb30 TBNZ	W21, #0, 4beb40

(2410) 0x4beb34 LDP	X21, X22, [SP, #32]

(2410) 0x4beb38 LDP	X29, X30, [SP], #96

(2410) 0x4beb3c RET

(2410) 0x4beb40 STP	X19, X20, [SP, #16]

(2410) 0x4beb44 ORR	W20, WZR, W21

(2410) 0x4beb48 STP	X23, X24, [SP, #48]

(2410) 0x4beb4c ORR	X23, XZR, X0

(2410) 0x4beb50 BL	4043f0

(2410) 0x4beb54 ORR	W19, WZR, W0

(2410) 0x4beb58 CMP	W0, #0

(2410) 0x4beb5c B.LE	4bed0c

(2410) 0x4beb60 ANDS	W1, W0, #128

(2410) 0x4beb64 SUB	W22, W0, #1

(2410) 0x4beb68 B.EQ	4bec30

(2410) 0x4beb6c CMP	W1, #1

(2410) 0x4beb70 B.EQ	4bec14

(2410) 0x4beb74 CMP	W1, #2

(2410) 0x4beb78 B.EQ	4bebfc

(2410) 0x4beb7c CMP	W1, #3

(2410) 0x4beb80 B.EQ	4bebe4

(2410) 0x4beb84 CMP	W1, #4

(2410) 0x4beb88 B.EQ	4bebcc

(2410) 0x4beb8c CMP	W1, #5

(2410) 0x4beb90 B.EQ	4bebb4

(2410) 0x4beb94 CMP	W1, #6

(2410) 0x4beb98 B.NE	4beea0

(2410) 0x4beb9c ORR	W0, WZR, W19

(2410) 0x4beba0 SUB	W19, W19, #1

(2410) 0x4beba4 BL	404130

(2410) 0x4beba8 CMP	W0, #0

(2410) 0x4bebac CCMP	W20, #0, #4, #0

(2410) 0x4bebb0 CSINC	W20, WZR, WZR, #0

(2410) 0x4bebb4 ORR	W0, WZR, W19

(2410) 0x4bebb8 SUB	W19, W19, #1

(2410) 0x4bebbc BL	404130

(2410) 0x4bebc0 CMP	W0, #0

(2410) 0x4bebc4 CCMP	W20, #0, #4, #0

(2410) 0x4bebc8 CSINC	W20, WZR, WZR, #0

(2410) 0x4bebcc ORR	W0, WZR, W19

(2410) 0x4bebd0 SUB	W19, W19, #1

(2410) 0x4bebd4 BL	404130

(2410) 0x4bebd8 CMP	W0, #0

(2410) 0x4bebdc CCMP	W20, #0, #4, #0

(2410) 0x4bebe0 CSINC	W20, WZR, WZR, #0

(2410) 0x4bebe4 ORR	W0, WZR, W19

(2410) 0x4bebe8 SUB	W19, W19, #1

(2410) 0x4bebec BL	404130

(2410) 0x4bebf0 CMP	W0, #0

(2410) 0x4bebf4 CCMP	W20, #0, #4, #0

(2410) 0x4bebf8 CSINC	W20, WZR, WZR, #0

(2410) 0x4bebfc ORR	W0, WZR, W19

(2410) 0x4bec00 SUB	W19, W19, #1

(2410) 0x4bec04 BL	404130

(2410) 0x4bec08 CMP	W0, #0

(2410) 0x4bec0c CCMP	W20, #0, #4, #0

(2410) 0x4bec10 CSINC	W20, WZR, WZR, #0

(2410) 0x4bec14 ORR	W0, WZR, W19

(2410) 0x4bec18 BL	404130

(2410) 0x4bec1c CMP	W0, #0

(2410) 0x4bec20 CCMP	W20, #0, #4, #0

(2410) 0x4bec24 CSINC	W20, WZR, WZR, #0

(2410) 0x4bec28 SUBS	W19, W19, #1

(2410) 0x4bec2c B.EQ	4becf4

  (2419) 0x4bec30 ORR	W0, WZR, W19

  (2419) 0x4bec34 SUB	W24, W19, #1

  (2419) 0x4bec38 BL	404130

  (2419) 0x4bec3c CMP	W0, #0

  (2419) 0x4bec40 ORR	W0, WZR, W24

  (2419) 0x4bec44 CCMP	W20, #0, #4, #0

  (2419) 0x4bec48 CSINC	W22, WZR, WZR, #0

  (2419) 0x4bec4c BL	404130

  (2419) 0x4bec50 ORR	W2, WZR, W0

  (2419) 0x4bec54 SUB	W0, W24, #1

  (2419) 0x4bec58 CMP	W2, #0

  (2419) 0x4bec5c CCMP	W22, #0, #4, #0

  (2419) 0x4bec60 CSINC	W20, WZR, WZR, #0

  (2419) 0x4bec64 BL	404130

  (2419) 0x4bec68 ORR	W3, WZR, W0

  (2419) 0x4bec6c SUB	W0, W19, #3

  (2419) 0x4bec70 CMP	W3, #0

  (2419) 0x4bec74 CCMP	W20, #0, #4, #0

  (2419) 0x4bec78 CSINC	W24, WZR, WZR, #0

  (2419) 0x4bec7c BL	404130

  (2419) 0x4bec80 ORR	W4, WZR, W0

  (2419) 0x4bec84 SUB	W0, W19, #4

  (2419) 0x4bec88 CMP	W4, #0

  (2419) 0x4bec8c CCMP	W24, #0, #4, #0

  (2419) 0x4bec90 CSINC	W22, WZR, WZR, #0

  (2419) 0x4bec94 BL	404130

  (2419) 0x4bec98 ORR	W5, WZR, W0

  (2419) 0x4bec9c SUB	W0, W19, #5

  (2419) 0x4beca0 CMP	W5, #0

  (2419) 0x4beca4 CCMP	W22, #0, #4, #0

  (2419) 0x4beca8 CSINC	W20, WZR, WZR, #0

  (2419) 0x4becac BL	404130

  (2419) 0x4becb0 ORR	W6, WZR, W0

  (2419) 0x4becb4 SUB	W0, W19, #6

  (2419) 0x4becb8 CMP	W6, #0

  (2419) 0x4becbc CCMP	W20, #0, #4, #0

  (2419) 0x4becc0 CSINC	W24, WZR, WZR, #0

  (2419) 0x4becc4 BL	404130

  (2419) 0x4becc8 ORR	W7, WZR, W0

  (2419) 0x4beccc SUB	W0, W19, #7

  (2419) 0x4becd0 CMP	W7, #0

  (2419) 0x4becd4 CCMP	W24, #0, #4, #0

  (2419) 0x4becd8 CSINC	W22, WZR, WZR, #0

  (2419) 0x4becdc BL	404130

  (2419) 0x4bece0 CMP	W0, #0

  (2419) 0x4bece4 CCMP	W22, #0, #4, #0

  (2419) 0x4bece8 CSINC	W20, WZR, WZR, #0

  (2419) 0x4becec SUBS	W19, W19, #8

  (2419) 0x4becf0 B.NE	4bec30

(2410) 0x4becf4 TBNZ	W20, #0, 4bed0c

(2410) 0x4becf8 LDP	X19, X20, [SP, #16]

(2410) 0x4becfc LDP	X23, X24, [SP, #48]

(2410) 0x4bed00 LDP	X21, X22, [SP, #32]

(2410) 0x4bed04 LDP	X29, X30, [SP], #96

(2410) 0x4bed08 RET

(2410) 0x4bed0c STP	X25, X26, [SP, #64]

(2410) 0x4bed10 ADD	X24, X23, #104

(2410) 0x4bed14 ADD	X20, X23, #112

(2410) 0x4bed18 STR	D15, [SP, #88]

(2410) 0x4bed1c BL	4041a0

(2410) 0x4bed20 LDR	X9, [X23]

(2410) 0x4bed24 ADRP	X8,

(2410) 0x4bed28 LDR	D15, [X8, #3856]

(2410) 0x4bed2c LDR	D0, [X23, #8]

(2410) 0x4bed30 SUB	X0, X0, X9

(2410) 0x4bed34 LDR	X10, [X23, #16]

(2410) 0x4bed38 SCVTF	D1, X0

(2410) 0x4bed3c LDR	X14, [X24, #16]

(2410) 0x4bed40 ADD	X11, X10, #1

(2410) 0x4bed44 FMUL	D15, D1, D15

(2410) 0x4bed48 STR	X11, [X23, #16]

(2410) 0x4bed4c FADD	D2, D0, D15

(2410) 0x4bed50 STR	D2, [X23, #8]

(2410) 0x4bed54 CBZ	X14, 4bef50

(2410) 0x4bed58 LDR	X15, [X23, #80]

(2410) 0x4bed5c ORR	X19, XZR, X20

  (2416) 0x4bed60 LDR	X12, [X14, #32]

  (2416) 0x4bed64 CMP	X12, X15

  (2416) 0x4bed68 B.NE	4bee78

  (2416) 0x4bed6c LDR	X12, [X14, #40]

  (2416) 0x4bed70 LDR	X13, [X23, #88]

  (2416) 0x4bed74 CMP	X12, X13

  (2416) 0x4bed78 B.NE	4bee7c

  (2416) 0x4bed7c ORR	X19, XZR, X14

  (2416) 0x4bed80 LDR	X14, [X14, #16]

  (2416) 0x4bed84 CBNZ	X14, 4bed60

(2410) 0x4bed88 CMP	X20, X19

(2410) 0x4bed8c B.EQ	4bef50

(2410) 0x4bed90 LDR	X16, [X19, #32]

(2410) 0x4bed94 ADD	X25, X19, #32

(2410) 0x4bed98 CMP	X16, X15

(2410) 0x4bed9c B.NE	4bf090

(2410) 0x4beda0 LDR	X16, [X25, #8]

(2410) 0x4beda4 LDR	X15, [X23, #88]

(2410) 0x4beda8 CMP	X15, X16

(2410) 0x4bedac B.NE	4bf090

(2410) 0x4bedb0 LDR	D31, [X19, #56]

(2410) 0x4bedb4 ADD	X24, X23, #152

(2410) 0x4bedb8 ADD	X20, X23, #160

(2410) 0x4bedbc LDR	X3, [X24, #16]

(2410) 0x4bedc0 FADD	D3, D31, D15

(2410) 0x4bedc4 STR	D3, [X19, #56]

(2410) 0x4bedc8 CBZ	X3, 4beeb8

(2410) 0x4bedcc LDR	X4, [X23, #80]

(2410) 0x4bedd0 ORR	X19, XZR, X20

(2410) 0x4bedd4 HINT	#0

(2410) 0x4bedd8 HINT	#0

(2410) 0x4beddc HINT	#0

  (2412) 0x4bede0 LDR	X17, [X3, #32]

  (2412) 0x4bede4 CMP	X17, X4

  (2412) 0x4bede8 B.NE	4bee64

  (2412) 0x4bedec LDR	X17, [X3, #40]

  (2412) 0x4bedf0 LDR	X2, [X23, #88]

  (2412) 0x4bedf4 CMP	X17, X2

  (2412) 0x4bedf8 B.NE	4bee68

  (2412) 0x4bedfc ORR	X19, XZR, X3

  (2412) 0x4bee00 LDR	X3, [X3, #16]

  (2412) 0x4bee04 CBNZ	X3, 4bede0

(2410) 0x4bee08 CMP	X19, X20

(2410) 0x4bee0c B.EQ	4beeb8

(2410) 0x4bee10 LDR	X26, [X19, #32]

(2410) 0x4bee14 ADD	X25, X19, #32

(2410) 0x4bee18 CMP	X26, X4

(2410) 0x4bee1c B.NE	4bf200

(2410) 0x4bee20 LDR	X26, [X25, #8]

(2410) 0x4bee24 LDR	X4, [X23, #88]

(2410) 0x4bee28 CMP	X4, X26

(2410) 0x4bee2c B.NE	4bf200

(2410) 0x4bee30 LDR	X24, [X19, #56]

(2410) 0x4bee34 LDR	X0, [X23, #72]

(2410) 0x4bee38 ADD	X2, X24, #1

(2410) 0x4bee3c STR	X2, [X19, #56]

(2410) 0x4bee40 CBZ	X0, 4bee8c

0x4bee44 LDR	D15, [SP, #88]

0x4bee48 ORR	X1, XZR, X23

0x4bee4c LDP	X19, X20, [SP, #16]

0x4bee50 LDP	X23, X24, [SP, #48]

0x4bee54 LDP	X25, X26, [SP, #64]

0x4bee58 LDP	X21, X22, [SP, #32]

0x4bee5c LDP	X29, X30, [SP], #96

0x4bee60 B	4c4960

  (2412) 0x4bee64 ORR	X2, XZR, X4

  (2412) 0x4bee68 CMP	X17, X2

  (2412) 0x4bee6c B.GE	4bedfc

  (2412) 0x4bee70 LDR	X3, [X3, #24]

  (2412) 0x4bee74 B	4bee04

  (2416) 0x4bee78 ORR	X13, XZR, X15

  (2416) 0x4bee7c CMP	X12, X13

  (2416) 0x4bee80 B.GE	4bed7c

  (2416) 0x4bee84 LDR	X14, [X14, #24]

  (2416) 0x4bee88 B	4bed84

(2410) 0x4bee8c LDR	D15, [SP, #88]

(2410) 0x4bee90 LDP	X19, X20, [SP, #16]

(2410) 0x4bee94 LDP	X23, X24, [SP, #48]

(2410) 0x4bee98 LDP	X25, X26, [SP, #64]

(2410) 0x4bee9c B	4beb34

(2410) 0x4beea0 BL	404130

(2410) 0x4beea4 CMP	W0, #0

(2410) 0x4beea8 ORR	W19, WZR, W22

(2410) 0x4beeac CCMP	W21, #0, #4, #0

(2410) 0x4beeb0 CSINC	W20, WZR, WZR, #0

(2410) 0x4beeb4 B	4beb9c

(2410) 0x4beeb8 MOVZ	X0, #64

(2410) 0x4beebc STR	X27, [SP, #80]

(2410) 0x4beec0 BL	403db0

(2410) 0x4beec4 LDP	X10, X11, [X23, #80]

(2410) 0x4beec8 ADD	X25, X0, #32

(2410) 0x4beecc ORR	X27, XZR, X0

(2410) 0x4beed0 ORR	X26, XZR, X0

(2410) 0x4beed4 LDR	X9, [X23, #96]

(2410) 0x4beed8 STP	X10, X11, [X0, #32]

(2410) 0x4beedc LDR	X11, [X24, #40]

(2410) 0x4beee0 STP	X9, XZR, [X25, #16]

(2410) 0x4beee4 CBZ	X11, 4bef10

(2410) 0x4beee8 LDR	X2, [X23, #184]

(2410) 0x4beeec LDR	X12, [X27, #32]

(2410) 0x4beef0 LDR	X0, [X2, #32]

(2410) 0x4beef4 ADD	X30, X2, #32

(2410) 0x4beef8 CMP	X0, X12

(2410) 0x4beefc B.NE	4bf690

(2410) 0x4bef00 LDR	X13, [X30, #8]

(2410) 0x4bef04 LDR	X19, [X25, #8]

(2410) 0x4bef08 CMP	X13, X19

(2410) 0x4bef0c B.NE	4bf670

(2410) 0x4bef10 LDR	X19, [X24, #16]

(2410) 0x4bef14 CBZ	X19, 4bf5e4

(2410) 0x4bef18 LDR	X22, [X27, #32]

(2410) 0x4bef1c ORR	X5, XZR, X22

  (2411) 0x4bef20 LDR	X4, [X19, #32]

  (2411) 0x4bef24 CMP	X22, X4

  (2411) 0x4bef28 B.NE	4bf074

  (2411) 0x4bef2c LDR	X18, [X25, #8]

  (2411) 0x4bef30 LDR	X15, [X19, #40]

  (2411) 0x4bef34 CMP	X18, X15

  (2411) 0x4bef38 B.NE	4bf07c

  (2411) 0x4bef3c LDR	X1, [X19, #24]

  (2411) 0x4bef40 MOVZ	W16, #0

  (2411) 0x4bef44 CBZ	X1, 4beff0

  (2411) 0x4bef48 ORR	X19, XZR, X1

  (2411) 0x4bef4c B	4bef20

(2410) 0x4bef50 MOVZ	X0, #64

(2410) 0x4bef54 STR	X27, [SP, #80]

(2410) 0x4bef58 BL	403db0

(2410) 0x4bef5c LDP	X4, X5, [X23, #80]

(2410) 0x4bef60 ADD	X25, X0, #32

(2410) 0x4bef64 ORR	X26, XZR, X0

(2410) 0x4bef68 ORR	X27, XZR, X0

(2410) 0x4bef6c LDR	X6, [X24, #40]

(2410) 0x4bef70 STP	X4, X5, [X0, #32]

(2410) 0x4bef74 LDR	X5, [X23, #96]

(2410) 0x4bef78 STP	X5, XZR, [X25, #16]

(2410) 0x4bef7c CBZ	X6, 4befa8

(2410) 0x4bef80 LDR	X2, [X23, #136]

(2410) 0x4bef84 LDR	X8, [X26, #32]

(2410) 0x4bef88 LDR	X7, [X2, #32]

(2410) 0x4bef8c ADD	X30, X2, #32

(2410) 0x4bef90 CMP	X7, X8

(2410) 0x4bef94 B.NE	4bf6e8

(2410) 0x4bef98 LDR	X19, [X30, #8]

(2410) 0x4bef9c LDR	X9, [X25, #8]

(2410) 0x4befa0 CMP	X19, X9

(2410) 0x4befa4 B.NE	4bf6c8

(2410) 0x4befa8 LDR	X19, [X24, #16]

(2410) 0x4befac CBZ	X19, 4bf5cc

(2410) 0x4befb0 LDR	X22, [X26, #32]

(2410) 0x4befb4 ORR	X18, XZR, X22

(2410) 0x4befb8 HINT	#0

(2410) 0x4befbc HINT	#0

  (2415) 0x4befc0 LDR	X15, [X19, #32]

  (2415) 0x4befc4 CMP	X22, X15

  (2415) 0x4befc8 B.NE	4bf058

  (2415) 0x4befcc LDR	X0, [X25, #8]

  (2415) 0x4befd0 LDR	X11, [X19, #40]

  (2415) 0x4befd4 CMP	X0, X11

  (2415) 0x4befd8 B.NE	4bf060

  (2415) 0x4befdc LDR	X13, [X19, #24]

  (2415) 0x4befe0 MOVZ	W12, #0

  (2415) 0x4befe4 CBZ	X13, 4bf024

  (2415) 0x4befe8 ORR	X19, XZR, X13

  (2415) 0x4befec B	4befc0

(2410) 0x4beff0 ORR	X2, XZR, X19

(2410) 0x4beff4 TBNZ	W16, #0, 4bf474

(2410) 0x4beff8 CMP	X22, X4

(2410) 0x4beffc B.NE	4bf5ac

(2410) 0x4bf000 LDR	X5, [X25, #8]

(2410) 0x4bf004 LDR	X4, [X19, #40]

(2410) 0x4bf008 CMP	X4, X5

(2410) 0x4bf00c B.NE	4bf5ac

(2410) 0x4bf010 ORR	X0, XZR, X26

(2410) 0x4bf014 MOVZ	X1, #64

(2410) 0x4bf018 BL	403d90

(2410) 0x4bf01c LDR	X27, [SP, #80]

(2410) 0x4bf020 B	4bee30

(2410) 0x4bf024 ORR	X2, XZR, X19

(2410) 0x4bf028 TBNZ	W12, #0, 4bf49c

(2410) 0x4bf02c CMP	X22, X15

(2410) 0x4bf030 B.NE	4bf5bc

(2410) 0x4bf034 LDR	X18, [X25, #8]

(2410) 0x4bf038 LDR	X15, [X19, #40]

(2410) 0x4bf03c CMP	X15, X18

(2410) 0x4bf040 B.NE	4bf5bc

(2410) 0x4bf044 ORR	X0, XZR, X27

(2410) 0x4bf048 MOVZ	X1, #64

(2410) 0x4bf04c BL	403d90

(2410) 0x4bf050 LDR	X27, [SP, #80]

(2410) 0x4bf054 B	4bedb0

  (2415) 0x4bf058 ORR	X11, XZR, X15

  (2415) 0x4bf05c ORR	X0, XZR, X22

  (2415) 0x4bf060 CMP	X0, X11

  (2415) 0x4bf064 B.GE	4befdc

  (2415) 0x4bf068 LDR	X13, [X19, #16]

  (2415) 0x4bf06c ORR	W12, WZR, W21

  (2415) 0x4bf070 B	4befe4

  (2411) 0x4bf074 ORR	X15, XZR, X4

  (2411) 0x4bf078 ORR	X18, XZR, X22

  (2411) 0x4bf07c CMP	X18, X15

  (2411) 0x4bf080 B.GE	4bef3c

  (2411) 0x4bf084 LDR	X1, [X19, #16]

  (2411) 0x4bf088 ORR	W16, WZR, W21

  (2411) 0x4bf08c B	4bef44

(2410) 0x4bf090 STR	X27, [SP, #80]

(2410) 0x4bf094 CMP	X15, X16

(2410) 0x4bf098 B.GE	4bf050

(2410) 0x4bf09c MOVZ	X0, #64

(2410) 0x4bf0a0 BL	403db0

(2410) 0x4bf0a4 LDP	X22, X18, [X23, #80]

(2410) 0x4bf0a8 ADD	X26, X0, #32

(2410) 0x4bf0ac ORR	X27, XZR, X0

(2410) 0x4bf0b0 LDR	X1, [X23, #96]

(2410) 0x4bf0b4 STP	X22, X18, [X0, #32]

(2410) 0x4bf0b8 STP	X1, XZR, [X26, #16]

(2410) 0x4bf0bc LDR	X2, [X19, #32]

(2410) 0x4bf0c0 CMP	X22, X2

(2410) 0x4bf0c4 B.NE	4bf150

(2410) 0x4bf0c8 LDR	X17, [X25, #8]

(2410) 0x4bf0cc LDR	X30, [X26, #8]

(2410) 0x4bf0d0 CMP	X30, X17

(2410) 0x4bf0d4 B.LT	4bf154

(2410) 0x4bf0d8 B.EQ	4bf044

(2410) 0x4bf0dc LDR	X3, [X23, #136]

(2410) 0x4bf0e0 CMP	X3, X19

(2410) 0x4bf0e4 B.EQ	4bf4d0

(2410) 0x4bf0e8 ORR	X0, XZR, X19

(2410) 0x4bf0ec BL	404380

(2410) 0x4bf0f0 LDR	X5, [X0, #32]

(2410) 0x4bf0f4 ADD	X4, X0, #32

(2410) 0x4bf0f8 CMP	X5, X22

(2410) 0x4bf0fc B.NE	4bf77c

(2410) 0x4bf100 LDR	X6, [X4, #8]

(2410) 0x4bf104 LDR	X7, [X26, #8]

(2410) 0x4bf108 CMP	X7, X6

(2410) 0x4bf10c B.NE	4bf764

(2410) 0x4bf110 LDR	X19, [X24, #16]

(2410) 0x4bf114 CBZ	X19, 4bf794

(2410) 0x4bf118 HINT	#0

(2410) 0x4bf11c HINT	#0

  (2417) 0x4bf120 LDR	X13, [X19, #32]

  (2417) 0x4bf124 CMP	X13, X22

  (2417) 0x4bf128 B.NE	4bf550

  (2417) 0x4bf12c LDR	X10, [X26, #8]

  (2417) 0x4bf130 LDR	X9, [X19, #40]

  (2417) 0x4bf134 CMP	X10, X9

  (2417) 0x4bf138 B.NE	4bf558

  (2417) 0x4bf13c LDR	X0, [X19, #24]

  (2417) 0x4bf140 MOVZ	W11, #0

  (2417) 0x4bf144 CBZ	X0, 4bf4dc

  (2417) 0x4bf148 ORR	X19, XZR, X0

  (2417) 0x4bf14c B	4bf120

(2410) 0x4bf150 B.GE	4bf0dc

(2410) 0x4bf154 LDR	X25, [X23, #128]

(2410) 0x4bf158 CMP	X25, X19

(2410) 0x4bf15c B.EQ	4bf1d4

(2410) 0x4bf160 ORR	X0, XZR, X19

(2410) 0x4bf164 BL	403ff0

(2410) 0x4bf168 LDR	X15, [X0, #32]

(2410) 0x4bf16c ORR	X2, XZR, X0

(2410) 0x4bf170 CMP	X15, X22

(2410) 0x4bf174 B.NE	4bf1c0

(2410) 0x4bf178 LDR	X16, [X26, #8]

(2410) 0x4bf17c LDR	X15, [X0, #40]

(2410) 0x4bf180 CMP	X15, X16

(2410) 0x4bf184 B.NE	4bf1c4

(2410) 0x4bf188 LDR	X19, [X24, #16]

(2410) 0x4bf18c CBZ	X19, 4bf654

  (2418) 0x4bf190 LDR	X3, [X19, #32]

  (2418) 0x4bf194 CMP	X3, X22

  (2418) 0x4bf198 B.NE	4bf3f0

  (2418) 0x4bf19c LDR	X1, [X26, #8]

  (2418) 0x4bf1a0 LDR	X18, [X19, #40]

  (2418) 0x4bf1a4 CMP	X1, X18

  (2418) 0x4bf1a8 B.NE	4bf3f8

  (2418) 0x4bf1ac LDR	X2, [X19, #24]

  (2418) 0x4bf1b0 MOVZ	W17, #0

  (2418) 0x4bf1b4 CBZ	X2, 4bf40c

  (2418) 0x4bf1b8 ORR	X19, XZR, X2

  (2418) 0x4bf1bc B	4bf190

(2410) 0x4bf1c0 ORR	X16, XZR, X22

(2410) 0x4bf1c4 CMP	X15, X16

(2410) 0x4bf1c8 B.GE	4bf188

(2410) 0x4bf1cc LDR	X22, [X2, #24]

(2410) 0x4bf1d0 CBZ	X22, 4bf434

(2410) 0x4bf1d4 ORR	X2, XZR, X19

(2410) 0x4bf1d8 ORR	W0, WZR, W21

(2410) 0x4bf1dc ORR	X19, XZR, X27

(2410) 0x4bf1e0 ORR	X3, XZR, X20

(2410) 0x4bf1e4 ORR	X1, XZR, X19

(2410) 0x4bf1e8 BL	404410

(2410) 0x4bf1ec LDR	X20, [X24, #40]

(2410) 0x4bf1f0 LDR	X27, [SP, #80]

(2410) 0x4bf1f4 ADD	X1, X20, #1

(2410) 0x4bf1f8 STR	X1, [X24, #40]

(2410) 0x4bf1fc B	4bedb0

(2410) 0x4bf200 STR	X27, [SP, #80]

(2410) 0x4bf204 CMP	X4, X26

(2410) 0x4bf208 B.GE	4bf01c

(2410) 0x4bf20c MOVZ	X0, #64

(2410) 0x4bf210 BL	403db0

(2410) 0x4bf214 LDP	X22, X5, [X23, #80]

(2410) 0x4bf218 ADD	X27, X0, #32

(2410) 0x4bf21c ORR	X26, XZR, X0

(2410) 0x4bf220 LDR	X6, [X23, #96]

(2410) 0x4bf224 STP	X22, X5, [X0, #32]

(2410) 0x4bf228 STP	X6, XZR, [X27, #16]

(2410) 0x4bf22c LDR	X7, [X19, #32]

(2410) 0x4bf230 CMP	X22, X7

(2410) 0x4bf234 B.NE	4bf2bc

(2410) 0x4bf238 LDR	X30, [X25, #8]

(2410) 0x4bf23c LDR	X8, [X27, #8]

(2410) 0x4bf240 CMP	X8, X30

(2410) 0x4bf244 B.LT	4bf2c0

(2410) 0x4bf248 B.EQ	4bf010

(2410) 0x4bf24c LDR	X9, [X23, #184]

(2410) 0x4bf250 CMP	X19, X9

(2410) 0x4bf254 B.EQ	4bf4c4

(2410) 0x4bf258 ORR	X0, XZR, X19

(2410) 0x4bf25c BL	404380

(2410) 0x4bf260 LDR	X11, [X0, #32]

(2410) 0x4bf264 ORR	X6, XZR, X0

(2410) 0x4bf268 ADD	X10, X0, #32

(2410) 0x4bf26c CMP	X11, X22

(2410) 0x4bf270 B.NE	4bf720

(2410) 0x4bf274 LDR	X0, [X10, #8]

(2410) 0x4bf278 LDR	X12, [X27, #8]

(2410) 0x4bf27c CMP	X12, X0

(2410) 0x4bf280 B.NE	4bf74c

(2410) 0x4bf284 LDR	X19, [X24, #16]

(2410) 0x4bf288 CBZ	X19, 4bf738

  (2413) 0x4bf28c LDR	X3, [X19, #32]

  (2413) 0x4bf290 CMP	X3, X22

  (2413) 0x4bf294 B.NE	4bf534

  (2413) 0x4bf298 LDR	X15, [X27, #8]

  (2413) 0x4bf29c LDR	X14, [X19, #40]

  (2413) 0x4bf2a0 CMP	X15, X14

  (2413) 0x4bf2a4 B.NE	4bf53c

  (2413) 0x4bf2a8 LDR	X16, [X19, #24]

  (2413) 0x4bf2ac MOVZ	W18, #0

  (2413) 0x4bf2b0 CBZ	X16, 4bf508

  (2413) 0x4bf2b4 ORR	X19, XZR, X16

  (2413) 0x4bf2b8 B	4bf28c

(2410) 0x4bf2bc B.GE	4bf24c

(2410) 0x4bf2c0 LDR	X25, [X23, #176]

(2410) 0x4bf2c4 CMP	X19, X25

(2410) 0x4bf2c8 B.EQ	4bf344

(2410) 0x4bf2cc ORR	X0, XZR, X19

(2410) 0x4bf2d0 BL	403ff0

(2410) 0x4bf2d4 LDR	X4, [X0, #32]

(2410) 0x4bf2d8 ORR	X2, XZR, X0

(2410) 0x4bf2dc CMP	X4, X22

(2410) 0x4bf2e0 B.NE	4bf330

(2410) 0x4bf2e4 LDR	X17, [X27, #8]

(2410) 0x4bf2e8 LDR	X4, [X0, #40]

(2410) 0x4bf2ec CMP	X4, X17

(2410) 0x4bf2f0 B.NE	4bf334

(2410) 0x4bf2f4 LDR	X19, [X24, #16]

(2410) 0x4bf2f8 CBZ	X19, 4bf644

(2410) 0x4bf2fc HINT	#0

  (2414) 0x4bf300 LDR	X8, [X19, #32]

  (2414) 0x4bf304 CMP	X8, X22

  (2414) 0x4bf308 B.NE	4bf370

  (2414) 0x4bf30c LDR	X5, [X27, #8]

  (2414) 0x4bf310 LDR	X2, [X19, #40]

  (2414) 0x4bf314 CMP	X5, X2

  (2414) 0x4bf318 B.NE	4bf378

  (2414) 0x4bf31c LDR	X7, [X19, #24]

  (2414) 0x4bf320 MOVZ	W6, #0

  (2414) 0x4bf324 CBZ	X7, 4bf38c

  (2414) 0x4bf328 ORR	X19, XZR, X7

  (2414) 0x4bf32c B	4bf300

(2410) 0x4bf330 ORR	X17, XZR, X22

(2410) 0x4bf334 CMP	X4, X17

(2410) 0x4bf338 B.GE	4bf2f4

(2410) 0x4bf33c LDR	X22, [X2, #24]

(2410) 0x4bf340 CBZ	X22, 4bf3b4

(2410) 0x4bf344 ORR	X2, XZR, X19

(2410) 0x4bf348 ORR	X19, XZR, X26

(2410) 0x4bf34c ORR	X3, XZR, X20

(2410) 0x4bf350 ORR	W0, WZR, W21

(2410) 0x4bf354 ORR	X1, XZR, X19

(2410) 0x4bf358 BL	404410

(2410) 0x4bf35c LDR	X20, [X24, #40]

(2410) 0x4bf360 LDR	X27, [SP, #80]

(2410) 0x4bf364 ADD	X21, X20, #1

(2410) 0x4bf368 STR	X21, [X24, #40]

(2410) 0x4bf36c B	4bee30

  (2414) 0x4bf370 ORR	X2, XZR, X8

  (2414) 0x4bf374 ORR	X5, XZR, X22

  (2414) 0x4bf378 CMP	X5, X2

  (2414) 0x4bf37c B.GE	4bf31c

  (2414) 0x4bf380 LDR	X7, [X19, #16]

  (2414) 0x4bf384 ORR	W6, WZR, W21

  (2414) 0x4bf388 B	4bf324

(2410) 0x4bf38c ORR	X2, XZR, X19

(2410) 0x4bf390 TBNZ	W6, #0, 4bf58c

(2410) 0x4bf394 CMP	X22, X8

(2410) 0x4bf398 B.NE	4bf3ac

(2410) 0x4bf39c LDR	X22, [X27, #8]

(2410) 0x4bf3a0 LDR	X8, [X19, #40]

(2410) 0x4bf3a4 CMP	X8, X22

(2410) 0x4bf3a8 B.EQ	4bf010

(2410) 0x4bf3ac CMP	X8, X22

(2410) 0x4bf3b0 B.GE	4bf010

(2410) 0x4bf3b4 ORR	X19, XZR, X26

(2410) 0x4bf3b8 CMP	X20, X2

(2410) 0x4bf3bc B.EQ	4bf34c

(2410) 0x4bf3c0 LDR	X17, [X2, #32]

(2410) 0x4bf3c4 LDR	X7, [X19, #32]

(2410) 0x4bf3c8 CMP	X17, X7

(2410) 0x4bf3cc B.NE	4bf3e4

(2410) 0x4bf3d0 LDR	X17, [X2, #40]

(2410) 0x4bf3d4 MOVZ	W21, #0

(2410) 0x4bf3d8 LDR	X7, [X19, #40]

(2410) 0x4bf3dc CMP	X17, X7

(2410) 0x4bf3e0 B.EQ	4bf34c

(2410) 0x4bf3e4 CMP	X7, X17

(2410) 0x4bf3e8 CSINC	W21, WZR, WZR, #10

(2410) 0x4bf3ec B	4bf34c

  (2418) 0x4bf3f0 ORR	X18, XZR, X3

  (2418) 0x4bf3f4 ORR	X1, XZR, X22

  (2418) 0x4bf3f8 CMP	X1, X18

  (2418) 0x4bf3fc B.GE	4bf1ac

  (2418) 0x4bf400 LDR	X2, [X19, #16]

  (2418) 0x4bf404 ORR	W17, WZR, W21

  (2418) 0x4bf408 B	4bf1b4

(2410) 0x4bf40c ORR	X2, XZR, X19

(2410) 0x4bf410 TBNZ	W17, #0, 4bf56c

(2410) 0x4bf414 CMP	X22, X3

(2410) 0x4bf418 B.NE	4bf42c

(2410) 0x4bf41c LDR	X22, [X26, #8]

(2410) 0x4bf420 LDR	X3, [X19, #40]

(2410) 0x4bf424 CMP	X3, X22

(2410) 0x4bf428 B.EQ	4bf044

(2410) 0x4bf42c CMP	X3, X22

(2410) 0x4bf430 B.GE	4bf044

(2410) 0x4bf434 ORR	X19, XZR, X27

(2410) 0x4bf438 ORR	W0, WZR, W21

(2410) 0x4bf43c CMP	X20, X2

(2410) 0x4bf440 B.EQ	4bf1e0

(2410) 0x4bf444 LDR	X27, [X2, #32]

(2410) 0x4bf448 LDR	X16, [X19, #32]

(2410) 0x4bf44c CMP	X16, X27

(2410) 0x4bf450 B.NE	4bf468

(2410) 0x4bf454 LDR	X27, [X2, #40]

(2410) 0x4bf458 MOVZ	W0, #0

(2410) 0x4bf45c LDR	X16, [X19, #40]

(2410) 0x4bf460 CMP	X16, X27

(2410) 0x4bf464 B.EQ	4bf1e0

(2410) 0x4bf468 CMP	X16, X27

(2410) 0x4bf46c CSINC	W0, WZR, WZR, #10

(2410) 0x4bf470 B	4bf1e0

(2410) 0x4bf474 LDR	X3, [X24, #24]

(2410) 0x4bf478 CMP	X19, X3

(2410) 0x4bf47c B.EQ	4bf5b4

(2410) 0x4bf480 ORR	X0, XZR, X19

(2410) 0x4bf484 BL	403ff0

(2410) 0x4bf488 LDR	X4, [X0, #32]

(2410) 0x4bf48c ORR	X2, XZR, X19

(2410) 0x4bf490 ORR	X5, XZR, X22

(2410) 0x4bf494 ORR	X19, XZR, X0

(2410) 0x4bf498 B	4beff8

(2410) 0x4bf49c LDR	X14, [X24, #24]

(2410) 0x4bf4a0 CMP	X14, X19

(2410) 0x4bf4a4 B.EQ	4bf5c4

(2410) 0x4bf4a8 ORR	X0, XZR, X19

(2410) 0x4bf4ac BL	403ff0

(2410) 0x4bf4b0 LDR	X15, [X0, #32]

(2410) 0x4bf4b4 ORR	X2, XZR, X19

(2410) 0x4bf4b8 ORR	X18, XZR, X22

(2410) 0x4bf4bc ORR	X19, XZR, X0

(2410) 0x4bf4c0 B	4bf02c

(2410) 0x4bf4c4 ORR	X2, XZR, X19

(2410) 0x4bf4c8 ORR	X19, XZR, X26

(2410) 0x4bf4cc B	4bf3c0

(2410) 0x4bf4d0 ORR	X2, XZR, X19

(2410) 0x4bf4d4 ORR	X19, XZR, X27

(2410) 0x4bf4d8 B	4bf444

(2410) 0x4bf4dc ORR	X2, XZR, X19

(2410) 0x4bf4e0 TBNZ	W11, #0, 4bf5fc

(2410) 0x4bf4e4 CMP	X22, X13

(2410) 0x4bf4e8 B.NE	4bf4fc

(2410) 0x4bf4ec LDR	X22, [X26, #8]

(2410) 0x4bf4f0 LDR	X13, [X19, #40]

(2410) 0x4bf4f4 CMP	X13, X22

(2410) 0x4bf4f8 B.EQ	4bf044

(2410) 0x4bf4fc CMP	X13, X22

(2410) 0x4bf500 B.LT	4bf434

(2410) 0x4bf504 B	4bf044

(2410) 0x4bf508 ORR	X2, XZR, X19

(2410) 0x4bf50c TBNZ	W18, #0, 4bf620

(2410) 0x4bf510 CMP	X22, X3

(2410) 0x4bf514 B.NE	4bf528

(2410) 0x4bf518 LDR	X22, [X27, #8]

(2410) 0x4bf51c LDR	X3, [X19, #40]

(2410) 0x4bf520 CMP	X3, X22

(2410) 0x4bf524 B.EQ	4bf010

(2410) 0x4bf528 CMP	X3, X22

(2410) 0x4bf52c B.LT	4bf3b4

(2410) 0x4bf530 B	4bf010

  (2413) 0x4bf534 ORR	X14, XZR, X3

  (2413) 0x4bf538 ORR	X15, XZR, X22

  (2413) 0x4bf53c CMP	X15, X14

  (2413) 0x4bf540 B.GE	4bf2a8

  (2413) 0x4bf544 LDR	X16, [X19, #16]

  (2413) 0x4bf548 ORR	W18, WZR, W21

  (2413) 0x4bf54c B	4bf2b0

  (2417) 0x4bf550 ORR	X9, XZR, X13

  (2417) 0x4bf554 ORR	X10, XZR, X22

  (2417) 0x4bf558 CMP	X10, X9

  (2417) 0x4bf55c B.GE	4bf13c

  (2417) 0x4bf560 LDR	X0, [X19, #16]

  (2417) 0x4bf564 ORR	W11, WZR, W21

  (2417) 0x4bf568 B	4bf144

(2410) 0x4bf56c CMP	X25, X19

(2410) 0x4bf570 B.EQ	4bf434

(2410) 0x4bf574 ORR	X0, XZR, X19

(2410) 0x4bf578 BL	403ff0

(2410) 0x4bf57c LDR	X3, [X0, #32]

(2410) 0x4bf580 ORR	X2, XZR, X19

(2410) 0x4bf584 ORR	X19, XZR, X0

(2410) 0x4bf588 B	4bf414

(2410) 0x4bf58c CMP	X19, X25

(2410) 0x4bf590 B.EQ	4bf3b4

(2410) 0x4bf594 ORR	X0, XZR, X19

(2410) 0x4bf598 BL	403ff0

(2410) 0x4bf59c LDR	X8, [X0, #32]

(2410) 0x4bf5a0 ORR	X2, XZR, X19

(2410) 0x4bf5a4 ORR	X19, XZR, X0

(2410) 0x4bf5a8 B	4bf394

(2410) 0x4bf5ac CMP	X4, X5

(2410) 0x4bf5b0 B.GE	4bf010

(2410) 0x4bf5b4 ORR	X19, XZR, X27

(2410) 0x4bf5b8 B	4bf3b8

(2410) 0x4bf5bc CMP	X15, X18

(2410) 0x4bf5c0 B.GE	4bf044

(2410) 0x4bf5c4 ORR	X19, XZR, X26

(2410) 0x4bf5c8 B	4bf438

(2410) 0x4bf5cc LDR	X10, [X24, #24]

(2410) 0x4bf5d0 CMP	X20, X10

(2410) 0x4bf5d4 B.EQ	4bf6b8

(2410) 0x4bf5d8 LDR	X22, [X26, #32]

(2410) 0x4bf5dc ORR	X19, XZR, X20

(2410) 0x4bf5e0 B	4bf4a8

(2410) 0x4bf5e4 LDR	X14, [X24, #24]

(2410) 0x4bf5e8 CMP	X20, X14

(2410) 0x4bf5ec B.EQ	4bf664

(2410) 0x4bf5f0 LDR	X22, [X27, #32]

(2410) 0x4bf5f4 ORR	X19, XZR, X20

(2410) 0x4bf5f8 B	4bf480

(2410) 0x4bf5fc LDR	X12, [X24, #24]

(2410) 0x4bf600 CMP	X12, X19

(2410) 0x4bf604 B.EQ	4bf434

(2410) 0x4bf608 ORR	X0, XZR, X19

(2410) 0x4bf60c BL	403ff0

(2410) 0x4bf610 LDR	X13, [X0, #32]

(2410) 0x4bf614 ORR	X2, XZR, X19

(2410) 0x4bf618 ORR	X19, XZR, X0

(2410) 0x4bf61c B	4bf4e4

(2410) 0x4bf620 LDR	X1, [X24, #24]

(2410) 0x4bf624 CMP	X19, X1

(2410) 0x4bf628 B.EQ	4bf3b4

(2410) 0x4bf62c ORR	X0, XZR, X19

(2410) 0x4bf630 BL	403ff0

(2410) 0x4bf634 LDR	X3, [X0, #32]

(2410) 0x4bf638 ORR	X2, XZR, X19

(2410) 0x4bf63c ORR	X19, XZR, X0

(2410) 0x4bf640 B	4bf510

(2410) 0x4bf644 CMP	X20, X25

(2410) 0x4bf648 B.EQ	4bf7a8

(2410) 0x4bf64c ORR	X19, XZR, X20

(2410) 0x4bf650 B	4bf594

(2410) 0x4bf654 CMP	X20, X25

(2410) 0x4bf658 B.EQ	4bf710

(2410) 0x4bf65c ORR	X19, XZR, X20

(2410) 0x4bf660 B	4bf574

(2410) 0x4bf664 ORR	X19, XZR, X27

(2410) 0x4bf668 ORR	X2, XZR, X20

(2410) 0x4bf66c B	4bf34c

(2410) 0x4bf670 B.GE	4bef10

(2410) 0x4bf674 MOVZ	X6, #0

(2410) 0x4bf678 ORR	X19, XZR, X27

(2410) 0x4bf67c CMP	X6, #0

(2410) 0x4bf680 CCMP	X20, X2, #4, #0

(2410) 0x4bf684 CSINC	W21, WZR, WZR, #1

(2410) 0x4bf688 B.EQ	4bf34c

(2410) 0x4bf68c B	4bf3d0

(2410) 0x4bf690 B.GE	4bef10

(2410) 0x4bf694 MOVZ	X6, #0

(2410) 0x4bf698 ORR	X19, XZR, X27

(2410) 0x4bf69c CMP	X6, #0

(2410) 0x4bf6a0 CCMP	X20, X2, #4, #0

(2410) 0x4bf6a4 CSINC	W21, WZR, WZR, #1

(2410) 0x4bf6a8 B.EQ	4bf34c

(2410) 0x4bf6ac LDR	X17, [X2, #32]

(2410) 0x4bf6b0 LDR	X7, [X19, #32]

(2410) 0x4bf6b4 B	4bf3e4

(2410) 0x4bf6b8 ORR	X19, XZR, X26

(2410) 0x4bf6bc ORR	X2, XZR, X20

(2410) 0x4bf6c0 ORR	W0, WZR, W21

(2410) 0x4bf6c4 B	4bf1e0

(2410) 0x4bf6c8 B.GE	4befa8

(2410) 0x4bf6cc MOVZ	X0, #0

(2410) 0x4bf6d0 ORR	X19, XZR, X26

(2410) 0x4bf6d4 CMP	X0, #0

(2410) 0x4bf6d8 CCMP	X20, X2, #4, #0

(2410) 0x4bf6dc CSINC	W0, WZR, WZR, #1

(2410) 0x4bf6e0 B.EQ	4bf1e0

(2410) 0x4bf6e4 B	4bf454

(2410) 0x4bf6e8 B.GE	4befa8

(2410) 0x4bf6ec MOVZ	X0, #0

(2410) 0x4bf6f0 ORR	X19, XZR, X26

(2410) 0x4bf6f4 CMP	X0, #0

(2410) 0x4bf6f8 CCMP	X20, X2, #4, #0

(2410) 0x4bf6fc CSINC	W0, WZR, WZR, #1

(2410) 0x4bf700 B.EQ	4bf1e0

(2410) 0x4bf704 LDR	X27, [X2, #32]

(2410) 0x4bf708 LDR	X16, [X19, #32]

(2410) 0x4bf70c B	4bf468

(2410) 0x4bf710 ORR	X19, XZR, X27

(2410) 0x4bf714 ORR	X2, XZR, X20

(2410) 0x4bf718 ORR	W0, WZR, W21

(2410) 0x4bf71c B	4bf1e0

(2410) 0x4bf720 B.LE	4bf284

(2410) 0x4bf724 LDR	X21, [X19, #24]

(2410) 0x4bf728 CBZ	X21, 4bf4c4

(2410) 0x4bf72c ORR	X19, XZR, X26

(2410) 0x4bf730 ORR	X2, XZR, X0

(2410) 0x4bf734 B	4bf69c

(2410) 0x4bf738 LDR	X19, [X24, #24]

(2410) 0x4bf73c CMP	X20, X19

(2410) 0x4bf740 B.EQ	4bf7a8

(2410) 0x4bf744 ORR	X19, XZR, X20

(2410) 0x4bf748 B	4bf62c

(2410) 0x4bf74c B.GE	4bf284

(2410) 0x4bf750 LDR	X13, [X19, #24]

(2410) 0x4bf754 CBZ	X13, 4bf4c4

(2410) 0x4bf758 ORR	X19, XZR, X26

(2410) 0x4bf75c ORR	X2, XZR, X6

(2410) 0x4bf760 B	4bf67c

(2410) 0x4bf764 B.GE	4bf110

(2410) 0x4bf768 LDR	X8, [X19, #24]

(2410) 0x4bf76c CBZ	X8, 4bf4d0

(2410) 0x4bf770 ORR	X19, XZR, X27

(2410) 0x4bf774 ORR	X2, XZR, X0

(2410) 0x4bf778 B	4bf6d4

(2410) 0x4bf77c B.LE	4bf110

(2410) 0x4bf780 LDR	X14, [X19, #24]

(2410) 0x4bf784 CBZ	X14, 4bf4d0

(2410) 0x4bf788 ORR	X19, XZR, X27

(2410) 0x4bf78c ORR	X2, XZR, X0

(2410) 0x4bf790 B	4bf6f4

(2410) 0x4bf794 LDR	X19, [X24, #24]

(2410) 0x4bf798 CMP	X20, X19

(2410) 0x4bf79c B.EQ	4bf710

(2410) 0x4bf7a0 ORR	X19, XZR, X20

(2410) 0x4bf7a4 B	4bf608

(2410) 0x4bf7a8 ORR	X19, XZR, X26

(2410) 0x4bf7ac ORR	X2, XZR, X20

(2410) 0x4bf7b0 B	4bf34c

0x4bf7b4 HINT	#0

0x4bf7b8 HINT	#0

0x4bf7bc HINT	#0

Coverage (%)	Name	Source Location	Module
►9.36+	qmcplusplus::SoaDistanceTableA[...]	NewTimer.h:249	exec
○	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.02+	qmcplusplus::SoaDistanceTableA[...]	NewTimer.h:249	exec
○	qmcplusplus::ParticleSet::make[...]	ParticleSet.cpp:343	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.69+	miniqmcreference::einspline_sp[...]	NewTimer.h:249	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.69+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:101	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.69+	miniqmcreference::einspline_sp[...]	NewTimer.h:249	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.85+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.85+	main._omp_fn.1	miniqmc.cpp:452	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.18+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:101	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.18+	qmcplusplus::ParticleSet::make[...]	NewTimer.h:249	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.68+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.18+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	miniqmcreference::DiracDetermi[...]	SPOSet.h:86	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.01+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:233	exec
○	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.84+	qmcplusplus::ParticleSet::acce[...]	ParticleSet.cpp:395	exec
○	main._omp_fn.1	miniqmc.cpp:453	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.01+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:91	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:183	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.67+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:183	exec
○	miniqmcreference::DiracDetermi[...]	SPOSet.h:86	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.67+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:91	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:183	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.51+	qmcplusplus::ParticleSet::upda[...]	ParticleSet.cpp:245	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.34+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:138	exec
○	qmcplusplus::WaveFunction::acc[...]	WaveFunction.cpp:223	exec
○	main._omp_fn.1	miniqmc.cpp:451	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.17+	qmcplusplus::SoaDistanceTableA[...]	NewTimer.h:249	exec
○	qmcplusplus::ParticleSet::make[...]	ParticleSet.cpp:343	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.00+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:185	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	GOMP_parallel	libgomp.h:980	libgomp.so.1.0.0
○	main	miniqmc.cpp:411	exec
○	__libc_start_call_main		libc.so.6
○	__libc_start_main		libc.so.6
○	_start	miniqmc.cpp:529	exec
►1.00+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:118	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_4

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h:151,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-124
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/tuple:2887-2888
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_tree.h:269,283,298-299,631,733,748,778,786,1636,1947-1949,2109-2125,2217-2230,2242-2246,2373-2383,2459
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_map.h:511
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/chrono.h:214,716

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 0.67 cycles (4.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 78% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.00 to 2.67 cycles (1.13x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 89 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.63
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

30% of peak load performance is reached (29.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4beb20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDRB W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (6.3%)
TBNZ W21, #0, 4beb40 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4c4960 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_4

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h:151,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-124
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/tuple:2887-2888
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_tree.h:269,283,298-299,631,733,748,778,786,1636,1947-1949,2109-2125,2217-2230,2242-2246,2373-2383,2459
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_map.h:511
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/chrono.h:214,716

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.00 to 0.67 cycles (4.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 89 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.00	3.00	3.00	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.63
Overall L1	3.00

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.00 cycles. At this rate:

30% of peak load performance is reached (29.67 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
22% of peak store performance is reached (10.67 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4beb20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDRB W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (6.3%)
TBNZ W21, #0, 4beb40 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4c4960 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.02	0.03
▼Loop 2410 - stl_tree.h:269-2459 - exec–	0.00	0.01
○Loop 2416 - stl_tree.h:786-1949 - exec	0.00	0.22
○Loop 2412 - stl_tree.h:786-1949 - exec	0.00	0.10
○Loop 2418 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2419 - NewTimer.cpp:99-100 - exec	0.00	0.00
○Loop 2417 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2414 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2415 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2413 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2411 - stl_tree.h:778-2115 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code