OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector<double, 3u>&)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratioG ...	Module: exec	Source: DiracDeterminantRef.cpp:94-118 [...]	Coverage (incl. loops): 0.11% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 155

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 94 - 118

--------------------------------------------------------------------------------

94: typename DiracDeterminantRef<DU_TYPE>::ValueType DiracDeterminantRef<DU_TYPE>::ratioGrad(ParticleSet& P,

95:                                                                                          int iat,

96:                                                                                          GradType& grad_iat)

97: {

98:   SPOVGLTimer->start();

99:   Phi->evaluate(P, iat, psiV, dpsiV, d2psiV);

100:   SPOVGLTimer->stop();

101:   RatioTimer->start();

102:   const int WorkingIndex = iat - FirstIndex;

103:   UpdateMode             = ORB_PBYP_PARTIAL;

[...]

109:   if (invRow_id != WorkingIndex)

110:   {

111:     invRow_id = WorkingIndex;

112:     updateEng.getInvRow(psiM, WorkingIndex, invRow);

113:   }

114:   curRatio = simd::dot(invRow.data(), psiV.data(), invRow.size());

115:   grad_iat += ((RealType)1.0 / curRatio) * simd::dot(invRow.data(), dpsiV.data(), invRow.size());

116:   RatioTimer->stop();

117:   return curRatio;

118: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

92:   inline typename BinaryReturn<T1, T2, OpAddAssign>::Type_t operator()(const T1& a, const T2& b) const

93:   {

94:     (const_cast<T1&>(a) += b);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 413 - 453

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 98 - 113

--------------------------------------------------------------------------------

98:     if (delay_count == 0)

99:     {

100:       // Ainv is fresh, directly access Ainv

101:       std::copy_n(Ainv[rowchanged], invRow.size(), invRow.data());

102:       return;

103:     }

104:     const T cone(1);

105:     const T czero(0);

106:     const int norb     = Ainv.rows();

107:     const int lda_Binv = Binv.cols();

108:     // save Ainv[rowchanged] to invRow

109:     std::copy_n(Ainv[rowchanged], norb, invRow.data());

110:     // multiply V (NxK) Binv(KxK) U(KxN) invRow right to the left

111:     BLAS::gemv('T', norb, delay_count, cone, U.data(), norb, invRow.data(), 1, czero, p.data(), 1);

112:     BLAS::gemv('N', delay_count, delay_count, cone, Binv.data(), lda_Binv, p.data(), 1, czero, Binv[delay_count], 1);

113:     BLAS::gemv('N', norb, delay_count, -cone, V.data(), norb, Binv[delay_count], 1, cone, invRow.data(), 1);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 217

--------------------------------------------------------------------------------

77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

214:   inline const Type_t* operator[](size_type i) const { return X.data() + i * D2; }

215:

216:   /// returns a pointer of i-th row, g++ iterator problem

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

0x461b20 SUB	SP, SP, #224

0x461b24 STP	X29, X30, [SP, #32]

0x461b28 ADD	X29, SP, #32

0x461b2c STP	X19, X20, [SP, #48]

0x461b30 ORR	X19, XZR, X0

0x461b34 ADD	X20, X0, #440

0x461b38 STP	X21, X22, [SP, #64]

0x461b3c ORR	W22, WZR, W2

0x461b40 ORR	X21, XZR, X3

0x461b44 STP	X23, X24, [SP, #80]

0x461b48 ADD	X24, X0, #400

0x461b4c ORR	X23, XZR, X1

0x461b50 LDR	X0, [X0, #1128]

0x461b54 BL	4be880

0x461b58 LDR	X0, [X19, #1136]

0x461b5c ORR	X1, XZR, X23

0x461b60 ORR	X3, XZR, X24

0x461b64 ORR	W2, WZR, W22

0x461b68 ORR	X4, XZR, X20

0x461b6c ADD	X5, X19, #480

0x461b70 LDR	X6, [X0]

0x461b74 LDR	X7, [X6, #24]

0x461b78 BLR	X7

0x461b7c LDR	X0, [X19, #1128]

0x461b80 BL	4beb20

0x461b84 LDR	X0, [X19, #1096]

0x461b88 BL	4be880

0x461b8c LDR	W1, [X19, #1144]

0x461b90 MOVZ	W2, #2

0x461b94 LDR	W0, [X19, #1072]

0x461b98 STR	W2, [X19, #12]

0x461b9c SUB	W3, W22, W1

0x461ba0 CMP	W0, W3

0x461ba4 B.NE	461e8c

0x461ba8 LDR	X12, [X19, #1040]

0x461bac LDR	X0, [X19, #1056]

(1166) 0x461bb0 ORR	W17, WZR, W12

(1166) 0x461bb4 LDR	X30, [X24, #24]

(1166) 0x461bb8 CMP	W12, #0

(1166) 0x461bbc B.LE	462084

(1166) 0x461bc0 MOVI	D2, #0

(1166) 0x461bc4 SUB	W24, W12, #1

(1166) 0x461bc8 MOVZ	X2, #1

(1166) 0x461bcc LDR	D29, [X0]

(1166) 0x461bd0 AND	W7, W24, #128

(1166) 0x461bd4 LDR	D30, [X30]

(1166) 0x461bd8 FMADD	D25, D29, D30, D2

(1166) 0x461bdc CMP	W12, #1

(1166) 0x461be0 B.LE	461d18

(1166) 0x461be4 CBZ	W7, 461c90

(1166) 0x461be8 CMP	W7, #1

(1166) 0x461bec B.EQ	461c78

(1166) 0x461bf0 CMP	W7, #2

(1166) 0x461bf4 B.EQ	461c68

(1166) 0x461bf8 CMP	W7, #3

(1166) 0x461bfc B.EQ	461c58

(1166) 0x461c00 CMP	W7, #4

(1166) 0x461c04 B.EQ	461c48

(1166) 0x461c08 CMP	W7, #5

(1166) 0x461c0c B.EQ	461c38

(1166) 0x461c10 CMP	W7, #6

(1166) 0x461c14 B.EQ	461c28

(1166) 0x461c18 LDR	D3, [X0, #8]

(1166) 0x461c1c MOVZ	X2, #2

(1166) 0x461c20 LDR	D4, [X30, #8]

(1166) 0x461c24 FMADD	D25, D3, D4, D25

(1166) 0x461c28 LDR	D5, [X0, X2,LSL #3]

(1166) 0x461c2c LDR	D6, [X30, X2,LSL #3]

(1166) 0x461c30 ADD	X2, X2, #1

(1166) 0x461c34 FMADD	D25, D5, D6, D25

(1166) 0x461c38 LDR	D7, [X0, X2,LSL #3]

(1166) 0x461c3c LDR	D16, [X30, X2,LSL #3]

(1166) 0x461c40 ADD	X2, X2, #1

(1166) 0x461c44 FMADD	D25, D7, D16, D25

(1166) 0x461c48 LDR	D17, [X0, X2,LSL #3]

(1166) 0x461c4c LDR	D18, [X30, X2,LSL #3]

(1166) 0x461c50 ADD	X2, X2, #1

(1166) 0x461c54 FMADD	D25, D17, D18, D25

(1166) 0x461c58 LDR	D19, [X0, X2,LSL #3]

(1166) 0x461c5c LDR	D20, [X30, X2,LSL #3]

(1166) 0x461c60 ADD	X2, X2, #1

(1166) 0x461c64 FMADD	D25, D19, D20, D25

(1166) 0x461c68 LDR	D21, [X0, X2,LSL #3]

(1166) 0x461c6c LDR	D22, [X30, X2,LSL #3]

(1166) 0x461c70 ADD	X2, X2, #1

(1166) 0x461c74 FMADD	D25, D21, D22, D25

(1166) 0x461c78 LDR	D23, [X0, X2,LSL #3]

(1166) 0x461c7c LDR	D24, [X30, X2,LSL #3]

(1166) 0x461c80 ADD	X2, X2, #1

(1166) 0x461c84 FMADD	D25, D23, D24, D25

(1166) 0x461c88 CMP	W17, W2

(1166) 0x461c8c B.LE	461d18

  (1168) 0x461c90 LDR	D27, [X0, X2,LSL #3]

  (1168) 0x461c94 ADD	X1, X2, #1

  (1168) 0x461c98 ADD	X5, X2, #2

  (1168) 0x461c9c ADD	X3, X2, #3

  (1168) 0x461ca0 ADD	X16, X2, #4

  (1168) 0x461ca4 LDR	D26, [X30, X2,LSL #3]

  (1168) 0x461ca8 ADD	X8, X2, #5

  (1168) 0x461cac ADD	X9, X2, #6

  (1168) 0x461cb0 ADD	X11, X2, #7

  (1168) 0x461cb4 ADD	X2, X2, #8

  (1168) 0x461cb8 LDR	D28, [X0, X1,LSL #3]

  (1168) 0x461cbc LDR	D0, [X30, X1,LSL #3]

  (1168) 0x461cc0 FMADD	D31, D27, D26, D25

  (1168) 0x461cc4 LDR	D1, [X0, X5,LSL #3]

  (1168) 0x461cc8 LDR	D2, [X30, X5,LSL #3]

  (1168) 0x461ccc LDR	D3, [X0, X3,LSL #3]

  (1168) 0x461cd0 FMADD	D30, D28, D0, D31

  (1168) 0x461cd4 LDR	D4, [X30, X3,LSL #3]

  (1168) 0x461cd8 LDR	D29, [X0, X16,LSL #3]

  (1168) 0x461cdc FMADD	D5, D1, D2, D30

  (1168) 0x461ce0 LDR	D6, [X30, X16,LSL #3]

  (1168) 0x461ce4 LDR	D7, [X0, X8,LSL #3]

  (1168) 0x461ce8 LDR	D16, [X30, X8,LSL #3]

  (1168) 0x461cec FMADD	D17, D3, D4, D5

  (1168) 0x461cf0 LDR	D18, [X0, X9,LSL #3]

  (1168) 0x461cf4 LDR	D19, [X30, X9,LSL #3]

  (1168) 0x461cf8 FMADD	D20, D29, D6, D17

  (1168) 0x461cfc LDR	D21, [X0, X11,LSL #3]

  (1168) 0x461d00 LDR	D22, [X30, X11,LSL #3]

  (1168) 0x461d04 FMADD	D23, D7, D16, D20

  (1168) 0x461d08 FMADD	D24, D18, D19, D23

  (1168) 0x461d0c FMADD	D25, D21, D22, D24

  (1168) 0x461d10 CMP	W17, W2

  (1168) 0x461d14 B.GT	461c90

(1166) 0x461d18 ORR	X10, XZR, X0

(1166) 0x461d1c SUB	W0, W12, #1

(1166) 0x461d20 MOVI	D30, #0

(1166) 0x461d24 FMOV	D27, #1.0000000

(1166) 0x461d28 LDR	X22, [X20, #24]

(1166) 0x461d2c ADD	X14, X10, #8

(1166) 0x461d30 ADD	X13, X14, W0,UXTW #3

(1166) 0x461d34 SUB	X15, X13, X10

(1166) 0x461d38 STR	D25, [X19, #1080]

(1166) 0x461d3c SUB	X18, X15, #8

(1166) 0x461d40 UBFM	X6, X18, #3, #63

(1166) 0x461d44 ADD	X4, X6, #1

(1166) 0x461d48 FDIV	D0, D27, D25

(1166) 0x461d4c FMOV	D17, D30

(1166) 0x461d50 ANDS	X23, X4, #4160

(1166) 0x461d54 FMOV	D29, D30

(1166) 0x461d58 B.EQ	461dc0

(1166) 0x461d5c CMP	X23, #1

(1166) 0x461d60 B.EQ	461da0

(1166) 0x461d64 CMP	X23, #2

(1166) 0x461d68 B.EQ	461d88

(1166) 0x461d6c LDR	D25, [X10]

(1166) 0x461d70 ORR	X10, XZR, X14

(1166) 0x461d74 LDR	D26, [X22, #16]

(1166) 0x461d78 LDP	D31, D28, [X22], #24

(1166) 0x461d7c FMADD	D17, D25, D28, D30

(1166) 0x461d80 FMADD	D29, D25, D31, D30

(1166) 0x461d84 FMADD	D30, D25, D26, D30

(1166) 0x461d88 LDR	D1, [X10], #8

(1166) 0x461d8c LDR	D2, [X22, #16]

(1166) 0x461d90 LDP	D3, D4, [X22], #24

(1166) 0x461d94 FMADD	D30, D1, D2, D30

(1166) 0x461d98 FMADD	D17, D1, D4, D17

(1166) 0x461d9c FMADD	D29, D1, D3, D29

(1166) 0x461da0 LDR	D5, [X10], #8

(1166) 0x461da4 LDR	D6, [X22, #16]

(1166) 0x461da8 LDP	D7, D16, [X22], #24

(1166) 0x461dac FMADD	D30, D5, D6, D30

(1166) 0x461db0 FMADD	D17, D5, D16, D17

(1166) 0x461db4 FMADD	D29, D5, D7, D29

(1166) 0x461db8 CMP	X13, X10

(1166) 0x461dbc B.EQ	461e40

  (1167) 0x461dc0 ORR	X17, XZR, X22

  (1167) 0x461dc4 ORR	X30, XZR, X10

  (1167) 0x461dc8 LDP	D23, D24, [X22, #8]

  (1167) 0x461dcc ADD	X24, X22, #48

  (1167) 0x461dd0 ADD	X7, X22, #72

  (1167) 0x461dd4 LDR	D21, [X17], #24

  (1167) 0x461dd8 ADD	X10, X10, #32

  (1167) 0x461ddc ADD	X22, X22, #96

  (1167) 0x461de0 LDR	D22, [X30], #8

  (1167) 0x461de4 LDUR	D27, [X10, #488]

  (1167) 0x461de8 LDP	D28, D25, [X17, #8]

  (1167) 0x461dec LDUR	D5, [X22, #440]

  (1167) 0x461df0 FMADD	D1, D22, D24, D30

  (1167) 0x461df4 FMADD	D31, D22, D23, D17

  (1167) 0x461df8 FMADD	D26, D22, D21, D29

  (1167) 0x461dfc LDR	D19, [X30, #8]

  (1167) 0x461e00 LDP	D4, D7, [X24, #8]

  (1167) 0x461e04 FMADD	D3, D27, D25, D1

  (1167) 0x461e08 FMADD	D2, D27, D28, D31

  (1167) 0x461e0c LDUR	D18, [X22, #464]

  (1167) 0x461e10 FMADD	D29, D27, D5, D26

  (1167) 0x461e14 LDUR	D5, [X10, #504]

  (1167) 0x461e18 FMADD	D30, D19, D7, D3

  (1167) 0x461e1c LDUR	D7, [X22, #488]

  (1167) 0x461e20 FMADD	D17, D19, D4, D2

  (1167) 0x461e24 LDP	D16, D6, [X7, #8]

  (1167) 0x461e28 FMADD	D29, D19, D18, D29

  (1167) 0x461e2c FMADD	D29, D5, D7, D29

  (1167) 0x461e30 FMADD	D17, D5, D16, D17

  (1167) 0x461e34 FMADD	D30, D5, D6, D30

  (1167) 0x461e38 CMP	X13, X10

  (1167) 0x461e3c B.NE	461dc0

(1166) 0x461e40 FMUL	D18, D0, D17

(1166) 0x461e44 FMUL	D19, D0, D29

(1166) 0x461e48 FMUL	D20, D0, D30

(1166) 0x461e4c LDR	D30, [X21, #16]

(1166) 0x461e50 LDP	D0, D6, [X21]

(1166) 0x461e54 LDR	X0, [X19, #1096]

(1166) 0x461e58 FADD	D20, D30, D20

(1166) 0x461e5c FADD	D16, D0, D19

(1166) 0x461e60 FADD	D17, D6, D18

(1166) 0x461e64 STR	D20, [X21, #16]

(1166) 0x461e68 STP	D16, D17, [X21]

(1166) 0x461e6c BL	4beb20

(1166) 0x461e70 LDR	D0, [X19, #1080]

(1166) 0x461e74 LDP	X29, X30, [SP, #32]

(1166) 0x461e78 LDP	X21, X22, [SP, #64]

(1166) 0x461e7c LDP	X23, X24, [SP, #80]

(1166) 0x461e80 LDP	X19, X20, [SP, #48]

(1166) 0x461e84 ADD	SP, SP, #224

(1166) 0x461e88 RET

(1166) 0x461e8c STP	X27, X28, [SP, #112]

(1166) 0x461e90 SBFM	X4, X3, #0, #31

(1166) 0x461e94 ADD	X28, X19, #520

(1166) 0x461e98 LDR	X8, [X19, #216]

(1166) 0x461e9c STR	W3, [X19, #1072]

(1166) 0x461ea0 LDR	X5, [X19, #256]

(1166) 0x461ea4 LDR	W12, [X28, #360]

(1166) 0x461ea8 MADD	X9, X4, X8, XZR

(1166) 0x461eac ADD	X1, X5, X9,LSL #3

(1166) 0x461eb0 UBFM	X10, X9, #61, #60

(1166) 0x461eb4 CBZ	W12, 462054

(1166) 0x461eb8 STP	X25, X26, [SP, #96]

(1166) 0x461ebc ADD	X27, X19, #1032

(1166) 0x461ec0 ADD	X25, X19, #648

(1166) 0x461ec4 LDR	X11, [X25, #8]

(1166) 0x461ec8 LDR	X23, [X19, #208]

(1166) 0x461ecc LDR	X6, [X27, #24]

(1166) 0x461ed0 STR	D15, [SP, #128]

(1166) 0x461ed4 STR	X11, [SP, #144]

(1166) 0x461ed8 CMP	W23, #0

(1166) 0x461edc B.LE	461efc

(1166) 0x461ee0 UBFM	X2, X23, #61, #31

(1166) 0x461ee4 CMP	X2, #8

(1166) 0x461ee8 B.EQ	46209c

(1166) 0x461eec ORR	X0, XZR, X6

(1166) 0x461ef0 BL	403d60

(1166) 0x461ef4 LDR	X6, [X27, #24]

(1166) 0x461ef8 LDR	W12, [X28, #360]

(1166) 0x461efc FMOV	D15, #1.0000000

(1166) 0x461f00 ADD	X26, SP, #204

(1166) 0x461f04 ADD	X13, SP, #216

(1166) 0x461f08 STR	XZR, [SP, #216]

(1166) 0x461f0c LDR	X16, [X19, #840]

(1166) 0x461f10 MOVZ	W22, #1

(1166) 0x461f14 MOVZ	W15, #84

(1166) 0x461f18 ADD	X14, X19, #816

(1166) 0x461f1c ADD	X7, SP, #200

(1166) 0x461f20 LDR	X4, [X19, #568]

(1166) 0x461f24 ADD	X5, SP, #196

(1166) 0x461f28 ADD	X2, SP, #192

(1166) 0x461f2c ADD	X0, SP, #187

(1166) 0x461f30 ADD	X1, SP, #188

(1166) 0x461f34 STR	X26, [SP, #16]

(1166) 0x461f38 ADD	X3, SP, #208

(1166) 0x461f3c STR	X14, [SP, #168]

(1166) 0x461f40 STP	X13, X16, [SP]

(1166) 0x461f44 STRB	W15, [SP, #187]

(1166) 0x461f48 STP	W23, W12, [SP, #188]

(1166) 0x461f4c STP	W23, W22, [SP, #196]

(1166) 0x461f50 STR	W22, [SP, #204]

(1166) 0x461f54 STR	D15, [SP, #208]

(1166) 0x461f58 BL	404020

(1166) 0x461f5c LDR	W10, [X28, #360]

(1166) 0x461f60 ADD	X4, SP, #216

(1166) 0x461f64 MOVZ	W6, #78

(1166) 0x461f68 ADD	X18, X19, #672

(1166) 0x461f6c ADD	X7, SP, #200

(1166) 0x461f70 STR	W22, [SP, #204]

(1166) 0x461f74 LDR	W9, [SP, #144]

(1166) 0x461f78 ADD	X5, SP, #196

(1166) 0x461f7c ADD	X3, SP, #208

(1166) 0x461f80 STR	X4, [SP]

(1166) 0x461f84 ADD	X2, SP, #192

(1166) 0x461f88 ADD	X1, SP, #188

(1166) 0x461f8c LDR	X11, [SP, #168]

(1166) 0x461f90 ADD	X0, SP, #187

(1166) 0x461f94 STP	W10, W10, [SP, #188]

(1166) 0x461f98 SBFM	X8, X10, #0, #31

(1166) 0x461f9c STR	W6, [SP, #156]

(1166) 0x461fa0 STP	W9, W22, [SP, #196]

(1166) 0x461fa4 LDR	X12, [X25, #8]

(1166) 0x461fa8 STR	X26, [SP, #16]

(1166) 0x461fac LDR	X4, [X19, #696]

(1166) 0x461fb0 STRB	W6, [SP, #187]

(1166) 0x461fb4 LDR	X6, [X11, #24]

(1166) 0x461fb8 MADD	X14, X8, X12, XZR

(1166) 0x461fbc STR	X18, [SP, #160]

(1166) 0x461fc0 STR	D15, [SP, #208]

(1166) 0x461fc4 STR	XZR, [SP, #216]

(1166) 0x461fc8 ADD	X13, X4, X14,LSL #3

(1166) 0x461fcc STR	X13, [SP, #8]

(1166) 0x461fd0 BL	404020

(1166) 0x461fd4 LDR	W28, [X28, #360]

(1166) 0x461fd8 FMOV	D0, #-1.0000000

(1166) 0x461fdc ADD	X15, SP, #216

(1166) 0x461fe0 ADD	X0, SP, #187

(1166) 0x461fe4 STP	W23, W22, [SP, #196]

(1166) 0x461fe8 ADD	X7, SP, #200

(1166) 0x461fec ADD	X5, SP, #196

(1166) 0x461ff0 LDR	X4, [SP, #160]

(1166) 0x461ff4 ADD	X3, SP, #208

(1166) 0x461ff8 ADD	X2, SP, #192

(1166) 0x461ffc STR	X15, [SP]

(1166) 0x462000 ADD	X1, SP, #188

(1166) 0x462004 STP	D0, D15, [SP, #208]

(1166) 0x462008 STP	W23, W28, [SP, #188]

(1166) 0x46200c SBFM	X18, X28, #0, #31

(1166) 0x462010 LDR	X25, [X25, #8]

(1166) 0x462014 STR	W22, [SP, #204]

(1166) 0x462018 LDR	X23, [X4, #24]

(1166) 0x46201c LDR	X10, [X27, #24]

(1166) 0x462020 MADD	X22, X18, X25, XZR

(1166) 0x462024 LDR	W6, [SP, #156]

(1166) 0x462028 STP	X10, X26, [SP, #8]

(1166) 0x46202c LDR	X4, [X19, #632]

(1166) 0x462030 STRB	W6, [SP, #187]

(1166) 0x462034 ADD	X6, X23, X22,LSL #3

(1166) 0x462038 BL	404020

(1166) 0x46203c LDR	X12, [X27, #8]

(1166) 0x462040 LDP	X25, X26, [SP, #96]

(1166) 0x462044 LDR	X0, [X27, #24]

(1166) 0x462048 LDP	X27, X28, [SP, #112]

(1166) 0x46204c LDR	D15, [SP, #128]

(1166) 0x462050 B	461bb0

(1166) 0x462054 LDR	X12, [X19, #1040]

(1166) 0x462058 CBZ	X12, 462080

(1166) 0x46205c UBFM	X2, X12, #61, #60

(1166) 0x462060 LDR	X0, [X19, #1056]

(1166) 0x462064 CMP	X2, #8

(1166) 0x462068 B.LE	4620a8

(1166) 0x46206c BL	403d60

(1166) 0x462070 LDR	X12, [X19, #1040]

(1166) 0x462074 LDP	X27, X28, [SP, #112]

(1166) 0x462078 LDR	X0, [X19, #1056]

(1166) 0x46207c B	461bb0

(1166) 0x462080 LDP	X27, X28, [SP, #112]

(1166) 0x462084 MOVZ	X2, #32760

(1166) 0x462088 FMOV	D20, X2

(1166) 0x46208c STR	XZR, [X19, #1080]

(1166) 0x462090 FMOV	D19, D20

(1166) 0x462094 FMOV	D18, D20

(1166) 0x462098 B	461e4c

(1166) 0x46209c LDR	D31, [X5, X10]

(1166) 0x4620a0 STR	D31, [X6]

(1166) 0x4620a4 B	461efc

(1166) 0x4620a8 B.EQ	4620b4

(1166) 0x4620ac LDP	X27, X28, [SP, #112]

(1166) 0x4620b0 B	461bb0

(1166) 0x4620b4 LDR	D1, [X5, X10]

(1166) 0x4620b8 STR	D1, [X0]

(1166) 0x4620bc LDP	X27, X28, [SP, #112]

(1166) 0x4620c0 B	461bb0

0x4620c4 HINT	#0

0x4620c8 HINT	#0

0x4620cc HINT	#0

0x4620d0 HINT	#0

0x4620d4 HINT	#0

0x4620d8 HINT	#0

0x4620dc HINT	#0

Coverage (%)	Name	Source Location	Module
►49.98+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►48.69+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	DiracDeterminantRef.cpp:94-118
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:94-103,109-118
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,92-94
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.17 to 4.21 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.00 cycles (2.58x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50
cycles	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

14% of peak load performance is reached (13.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 461b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X20, X0, #440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR W22, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X0, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W2, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X4, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X19, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4beb20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W0, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W2, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W3, W22, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 461e8c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	DiracDeterminantRef.cpp:94-118
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:94-103,109-118
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,92-94
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.00 cycles (2.58x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	43
loop length	172
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50
cycles	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

14% of peak load performance is reached (13.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 461b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X20, X0, #440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR W22, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X0, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W2, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X4, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X19, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4beb20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W0, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W2, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W3, W22, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 461e8c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x36c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X12, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)–	0.11	0.16
▼Loop 1166 - OhmmsVector.h:178-248 - exec–	0.00	0.01
○Loop 1167 - inner_product.hpp:155-155 - exec	0.06	0.08
○Loop 1168 - inner_product.hpp:82-83 - exec	0.05	0.07

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code