OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::acceptMove(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::accept ...	Module: exec	Source: DiracDeterminantRef.cpp:123-139 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 1128 - 1131

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1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 53 - 54

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53:   std::memcpy(target, source, sizeof(T) * n);

54: }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h: 683 - 709

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683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/OpenMP.h: 38 - 38

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38: #pragma omp parallel

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

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223:     return X[i];

[...]

248:   inline pointer data() { return X; }

249:   inline const_pointer data() const { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 123 - 139

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123: void DiracDeterminantRef<DU_TYPE>::acceptMove(ParticleSet& P, int iat)

124: {

125:   const int WorkingIndex = iat - FirstIndex;

126:   PhaseValue += evaluatePhase(curRatio);

127:   LogValue += std::log(std::abs(curRatio));

128:   UpdateTimer->start();

129:   updateEng.acceptRow(psiM, WorkingIndex, psiV);

130:   // invRow becomes invalid after accepting a move

131:   invRow_id = -1;

132:   if (UpdateMode == ORB_PBYP_PARTIAL)

133:   {

134:     simd::copy(dpsiM[WorkingIndex], dpsiV.data(), NumOrbitals);

135:     simd::copy(d2psiM[WorkingIndex], d2psiV.data(), NumOrbitals);

136:   }

137:   UpdateTimer->stop();

138:   curRatio = 1.0;

139: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DeterminantHelper.h: 23 - 23

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23:   return T((sign_v > 0) ? 0.0 : M_PI);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 413 - 452

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 128 - 230

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128:     const int norb     = Ainv.rows();

129:     const int lda_Binv = Binv.cols();

130:     std::copy_n(Ainv[rowchanged], norb, V[delay_count]);

131:     std::copy_n(psiV.data(), norb, U[delay_count]);

132:     delay_list[delay_count] = rowchanged;

133:     // the new Binv is [[X Y] [Z x]]

134:     BLAS::gemv('T', norb, delay_count + 1, cminusone, V.data(), norb, psiV.data(), 1, czero, p.data(), 1);

135:     // x

136:     T y = -p[delay_count];

137:     for (int i = 0; i < delay_count; i++)

138:       y += Binv[delay_count][i] * p[i];

139:     Binv[delay_count][delay_count] = y = T(1) / y;

140:     // Y

141:     BLAS::gemv('T', delay_count, delay_count, y, Binv.data(), lda_Binv, p.data(), 1, czero, Binv.data() + delay_count,

142:                lda_Binv);

143:     // X

144:     BLAS::ger(delay_count, delay_count, cminusone, Binv[delay_count], 1, Binv.data() + delay_count, lda_Binv,

145:               Binv.data(), lda_Binv);

146:     // Z

147:     for (int i = 0; i < delay_count; i++)

148:       Binv[delay_count][i] *= -y;

149:     delay_count++;

[...]

160:     if (delay_count == 0)

161:       return;

162:     // update the inverse matrix

163:     const T cone(1);

164:     const T czero(0);

165:     const int norb = Ainv.rows();

166:     if (delay_count == 1)

167:     {

168:       // this is a special case invoking the Fahy's variant of Sherman-Morrison update.

169:       // Only use the first norb elements of tempMat as a temporal array

170:       BLAS::gemv('T', norb, norb, cone, Ainv.data(), norb, U[0], 1, czero, temp.data(), 1);

171:       temp[delay_list[0]] -= cone;

172:       BLAS::ger(norb, norb, -Binv[0][0], V[0], 1, temp.data(), 1, Ainv.data(), norb);

173:     }

174:     else

175:     {

176:       const int lda_Binv     = Binv.cols();

177:       int num_threads_nested = getNextLevelNumThreads();

178:       // always use serial when norb is small or only one second level thread

179:       bool use_serial(norb <= 256 || num_threads_nested == 1);

180:       if (use_serial || BlasThreadingEnv::NestedThreadingSupported())

181:       {

182:         // threading depends on BLAS

183:         BlasThreadingEnv knob(use_serial ? 1 : num_threads_nested);

184:         BLAS::gemm('T', 'N', delay_count, norb, norb, cone, U.data(), norb, Ainv.data(), norb, czero, tempMat.data(),

185:                    lda_Binv);

186:         for (int i = 0; i < delay_count; i++)

187:           tempMat(delay_list[i], i) -= cone;

188:         BLAS::gemm('N', 'N', norb, delay_count, delay_count, cone, V.data(), norb, Binv.data(), lda_Binv, czero,

189:                    U.data(), norb);

190:         BLAS::gemm('N', 'N', norb, norb, delay_count, -cone, U.data(), norb, tempMat.data(), lda_Binv, cone,

191:                    Ainv.data(), norb);

192:       }

193:       else

194:       {

195:         // manually threaded version of the above GEMM calls

196: #pragma omp parallel

[...]

230:     delay_count = 0;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 447

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187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

[...]

249:     dgemm(Atrans, Btrans, M, N, K, alpha, A, lda, B, ldb, beta, C, ldc);

[...]

447:     dger(&m, &n, &alpha, x, &incx, y, &incy, a, &lda);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 236

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77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

[...]

236:     return X[i * D2 + j];

0x461140 SUB	SP, SP, #336

0x461144 MOVI	D31, #0

0x461148 ADRP	X1,

0x46114c STP	X29, X30, [SP, #48]

0x461150 ADD	X29, SP, #48

0x461154 STP	X19, X20, [SP, #64]

0x461158 ORR	X19, XZR, X0

0x46115c STP	X21, X22, [SP, #80]

0x461160 STP	X23, X24, [SP, #96]

0x461164 ADD	X24, X0, #648

0x461168 ADD	X23, X0, #608

0x46116c STP	X25, X26, [SP, #112]

0x461170 ADD	X25, X0, #208

0x461174 ADD	X26, X0, #520

0x461178 STP	X27, X28, [SP, #128]

0x46117c STP	D14, D15, [SP, #144]

0x461180 LDR	D0, [X19, #1080]

0x461184 LDR	D30, [X1, #3952]

0x461188 LDP	D15, D2, [X19, #16]

0x46118c FCMPE	D0, D31

0x461190 LDR	W0, [X0, #1144]

0x461194 FABS	D0, D0

0x461198 SUB	W28, W2, W0

0x46119c FCSEL	D1, D31, D30, #12

0x4611a0 FADD	D3, D2, D1

0x4611a4 STR	D3, [X19, #24]

0x4611a8 BL	403dc0

0x4611ac FADD	D4, D15, D0

0x4611b0 LDR	X0, [X19, #1088]

0x4611b4 STR	D4, [X19, #16]

0x4611b8 BL	4be880

0x4611bc LDR	X9, [X19, #208]

0x4611c0 SBFM	X2, X28, #0, #31

0x4611c4 STR	X2, [SP, #168]

0x4611c8 LDR	X27, [X24, #8]

0x4611cc LDR	X4, [X23, #24]

0x4611d0 LDRSW	X3, [X19, #880]

0x4611d4 CMP	W9, #0

0x4611d8 B.LE	46166c

0x4611dc SBFM	X5, X28, #0, #31

0x4611e0 UBFM	X21, X9, #61, #31

0x4611e4 LDR	X10, [X25, #8]

0x4611e8 LDR	X6, [X19, #592]

0x4611ec LDR	X7, [X19, #256]

0x4611f0 MADD	X11, X5, X10, XZR

0x4611f4 MADD	X8, X3, X6, XZR

0x4611f8 UBFM	X12, X11, #61, #60

0x4611fc ADD	X1, X7, X11,LSL #3

0x461200 ADD	X0, X4, X8,LSL #3

0x461204 UBFM	X13, X8, #61, #60

0x461208 CMP	X21, #8

0x46120c B.EQ	461aa4

0x461210 ORR	X2, XZR, X21

0x461214 STR	X9, [SP, #160]

0x461218 BL	403d60

0x46121c LDR	X4, [X26, #8]

0x461220 ORR	X2, XZR, X21

0x461224 LDRSW	X9, [X26, #360]

0x461228 LDR	X3, [X19, #568]

0x46122c LDR	X1, [X19, #424]

0x461230 MADD	X18, X9, X4, XZR

0x461234 ADD	X0, X3, X18,LSL #3

0x461238 BL	403d60

0x46123c LDR	X4, [X23, #24]

0x461240 LDR	X9, [SP, #160]

0x461244 LDR	X6, [X19, #424]

0x461248 LDRSW	X3, [X26, #360]

(1162) 0x46124c FMOV	D7, #-1.0000000

(1162) 0x461250 MOVZ	W8, #1

(1162) 0x461254 ADD	X21, SP, #288

(1162) 0x461258 LDR	X0, [X19, #856]

(1162) 0x46125c ADD	X20, SP, #304

(1162) 0x461260 ADD	X17, X19, #816

(1162) 0x461264 MOVZ	W30, #84

(1162) 0x461268 ADD	X22, SP, #296

(1162) 0x46126c LDR	X1, [X19, #840]

(1162) 0x461270 ADD	X7, SP, #280

(1162) 0x461274 ADD	X5, SP, #272

(1162) 0x461278 ADD	X2, SP, #264

(1162) 0x46127c STR	X17, [SP, #160]

(1162) 0x461280 STR	W28, [X0, X3,LSL #2]

(1162) 0x461284 ORR	X3, XZR, X22

(1162) 0x461288 ADD	X0, SP, #256

(1162) 0x46128c LDR	W10, [X26, #360]

(1162) 0x461290 ADD	X28, X19, #672

(1162) 0x461294 STP	X20, X1, [SP]

(1162) 0x461298 ADD	X1, SP, #260

(1162) 0x46129c STR	X21, [SP, #16]

(1162) 0x4612a0 ADD	W11, W10, W8

(1162) 0x4612a4 STRB	W30, [SP, #256]

(1162) 0x4612a8 STR	W9, [SP, #260]

(1162) 0x4612ac STR	W11, [SP, #264]

(1162) 0x4612b0 STR	W9, [SP, #272]

(1162) 0x4612b4 STR	W8, [SP, #280]

(1162) 0x4612b8 STR	W8, [SP, #288]

(1162) 0x4612bc STR	D7, [SP, #296]

(1162) 0x4612c0 STR	XZR, [SP, #304]

(1162) 0x4612c4 BL	404020

(1162) 0x4612c8 LDR	X2, [SP, #160]

(1162) 0x4612cc LDR	W14, [X26, #360]

(1162) 0x4612d0 LDR	X7, [X24, #8]

(1162) 0x4612d4 LDR	X6, [X2, #24]

(1162) 0x4612d8 SBFM	X12, X14, #61, #31

(1162) 0x4612dc SBFM	X5, X14, #0, #31

(1162) 0x4612e0 LDR	X4, [X28, #24]

(1162) 0x4612e4 LDR	D14, [X6, X12]

(1162) 0x4612e8 FNEG	D30, D14

(1162) 0x4612ec CMP	W14, #0

(1162) 0x4612f0 B.LE	461434

(1162) 0x4612f4 SUB	X13, X12, #8

(1162) 0x4612f8 MADD	X15, X5, X7, XZR

(1162) 0x4612fc MOVZ	X17, #0

(1162) 0x461300 UBFM	X16, X13, #3, #63

(1162) 0x461304 ADD	X18, X16, #1

(1162) 0x461308 ANDS	X3, X18, #4224

(1162) 0x46130c ADD	X9, X4, X15,LSL #3

(1162) 0x461310 B.EQ	4613ac

(1162) 0x461314 CMP	X3, #1

(1162) 0x461318 B.EQ	461394

(1162) 0x46131c CMP	X3, #2

(1162) 0x461320 B.EQ	461384

(1162) 0x461324 CMP	X3, #3

(1162) 0x461328 B.EQ	461374

(1162) 0x46132c CMP	X3, #4

(1162) 0x461330 B.EQ	461364

(1162) 0x461334 CMP	X3, #5

(1162) 0x461338 B.EQ	461354

(1162) 0x46133c CMP	X3, #6

(1162) 0x461340 B.NE	4616c4

(1162) 0x461344 LDR	D26, [X9, X17]

(1162) 0x461348 LDR	D25, [X6, X17]

(1162) 0x46134c ADD	X17, X17, #8

(1162) 0x461350 FMADD	D30, D26, D25, D30

(1162) 0x461354 LDR	D16, [X9, X17]

(1162) 0x461358 LDR	D24, [X6, X17]

(1162) 0x46135c ADD	X17, X17, #8

(1162) 0x461360 FMADD	D30, D16, D24, D30

(1162) 0x461364 LDR	D23, [X9, X17]

(1162) 0x461368 LDR	D22, [X6, X17]

(1162) 0x46136c ADD	X17, X17, #8

(1162) 0x461370 FMADD	D30, D23, D22, D30

(1162) 0x461374 LDR	D21, [X9, X17]

(1162) 0x461378 LDR	D20, [X6, X17]

(1162) 0x46137c ADD	X17, X17, #8

(1162) 0x461380 FMADD	D30, D21, D20, D30

(1162) 0x461384 LDR	D19, [X9, X17]

(1162) 0x461388 LDR	D18, [X6, X17]

(1162) 0x46138c ADD	X17, X17, #8

(1162) 0x461390 FMADD	D30, D19, D18, D30

(1162) 0x461394 LDR	D17, [X9, X17]

(1162) 0x461398 LDR	D29, [X6, X17]

(1162) 0x46139c ADD	X17, X17, #8

(1162) 0x4613a0 FMADD	D30, D17, D29, D30

(1162) 0x4613a4 CMP	X12, X17

(1162) 0x4613a8 B.EQ	461434

  (1165) 0x4613ac LDR	D31, [X9, X17]

  (1165) 0x4613b0 ADD	X30, X17, #8

  (1165) 0x4613b4 ADD	X1, X17, #16

  (1165) 0x4613b8 ADD	X8, X17, #24

  (1165) 0x4613bc ADD	X0, X17, #32

  (1165) 0x4613c0 LDR	D0, [X6, X17]

  (1165) 0x4613c4 ADD	X11, X17, #40

  (1165) 0x4613c8 ADD	X10, X17, #48

  (1165) 0x4613cc ADD	X2, X17, #56

  (1165) 0x4613d0 ADD	X17, X17, #64

  (1165) 0x4613d4 LDR	D5, [X9, X30]

  (1165) 0x4613d8 LDR	D4, [X6, X30]

  (1165) 0x4613dc FMADD	D15, D31, D0, D30

  (1165) 0x4613e0 LDR	D3, [X9, X1]

  (1165) 0x4613e4 LDR	D2, [X6, X1]

  (1165) 0x4613e8 LDR	D1, [X9, X8]

  (1165) 0x4613ec FMADD	D6, D5, D4, D15

  (1165) 0x4613f0 LDR	D7, [X6, X8]

  (1165) 0x4613f4 LDR	D14, [X9, X0]

  (1165) 0x4613f8 FMADD	D27, D3, D2, D6

  (1165) 0x4613fc LDR	D25, [X6, X0]

  (1165) 0x461400 LDR	D16, [X9, X11]

  (1165) 0x461404 LDR	D28, [X6, X11]

  (1165) 0x461408 FMADD	D24, D1, D7, D27

  (1165) 0x46140c LDR	D23, [X9, X10]

  (1165) 0x461410 LDR	D26, [X6, X10]

  (1165) 0x461414 FMADD	D22, D14, D25, D24

  (1165) 0x461418 LDR	D21, [X9, X2]

  (1165) 0x46141c LDR	D20, [X6, X2]

  (1165) 0x461420 FMADD	D19, D16, D28, D22

  (1165) 0x461424 FMADD	D18, D23, D26, D19

  (1165) 0x461428 FMADD	D30, D21, D20, D18

  (1165) 0x46142c CMP	X12, X17

  (1165) 0x461430 B.NE	4613ac

(1162) 0x461434 FMOV	D14, #1.0000000

(1162) 0x461438 MADD	X13, X7, X5, X5

(1162) 0x46143c ADD	X12, X4, X12

(1162) 0x461440 MOVZ	W15, #84

(1162) 0x461444 MOVZ	W16, #1

(1162) 0x461448 ADD	X7, SP, #280

(1162) 0x46144c ADD	X5, SP, #272

(1162) 0x461450 ORR	X3, XZR, X22

(1162) 0x461454 STR	W15, [SP, #160]

(1162) 0x461458 ADD	X2, SP, #264

(1162) 0x46145c ADD	X1, SP, #260

(1162) 0x461460 FDIV	D15, D14, D30

(1162) 0x461464 ADD	X0, SP, #256

(1162) 0x461468 STR	D15, [X4, X13,LSL #3]

(1162) 0x46146c STP	X20, X12, [SP]

(1162) 0x461470 STR	X21, [SP, #16]

(1162) 0x461474 STRB	W15, [SP, #256]

(1162) 0x461478 STR	W14, [SP, #260]

(1162) 0x46147c STR	W14, [SP, #264]

(1162) 0x461480 STR	W27, [SP, #272]

(1162) 0x461484 STR	W16, [SP, #280]

(1162) 0x461488 STR	W27, [SP, #288]

(1162) 0x46148c STR	D15, [SP, #296]

(1162) 0x461490 STR	XZR, [SP, #304]

(1162) 0x461494 BL	404020

(1162) 0x461498 LDR	W7, [X26, #360]

(1162) 0x46149c FMOV	D17, #-1.0000000

(1162) 0x4614a0 MOVZ	W14, #1

(1162) 0x4614a4 ORR	X6, XZR, X21

(1162) 0x4614a8 STR	X22, [SP]

(1162) 0x4614ac ADD	X4, SP, #280

(1162) 0x4614b0 ORR	X2, XZR, X20

(1162) 0x4614b4 LDR	X18, [X24, #8]

(1162) 0x4614b8 ADD	X1, SP, #272

(1162) 0x4614bc ADD	X0, SP, #264

(1162) 0x4614c0 STR	W14, [SP, #280]

(1162) 0x4614c4 STR	W27, [SP, #288]

(1162) 0x4614c8 SBFM	X5, X7, #0, #31

(1162) 0x4614cc STR	W7, [SP, #264]

(1162) 0x4614d0 STR	W7, [SP, #272]

(1162) 0x4614d4 LDR	X7, [X28, #24]

(1162) 0x4614d8 MADD	X3, X5, X18, XZR

(1162) 0x4614dc STR	W27, [SP, #296]

(1162) 0x4614e0 STR	D17, [SP, #304]

(1162) 0x4614e4 ADD	X5, X7, X5,LSL #3

(1162) 0x4614e8 ADD	X3, X7, X3,LSL #3

(1162) 0x4614ec BL	403df0

(1162) 0x4614f0 LDR	W6, [X26, #360]

(1162) 0x4614f4 LDR	W4, [SP, #160]

(1162) 0x4614f8 CMP	W6, #0

(1162) 0x4614fc B.LE	4616e8

(1162) 0x461500 LDR	X30, [X24, #8]

(1162) 0x461504 SBFM	X17, X6, #0, #31

(1162) 0x461508 LDR	X0, [X28, #24]

(1162) 0x46150c MADD	X1, X17, X30, XZR

(1162) 0x461510 ADD	X10, X17, X1

(1162) 0x461514 ADD	X5, X0, X1,LSL #3

(1162) 0x461518 ADD	X2, X0, X10,LSL #3

(1162) 0x46151c SUB	X13, X2, X5

(1162) 0x461520 SUB	X12, X13, #8

(1162) 0x461524 UBFM	X15, X12, #3, #63

(1162) 0x461528 ADD	X16, X15, #1

(1162) 0x46152c ANDS	X14, X16, #4224

(1162) 0x461530 B.EQ	4615b4

(1162) 0x461534 CMP	X14, #1

(1162) 0x461538 B.EQ	4615a0

(1162) 0x46153c CMP	X14, #2

(1162) 0x461540 B.EQ	461594

(1162) 0x461544 CMP	X14, #3

(1162) 0x461548 B.EQ	461588

(1162) 0x46154c CMP	X14, #4

(1162) 0x461550 B.EQ	46157c

(1162) 0x461554 CMP	X14, #5

(1162) 0x461558 B.EQ	461570

(1162) 0x46155c CMP	X14, #6

(1162) 0x461560 B.NE	4616d8

(1162) 0x461564 LDR	D3, [X5]

(1162) 0x461568 FNMUL	D2, D3, D15

(1162) 0x46156c STR	D2, [X5], #8

(1162) 0x461570 LDR	D1, [X5]

(1162) 0x461574 FNMUL	D6, D1, D15

(1162) 0x461578 STR	D6, [X5], #8

(1162) 0x46157c LDR	D7, [X5]

(1162) 0x461580 FNMUL	D27, D7, D15

(1162) 0x461584 STR	D27, [X5], #8

(1162) 0x461588 LDR	D25, [X5]

(1162) 0x46158c FNMUL	D16, D25, D15

(1162) 0x461590 STR	D16, [X5], #8

(1162) 0x461594 LDR	D28, [X5]

(1162) 0x461598 FNMUL	D24, D28, D15

(1162) 0x46159c STR	D24, [X5], #8

(1162) 0x4615a0 LDR	D23, [X5]

(1162) 0x4615a4 FNMUL	D26, D23, D15

(1162) 0x4615a8 STR	D26, [X5], #8

(1162) 0x4615ac CMP	X2, X5

(1162) 0x4615b0 B.EQ	461614

  (1164) 0x4615b4 LDR	D22, [X5]

  (1164) 0x4615b8 ORR	X7, XZR, X5

  (1164) 0x4615bc FNMUL	D21, D22, D15

  (1164) 0x4615c0 STR	D21, [X7], #8

  (1164) 0x4615c4 LDR	D20, [X5, #8]

  (1164) 0x4615c8 FNMUL	D19, D20, D15

  (1164) 0x4615cc STR	D19, [X5, #8]

  (1164) 0x4615d0 LDR	D18, [X7, #8]

  (1164) 0x4615d4 FNMUL	D14, D18, D15

  (1164) 0x4615d8 STR	D14, [X7, #8]

  (1164) 0x4615dc LDR	D2, [X5, #56]

  (1164) 0x4615e0 LDP	D17, D29, [X5, #24]

  (1164) 0x4615e4 LDP	D30, D31, [X5, #40]

  (1164) 0x4615e8 ADD	X5, X5, #64

  (1164) 0x4615ec FNMUL	D1, D2, D15

  (1164) 0x4615f0 FNMUL	D5, D17, D15

  (1164) 0x4615f4 FNMUL	D4, D29, D15

  (1164) 0x4615f8 FNMUL	D3, D30, D15

  (1164) 0x4615fc FNMUL	D0, D31, D15

  (1164) 0x461600 STUR	D1, [X5, #504]

  (1164) 0x461604 STP	D5, D4, [X5, #984]

  (1164) 0x461608 STP	D3, D0, [X5, #1000]

  (1164) 0x46160c CMP	X2, X5

  (1164) 0x461610 B.NE	4615b4

(1162) 0x461614 ADD	W18, W6, #1

(1162) 0x461618 STR	W18, [X26, #360]

(1162) 0x46161c CMP	W27, W18

(1162) 0x461620 B.EQ	4617cc

(1162) 0x461624 LDR	W27, [X19, #12]

(1162) 0x461628 MOVN	W26, #0

(1162) 0x46162c STR	W26, [X19, #1072]

(1162) 0x461630 CMP	W27, #2

(1162) 0x461634 B.EQ	461674

(1162) 0x461638 LDR	X0, [X19, #1088]

(1162) 0x46163c BL	4beb20

(1162) 0x461640 FMOV	D31, #1.0000000

(1162) 0x461644 STR	D31, [X19, #1080]

(1162) 0x461648 LDP	D14, D15, [SP, #144]

(1162) 0x46164c LDP	X29, X30, [SP, #48]

(1162) 0x461650 LDP	X19, X20, [SP, #64]

(1162) 0x461654 LDP	X21, X22, [SP, #80]

(1162) 0x461658 LDP	X23, X24, [SP, #96]

(1162) 0x46165c LDP	X25, X26, [SP, #112]

(1162) 0x461660 LDP	X27, X28, [SP, #128]

(1162) 0x461664 ADD	SP, SP, #336

(1162) 0x461668 RET

(1162) 0x46166c LDR	X6, [X19, #424]

(1162) 0x461670 B	46124c

(1162) 0x461674 LDR	X22, [SP, #168]

(1162) 0x461678 MOVZ	W20, #24

(1162) 0x46167c LDR	X13, [X19, #280]

(1162) 0x461680 LDR	X16, [X19, #320]

(1162) 0x461684 LDR	W7, [X19, #1152]

(1162) 0x461688 MADD	X5, X22, X13, XZR

(1162) 0x46168c LDR	X1, [X19, #464]

(1162) 0x461690 ADD	X4, X5, X5,LSL #1

(1162) 0x461694 SMADDL	X2, W7, W20, XZR

(1162) 0x461698 ADD	X0, X16, X4,LSL #3

(1162) 0x46169c BL	404070

(1162) 0x4616a0 LDR	X11, [X19, #344]

(1162) 0x4616a4 LDR	X3, [X19, #384]

(1162) 0x4616a8 LDRSW	X8, [X19, #1152]

(1162) 0x4616ac MADD	X10, X22, X11, XZR

(1162) 0x4616b0 LDR	X1, [X19, #504]

(1162) 0x4616b4 ADD	X0, X3, X10,LSL #3

(1162) 0x4616b8 UBFM	X2, X8, #61, #60

(1162) 0x4616bc BL	404070

(1162) 0x4616c0 B	461638

(1162) 0x4616c4 LDR	D28, [X9]

(1162) 0x4616c8 MOVZ	X17, #8

(1162) 0x4616cc LDR	D27, [X6]

(1162) 0x4616d0 FMADD	D30, D28, D27, D30

(1162) 0x4616d4 B	461344

(1162) 0x4616d8 LDR	D5, [X5]

(1162) 0x4616dc FNMUL	D4, D5, D15

(1162) 0x4616e0 STR	D4, [X5], #8

(1162) 0x4616e4 B	461564

(1162) 0x4616e8 ADDS	W9, W6, #1

(1162) 0x4616ec CCMP	W27, W9, #0, #1

(1162) 0x4616f0 STR	W9, [X26, #360]

(1162) 0x4616f4 B.NE	461624

(1162) 0x4616f8 LDR	X27, [X19, #208]

(1162) 0x4616fc ORR	W6, WZR, W27

(1162) 0x461700 CMP	W9, #1

(1162) 0x461704 B.NE	4617d0

(1162) 0x461708 LDR	X25, [X19, #800]

(1162) 0x46170c ADD	X1, SP, #260

(1162) 0x461710 ADD	X0, SP, #256

(1162) 0x461714 ADD	X7, SP, #280

(1162) 0x461718 ADD	X5, SP, #272

(1162) 0x46171c STRB	W4, [SP, #256]

(1162) 0x461720 LDR	X6, [X19, #568]

(1162) 0x461724 ORR	X3, XZR, X22

(1162) 0x461728 ADD	X2, SP, #264

(1162) 0x46172c STR	X21, [SP, #16]

(1162) 0x461730 STR	W9, [SP, #160]

(1162) 0x461734 STP	X20, X25, [SP]

(1162) 0x461738 LDR	X4, [X19, #256]

(1162) 0x46173c STR	W27, [SP, #260]

(1162) 0x461740 STR	W27, [SP, #264]

(1162) 0x461744 STR	W27, [SP, #272]

(1162) 0x461748 STR	W9, [SP, #280]

(1162) 0x46174c STR	W9, [SP, #288]

(1162) 0x461750 STR	D14, [SP, #296]

(1162) 0x461754 STR	XZR, [SP, #304]

(1162) 0x461758 BL	404020

(1162) 0x46175c ORR	X2, XZR, X20

(1162) 0x461760 LDR	X20, [X19, #856]

(1162) 0x461764 ORR	X6, XZR, X21

(1162) 0x461768 ADD	X4, SP, #280

(1162) 0x46176c ADD	X1, SP, #272

(1162) 0x461770 LDR	X5, [X19, #800]

(1162) 0x461774 ADD	X0, SP, #264

(1162) 0x461778 LDR	X3, [X23, #24]

(1162) 0x46177c LDRSW	X8, [X20]

(1162) 0x461780 LDR	X23, [X28, #24]

(1162) 0x461784 LDR	X7, [X19, #256]

(1162) 0x461788 UBFM	X11, X8, #61, #60

(1162) 0x46178c LDR	W21, [SP, #160]

(1162) 0x461790 LDR	D29, [X5, X11]

(1162) 0x461794 FSUB	D30, D29, S14

(1162) 0x461798 STR	D30, [X5, X11]

(1162) 0x46179c LDR	D31, [X23]

(1162) 0x4617a0 STR	X22, [SP]

(1162) 0x4617a4 STR	W27, [SP, #264]

(1162) 0x4617a8 STR	W27, [SP, #272]

(1162) 0x4617ac STR	W21, [SP, #280]

(1162) 0x4617b0 STR	W21, [SP, #288]

(1162) 0x4617b4 FNEG	D0, D31

(1162) 0x4617b8 STR	W27, [SP, #296]

(1162) 0x4617bc STR	D0, [SP, #304]

(1162) 0x4617c0 BL	403df0

(1162) 0x4617c4 STR	WZR, [X26, #360]

(1162) 0x4617c8 B	461624

(1162) 0x4617cc LDR	W6, [X19, #208]

(1162) 0x4617d0 MOVZ	W4, #1

(1162) 0x4617d4 ADRP	X3,

(1162) 0x4617d8 STR	W6, [SP, #160]

(1162) 0x4617dc ADD	X0, X3, #2304

(1162) 0x4617e0 MOVZ	W2, #0

(1162) 0x4617e4 LDR	X27, [X24, #8]

(1162) 0x4617e8 MOVZ	W3, #0

(1162) 0x4617ec ORR	X1, XZR, X20

(1162) 0x4617f0 STR	W4, [SP, #304]

(1162) 0x4617f4 BL	404320

(1162) 0x4617f8 LDR	W8, [SP, #160]

(1162) 0x4617fc MOVZ	W9, #1

(1162) 0x461800 LDR	W24, [SP, #304]

(1162) 0x461804 CMP	W8, #256

(1162) 0x461808 CCMP	W24, #1, #4, #12

(1162) 0x46180c B.NE	461ac8

(1162) 0x461810 ORR	W24, WZR, W9

(1162) 0x461814 ORR	W1, WZR, W24

(1162) 0x461818 ADD	X0, SP, #184

(1162) 0x46181c STR	W8, [SP, #160]

(1162) 0x461820 BL	523240

(1162) 0x461824 ADD	X1, SP, #256

(1162) 0x461828 ADD	X24, X19, #736

(1162) 0x46182c LDR	W13, [X26, #360]

(1162) 0x461830 FMOV	D15, #1.0000000

(1162) 0x461834 ADD	X25, X19, #232

(1162) 0x461838 ADD	X2, SP, #260

(1162) 0x46183c STR	W27, [SP, #260]

(1162) 0x461840 LDR	W12, [SP, #160]

(1162) 0x461844 MOVZ	W11, #84

(1162) 0x461848 MOVZ	W10, #78

(1162) 0x46184c STP	X1, X20, [SP, #8]

(1162) 0x461850 ADD	X20, X19, #544

(1162) 0x461854 ORR	X5, XZR, X22

(1162) 0x461858 ADD	X7, SP, #252

(1162) 0x46185c ADD	X4, SP, #248

(1162) 0x461860 ADD	X3, SP, #244

(1162) 0x461864 ADD	X0, SP, #182

(1162) 0x461868 LDR	X15, [X24, #24]

(1162) 0x46186c ADD	X1, SP, #183

(1162) 0x461870 STR	W12, [SP, #160]

(1162) 0x461874 LDR	X14, [X25, #24]

(1162) 0x461878 STP	W13, W12, [SP, #240]

(1162) 0x46187c STP	W12, W12, [SP, #248]

(1162) 0x461880 STP	X15, X2, [SP, #24]

(1162) 0x461884 ADD	X2, SP, #240

(1162) 0x461888 STR	X14, [SP]

(1162) 0x46188c LDR	X6, [X20, #24]

(1162) 0x461890 STRB	W11, [SP, #182]

(1162) 0x461894 STRB	W10, [SP, #183]

(1162) 0x461898 STR	W12, [SP, #256]

(1162) 0x46189c STR	D15, [SP, #296]

(1162) 0x4618a0 STR	XZR, [SP, #304]

(1162) 0x4618a4 BL	4040c0

(1162) 0x4618a8 LDR	W17, [X26, #360]

(1162) 0x4618ac LDR	W30, [SP, #160]

(1162) 0x4618b0 CMP	W17, #0

(1162) 0x4618b4 B.LE	4619bc

(1162) 0x4618b8 ANDS	X16, X17, #4160

(1162) 0x4618bc LDR	X9, [X24, #24]

(1162) 0x4618c0 FMOV	D6, #1.0000000

(1162) 0x4618c4 SBFM	X18, X17, #0, #31

(1162) 0x4618c8 MOVZ	X0, #0

(1162) 0x4618cc LDR	X6, [X19, #720]

(1162) 0x4618d0 LDR	X7, [X19, #856]

(1162) 0x4618d4 B.EQ	461944

(1162) 0x4618d8 CMP	X16, #1

(1162) 0x4618dc B.EQ	461920

(1162) 0x4618e0 CMP	X16, #2

(1162) 0x4618e4 B.EQ	461904

(1162) 0x4618e8 LDRSW	X5, [X7]

(1162) 0x4618ec MOVZ	X0, #1

(1162) 0x4618f0 MADD	X4, X5, X6, XZR

(1162) 0x4618f4 ADD	X3, X9, X4,LSL #3

(1162) 0x4618f8 LDR	D7, [X3]

(1162) 0x4618fc FSUB	D27, D7, S6

(1162) 0x461900 STR	D27, [X3]

(1162) 0x461904 LDRSW	X8, [X7, X0,LSL #2]

(1162) 0x461908 MADD	X22, X8, X6, X0

(1162) 0x46190c ADD	X0, X0, #1

(1162) 0x461910 ADD	X11, X9, X22,LSL #3

(1162) 0x461914 LDR	D25, [X11]

(1162) 0x461918 FSUB	D16, D25, S6

(1162) 0x46191c STR	D16, [X11]

(1162) 0x461920 LDRSW	X10, [X7, X0,LSL #2]

(1162) 0x461924 MADD	X1, X10, X6, X0

(1162) 0x461928 ADD	X0, X0, #1

(1162) 0x46192c ADD	X2, X9, X1,LSL #3

(1162) 0x461930 LDR	D28, [X2]

(1162) 0x461934 FSUB	D24, D28, S6

(1162) 0x461938 STR	D24, [X2]

(1162) 0x46193c CMP	X18, X0

(1162) 0x461940 B.EQ	4619bc

  (1163) 0x461944 LDRSW	X15, [X7, X0,LSL #2]

  (1163) 0x461948 ADD	X14, X0, #1

  (1163) 0x46194c ADD	X12, X0, #3

  (1163) 0x461950 ADD	X13, X0, #2

  (1163) 0x461954 LDRSW	X16, [X7, X14,LSL #2]

  (1163) 0x461958 LDRSW	X3, [X7, X13,LSL #2]

  (1163) 0x46195c MADD	X5, X15, X6, X0

  (1163) 0x461960 ADD	X0, X0, #4

  (1163) 0x461964 LDRSW	X10, [X7, X12,LSL #2]

  (1163) 0x461968 MADD	X4, X16, X6, X14

  (1163) 0x46196c UBFM	X8, X5, #61, #60

  (1163) 0x461970 MADD	X11, X3, X6, X13

  (1163) 0x461974 LDR	D23, [X9, X8]

  (1163) 0x461978 UBFM	X22, X4, #61, #60

  (1163) 0x46197c MADD	X2, X10, X6, X12

  (1163) 0x461980 UBFM	X1, X11, #61, #60

  (1163) 0x461984 UBFM	X15, X2, #61, #60

  (1163) 0x461988 FSUB	D26, D23, S6

  (1163) 0x46198c STR	D26, [X9, X8]

  (1163) 0x461990 LDR	D22, [X9, X22]

  (1163) 0x461994 FSUB	D21, D22, S6

  (1163) 0x461998 STR	D21, [X9, X22]

  (1163) 0x46199c LDR	D20, [X9, X1]

  (1163) 0x4619a0 FSUB	D19, D20, S6

  (1163) 0x4619a4 STR	D19, [X9, X1]

  (1163) 0x4619a8 LDR	D18, [X9, X15]

  (1163) 0x4619ac FSUB	D14, D18, S6

  (1163) 0x4619b0 STR	D14, [X9, X15]

  (1163) 0x4619b4 CMP	X18, X0

  (1163) 0x4619b8 B.NE	461944

(1162) 0x4619bc LDR	X0, [X20, #24]

(1162) 0x4619c0 FMOV	D17, #1.0000000

(1162) 0x4619c4 ADD	X6, SP, #232

(1162) 0x4619c8 ADD	X18, SP, #236

(1162) 0x4619cc MOVZ	W9, #78

(1162) 0x4619d0 ADD	X5, SP, #280

(1162) 0x4619d4 STR	W30, [SP, #160]

(1162) 0x4619d8 LDR	X28, [X28, #24]

(1162) 0x4619dc ADD	X7, SP, #228

(1162) 0x4619e0 ADD	X4, SP, #224

(1162) 0x4619e4 ADD	X3, SP, #220

(1162) 0x4619e8 ADD	X2, SP, #216

(1162) 0x4619ec STRB	W9, [SP, #180]

(1162) 0x4619f0 ADD	X1, SP, #181

(1162) 0x4619f4 STRB	W9, [SP, #181]

(1162) 0x4619f8 STP	X21, X0, [SP, #16]

(1162) 0x4619fc ADD	X0, SP, #180

(1162) 0x461a00 STP	X28, X6, [SP]

(1162) 0x461a04 LDR	X6, [X23, #24]

(1162) 0x461a08 STR	X18, [SP, #32]

(1162) 0x461a0c STP	W30, W17, [SP, #216]

(1162) 0x461a10 STP	W17, W30, [SP, #224]

(1162) 0x461a14 STP	W27, W30, [SP, #232]

(1162) 0x461a18 STR	D17, [SP, #280]

(1162) 0x461a1c STR	XZR, [SP, #288]

(1162) 0x461a20 BL	4040c0

(1162) 0x461a24 LDR	X24, [X24, #24]

(1162) 0x461a28 ADD	X23, SP, #208

(1162) 0x461a2c ADD	X30, SP, #272

(1162) 0x461a30 FMOV	D29, #-1.0000000

(1162) 0x461a34 FMOV	D30, #1.0000000

(1162) 0x461a38 ADD	X21, SP, #212

(1162) 0x461a3c MOVZ	W17, #78

(1162) 0x461a40 LDR	X25, [X25, #24]

(1162) 0x461a44 ADD	X5, SP, #264

(1162) 0x461a48 ADD	X7, SP, #204

(1162) 0x461a4c ADD	X4, SP, #200

(1162) 0x461a50 ADD	X3, SP, #196

(1162) 0x461a54 STRB	W17, [SP, #178]

(1162) 0x461a58 LDR	W14, [SP, #160]

(1162) 0x461a5c ADD	X2, SP, #192

(1162) 0x461a60 ADD	X1, SP, #179

(1162) 0x461a64 STP	X24, X23, [SP]

(1162) 0x461a68 ADD	X0, SP, #178

(1162) 0x461a6c STP	X30, X25, [SP, #16]

(1162) 0x461a70 LDR	W12, [X26, #360]

(1162) 0x461a74 STRB	W17, [SP, #179]

(1162) 0x461a78 LDR	X6, [X20, #24]

(1162) 0x461a7c STR	X21, [SP, #32]

(1162) 0x461a80 STP	W14, W14, [SP, #192]

(1162) 0x461a84 STP	W12, W14, [SP, #200]

(1162) 0x461a88 STP	W27, W14, [SP, #208]

(1162) 0x461a8c STP	D29, D30, [SP, #264]

(1162) 0x461a90 BL	4040c0

(1162) 0x461a94 ADD	X0, SP, #184

(1162) 0x461a98 BL	523248

(1162) 0x461a9c STR	WZR, [X26, #360]

(1162) 0x461aa0 B	461624

0x461aa4 LDR	D5, [X7, X12]

0x461aa8 LDR	X6, [X19, #424]

0x461aac LDR	X15, [X26, #8]

0x461ab0 LDR	X14, [X19, #568]

0x461ab4 STR	D5, [X4, X13]

0x461ab8 LDR	D6, [X6]

0x461abc MADD	X16, X3, X15, XZR

0x461ac0 STR	D6, [X14, X16,LSL #3]

0x461ac4 B	46124c

(1162) 0x461ac8 STR	W8, [SP, #160]

(1162) 0x461acc BL	52324c

(1162) 0x461ad0 LDR	W8, [SP, #160]

(1162) 0x461ad4 TBNZ	W0, #0, 461814

(1162) 0x461ad8 ADRP	X22,

(1162) 0x461adc ORR	X1, XZR, X20

(1162) 0x461ae0 STP	X26, X25, [SP, #304]

(1162) 0x461ae4 ADD	X0, X22, #2348

(1162) 0x461ae8 MOVZ	W3, #0

(1162) 0x461aec MOVZ	W2, #0

(1162) 0x461af0 STR	W8, [SP, #320]

(1162) 0x461af4 STR	W27, [SP, #324]

(1162) 0x461af8 STR	W24, [SP, #328]

(1162) 0x461afc BL	404320

(1162) 0x461b00 STR	WZR, [X26, #360]

(1162) 0x461b04 B	461624

0x461b08 ORR	X19, XZR, X0

0x461b0c ADD	X0, SP, #184

0x461b10 BL	523248

0x461b14 ORR	X0, XZR, X19

0x461b18 BL	404160

0x461b1c HINT	#0

Coverage (%)	Name	Source Location	Module
►52.19+	qmcplusplus::WaveFunction::acc[...]	WaveFunction.cpp:223	exec
○	main._omp_fn.1	miniqmc.cpp:451	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►45.99+	qmcplusplus::WaveFunction::acc[...]	stl_vector.h:992	exec
○	main._omp_fn.1	miniqmc.cpp:451	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	DiracDeterminantRef.cpp:123-139
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1128-1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:53-54
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/OpenMP.h:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248-249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:123-139
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DeterminantHelper.h:23
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-452
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:128-149,160-196,230
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187,249,447
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,217,236

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.83 to 3.83 cycles (3.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.83 to 9.25 cycles (1.39x speedup).

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
7% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.83 to 3.00 cycles (4.28x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 192 bytes. The binary function is storing 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	82
loop length	328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	5.67	5.67	5.67	5.67	5.67	5.67	3.50	3.50	2.00	2.00	12.83	12.50	12.67	4.00	4.00
cycles	4.50	4.50	5.67	5.67	5.67	5.67	5.67	5.67	3.50	3.50	2.00	2.00	12.83	12.50	12.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.13
Overall L1	12.83

Vectorization ratios

INT

all	5%
load	7%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	7%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

15% of peak load performance is reached (14.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 461140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X1, <525148>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X0, #648	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X23, X0, #608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X25, X26, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X25, X0, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X0, #520	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X19, #1080]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D30, [X1, #3952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D15, D2, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR W0, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FABS D0, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W28, W2, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FCSEL D1, D31, D30, #12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D2, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X19, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
BL 403dc0 <@plt_start@+0xe0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D4, D15, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D4, [X19, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X2, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X27, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X3, [X19, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 46166c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X5, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
UBFM X21, X9, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X19, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X11, X5, X10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X8, X3, X6, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X12, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X7, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X4, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461aa4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 403d60 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDRSW X9, [X26, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X18, X9, X4, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X3, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403d60 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X3, [X26, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D5, [X7, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X6, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D5, [X4, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X3, X15, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR D6, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 46124c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, SP, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 523248 <_ZN11qmcplusplus16BlasThreadingEnvD1Ev>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404160 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	DiracDeterminantRef.cpp:123-139
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1128-1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:53-54
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/OpenMP.h:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,248-249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:123-139
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DeterminantHelper.h:23
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-452
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:128-149,160-196,230
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187,249,447
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,217,236

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.83 to 3.83 cycles (3.35x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

4% of VPU instructions are used in vector version (process two or more data elements in vector registers):

7% of VPU loads are used in vector version.
7% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.83 to 3.00 cycles (4.28x speedup).

Matching between your function (in the source code) and the binary function

The binary function is composed of 2 FP arithmetical operations:

2: addition or subtraction

The binary function is loading 192 bytes. The binary function is storing 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	82
loop length	328
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.13 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	5.67	5.67	5.67	5.67	5.67	5.67	3.50	3.50	2.00	2.00	12.83	12.50	12.67	4.00	4.00
cycles	4.50	4.50	5.67	5.67	5.67	5.67	5.67	5.67	3.50	3.50	2.00	2.00	12.83	12.50	12.67	4.00	4.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.13
Overall L1	12.83

Vectorization ratios

INT

all	5%
load	7%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	4%
load	7%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.83 cycles. At this rate:

15% of peak load performance is reached (14.96 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
25% of peak store performance is reached (12.47 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 461140

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVI D31, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADRP X1, <525148>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X23, X24, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X0, #648	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X23, X0, #608	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X25, X26, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X25, X0, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X26, X0, #520	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D0, [X19, #1080]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D30, [X1, #3952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D15, D2, [X19, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FCMPE D0, D31	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR W0, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FABS D0, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W28, W2, W0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FCSEL D1, D31, D30, #12	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FADD D3, D2, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STR D3, [X19, #24]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
BL 403dc0 <@plt_start@+0xe0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FADD D4, D15, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR X0, [X19, #1088]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D4, [X19, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
BL 4be880 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X2, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STR X2, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X27, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X4, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X3, [X19, #880]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 46166c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x52c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SBFM X5, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
UBFM X21, X9, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X10, [X25, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X19, #592]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X11, X5, X10, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
MADD X8, X3, X6, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
UBFM X12, X11, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, X7, X11,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, X4, X8,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM X13, X8, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X21, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 461aa4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 403d60 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X2, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDRSW X9, [X26, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X3, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X1, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X18, X9, X4, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X0, X3, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403d60 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDRSW X3, [X26, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D5, [X7, X12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X6, [X19, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X15, [X26, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D5, [X4, X13]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
LDR D6, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
MADD X16, X3, X15, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
STR D6, [X14, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 46124c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10acceptMoveERNS1_11ParticleSetEi+0x10c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X0, SP, #184	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 523248 <_ZN11qmcplusplus16BlasThreadingEnvD1Ev>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404160 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::acceptMove(qmcplusplus::ParticleSet&, int)–	0.01	0.01
▼Loop 1162 - OhmmsVector.h:223-249 - exec–	0.01	0.01
○Loop 1165 - DelayedUpdate.h:137-138 - exec	0.00	0.01
○Loop 1163 - DelayedUpdate.h:186-187 - exec	0.00	0.00
○Loop 1164 - DelayedUpdate.h:147-148 - exec	0.00	0.00

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