OV - exec - Function qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSet&)

	Function: qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSe ...	Module: exec	Source: SoaDistanceTableABOMPTarget.h:61-233 [...]	Coverage (incl. loops): 5.76% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

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242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 993 - 1131

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993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp: 46 - 46

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46:   return ((n + ND - 1) / ND) * ND;

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

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193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 149 - 248

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149:     if (nAllocated)

[...]

156:     nLocal     = n;

157:     nAllocated = 0;

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

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280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp: 78 - 79

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78:     free(p);

79:   }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp: 38 - 38

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38:   return a < b ? a : b;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 154 - 267

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154:     nAllocated = 0;

[...]

167:     if (nAllocated)

[...]

174:     nLocal  = n;

175:     nGhosts = n_padded;

176:     myData  = ptr;

[...]

267:   inline const T* data() const { return myData; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 61 - 233

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61:     if (num_sources_ * num_targets_ == 0)

62:       return;

63:     if (distances_.size())

64:       return;

65:

66:     // initialize memory containers and views

67:     const size_t num_padded  = getAlignedSize<T>(num_sources_);

68:     const size_t stride_size = getPerTargetPctlStrideSize();

69:     r_dr_memorypool_.resize(stride_size * num_targets_);

70:

71:     distances_.resize(num_targets_);

72:     displacements_.resize(num_targets_);

73:     for (int i = 0; i < num_targets_; ++i)

74:     {

75:       distances_[i].attachReference(r_dr_memorypool_.data() + i * stride_size, num_sources_);

76:       displacements_[i].attachReference(num_sources_, num_padded,

77:                                         r_dr_memorypool_.data() + i * stride_size + num_padded);

[...]

180:   size_t getPerTargetPctlStrideSize() const override { return getAlignedSize<T>(num_sources_) * (D + 1); }

181:

182:   /** evaluate the full table */

183:   inline void evaluate(ParticleSet& P) override

184:   {

185:     resize();

186:

187:     ScopedTimer local_timer(evaluate_timer_);

188:     // be aware of the sign of Displacement

189:     const int num_targets_local = num_targets_;

190:     const int num_sources_local = num_sources_;

191:     const int num_padded        = getAlignedSize<T>(num_sources_);

192:

193:     target_pos.resize(num_targets_ * D);

194:     for (size_t iat = 0; iat < num_targets_; iat++)

195:       for (size_t idim = 0; idim < D; idim++)

196:         target_pos[iat * D + idim] = P.R[iat][idim];

197:

198:     auto* target_pos_ptr = target_pos.data();

199:     auto* source_pos_ptr = origin_.getCoordinates().getAllParticlePos().data();

[...]

205:     const size_t num_teams     = (num_sources_ + ChunkSizePerTeam - 1) / ChunkSizePerTeam;

206:     const size_t stride_size   = getPerTargetPctlStrideSize();

207:

208:     {

209:       ScopedTimer offload(offload_timer_);

210:       PRAGMA_OFFLOAD("omp target teams distribute collapse(2) num_teams(num_targets_*num_teams) \

211:                         map(to: source_pos_ptr[:num_padded*D]) \

212:                         map(always, to: target_pos_ptr[:num_targets_*D]) \

213:                         map(always, from: r_dr_ptr[:num_targets_*stride_size])")

214:       for (int iat = 0; iat < num_targets_local; ++iat)

215:         for (int team_id = 0; team_id < num_teams; team_id++)

216:         {

217:           const int first = ChunkSizePerTeam * team_id;

218:           const int last  = omptarget::min(first + ChunkSizePerTeam, num_sources_local);

219:

220:           T pos[D];

221:           for (int idim = 0; idim < D; idim++)

222:             pos[idim] = target_pos_ptr[iat * D + idim];

223:

224:           auto* r_iat_ptr  = r_dr_ptr + iat * stride_size;

225:           auto* dr_iat_ptr = r_iat_ptr + num_padded;

226:

227:           PRAGMA_OFFLOAD("omp parallel for")

228:           for (int iel = first; iel < last; iel++)

229:             DTD_BConds<T, D, SC>::computeDistancesOffload(pos, source_pos_ptr, num_padded, r_iat_ptr, dr_iat_ptr,

230:                                                           num_padded, iel);

231:         }

232:     }

233:   }

0x5208e0 STP	X29, X30, [SP, #864]!

0x5208e4 ADD	X29, SP, #0

0x5208e8 STP	X19, X20, [SP, #16]

0x5208ec STP	X21, X22, [SP, #32]

0x5208f0 ORR	X22, XZR, X0

0x5208f4 STP	X23, X24, [SP, #48]

0x5208f8 STP	X25, X26, [SP, #64]

0x5208fc STP	X27, X28, [SP, #80]

0x520900 STP	D14, D15, [SP, #96]

0x520904 STR	X1, [SP, #120]

0x520908 LDP	X2, X1, [X0, #16]

0x52090c MADD	X3, X2, X1, XZR

0x520910 CBZ	X3, 520928

0x520914 LDR	X4, [X0, #72]

0x520918 ADD	X21, X0, #72

0x52091c LDR	X5, [X21, #8]

0x520920 CMP	X5, X4

0x520924 B.EQ	520d84

(3893) 0x520928 LDR	X20, [X22, #440]

(3893) 0x52092c ADD	X21, X22, #384

(3893) 0x520930 ORR	X0, XZR, X20

(3893) 0x520934 BL	4be880

(3893) 0x520938 LDP	X23, X26, [X22, #16]

(3893) 0x52093c MOVI	D0, #0

(3893) 0x520940 ORR	X0, XZR, X21

(3893) 0x520944 ADD	X8, X23, #3

(3893) 0x520948 ADD	X1, X26, X26,LSL #1

(3893) 0x52094c AND	X27, X8, #8062

(3893) 0x520950 BL	4ff380

(3893) 0x520954 LDR	X30, [X22, #24]

(3893) 0x520958 LDR	X25, [X21, #24]

(3893) 0x52095c CBZ	X30, 520b6c

(3893) 0x520960 ADD	X9, X30, X30,LSL #1

(3893) 0x520964 ORR	X10, XZR, #3841

(3893) 0x520968 ORR	X1, XZR, X25

(3893) 0x52096c LDR	X16, [SP, #120]

(3893) 0x520970 MOVK	X10, #43691

(3893) 0x520974 UBFM	X11, X9, #61, #60

(3893) 0x520978 MOVK	X10, #2730

(3893) 0x52097c SUB	X12, X11, #24

(3893) 0x520980 UBFM	X0, X12, #3, #63

(3893) 0x520984 LDR	X17, [X16, #64]

(3893) 0x520988 MADD	X13, X0, X10, XZR

(3893) 0x52098c ADD	X14, X13, #1

(3893) 0x520990 ANDS	X15, X14, #4224

(3893) 0x520994 ADD	X19, X17, X9,LSL #3

(3893) 0x520998 B.EQ	520a94

(3893) 0x52099c CMP	X15, #1

(3893) 0x5209a0 B.EQ	520a6c

(3893) 0x5209a4 CMP	X15, #2

(3893) 0x5209a8 B.EQ	520a4c

(3893) 0x5209ac CMP	X15, #3

(3893) 0x5209b0 B.EQ	520a2c

(3893) 0x5209b4 CMP	X15, #4

(3893) 0x5209b8 B.EQ	520a0c

(3893) 0x5209bc CMP	X15, #5

(3893) 0x5209c0 B.EQ	5209ec

(3893) 0x5209c4 CMP	X15, #6

(3893) 0x5209c8 B.NE	520f08

(3893) 0x5209cc LDR	D2, [X17]

(3893) 0x5209d0 ADD	X1, X1, #24

(3893) 0x5209d4 ADD	X17, X17, #24

(3893) 0x5209d8 STUR	D2, [X1, #488]

(3893) 0x5209dc LDUR	D3, [X17, #496]

(3893) 0x5209e0 STUR	D3, [X1, #496]

(3893) 0x5209e4 LDUR	D4, [X17, #504]

(3893) 0x5209e8 STUR	D4, [X1, #504]

(3893) 0x5209ec LDR	D5, [X17]

(3893) 0x5209f0 ADD	X1, X1, #24

(3893) 0x5209f4 ADD	X17, X17, #24

(3893) 0x5209f8 STUR	D5, [X1, #488]

(3893) 0x5209fc LDUR	D6, [X17, #496]

(3893) 0x520a00 STUR	D6, [X1, #496]

(3893) 0x520a04 LDUR	D7, [X17, #504]

(3893) 0x520a08 STUR	D7, [X1, #504]

(3893) 0x520a0c LDR	D14, [X17]

(3893) 0x520a10 ADD	X1, X1, #24

(3893) 0x520a14 ADD	X17, X17, #24

(3893) 0x520a18 STUR	D14, [X1, #488]

(3893) 0x520a1c LDUR	D15, [X17, #496]

(3893) 0x520a20 STUR	D15, [X1, #496]

(3893) 0x520a24 LDUR	D16, [X17, #504]

(3893) 0x520a28 STUR	D16, [X1, #504]

(3893) 0x520a2c LDR	D17, [X17]

(3893) 0x520a30 ADD	X1, X1, #24

(3893) 0x520a34 ADD	X17, X17, #24

(3893) 0x520a38 STUR	D17, [X1, #488]

(3893) 0x520a3c LDUR	D18, [X17, #496]

(3893) 0x520a40 STUR	D18, [X1, #496]

(3893) 0x520a44 LDUR	D19, [X17, #504]

(3893) 0x520a48 STUR	D19, [X1, #504]

(3893) 0x520a4c LDR	D20, [X17]

(3893) 0x520a50 ADD	X1, X1, #24

(3893) 0x520a54 ADD	X17, X17, #24

(3893) 0x520a58 STUR	D20, [X1, #488]

(3893) 0x520a5c LDUR	D21, [X17, #496]

(3893) 0x520a60 STUR	D21, [X1, #496]

(3893) 0x520a64 LDUR	D22, [X17, #504]

(3893) 0x520a68 STUR	D22, [X1, #504]

(3893) 0x520a6c LDR	D23, [X17]

(3893) 0x520a70 ADD	X17, X17, #24

(3893) 0x520a74 ADD	X1, X1, #24

(3893) 0x520a78 STUR	D23, [X1, #488]

(3893) 0x520a7c LDUR	D24, [X17, #496]

(3893) 0x520a80 STUR	D24, [X1, #496]

(3893) 0x520a84 LDUR	D25, [X17, #504]

(3893) 0x520a88 STUR	D25, [X1, #504]

(3893) 0x520a8c CMP	X19, X17

(3893) 0x520a90 B.EQ	520b6c

  (3900) 0x520a94 LDR	D26, [X17]

  (3900) 0x520a98 ORR	X28, XZR, X17

  (3900) 0x520a9c ORR	X24, XZR, X1

  (3900) 0x520aa0 ADD	X17, X17, #192

  (3900) 0x520aa4 ADD	X1, X1, #192

  (3900) 0x520aa8 STUR	D26, [X1, #320]

  (3900) 0x520aac LDUR	D27, [X17, #328]

  (3900) 0x520ab0 STUR	D27, [X1, #328]

  (3900) 0x520ab4 LDUR	D28, [X17, #336]

  (3900) 0x520ab8 STUR	D28, [X1, #336]

  (3900) 0x520abc LDUR	D29, [X17, #344]

  (3900) 0x520ac0 STUR	D29, [X1, #344]

  (3900) 0x520ac4 LDUR	D30, [X17, #352]

  (3900) 0x520ac8 STUR	D30, [X1, #352]

  (3900) 0x520acc LDUR	D31, [X17, #360]

  (3900) 0x520ad0 STUR	D31, [X1, #360]

  (3900) 0x520ad4 LDUR	D0, [X17, #368]

  (3900) 0x520ad8 STUR	D0, [X1, #368]

  (3900) 0x520adc LDUR	D1, [X17, #376]

  (3900) 0x520ae0 STUR	D1, [X1, #376]

  (3900) 0x520ae4 LDUR	D2, [X17, #384]

  (3900) 0x520ae8 STUR	D2, [X1, #384]

  (3900) 0x520aec LDUR	D3, [X17, #392]

  (3900) 0x520af0 STUR	D3, [X1, #392]

  (3900) 0x520af4 LDUR	D4, [X17, #400]

  (3900) 0x520af8 STUR	D4, [X1, #400]

  (3900) 0x520afc LDUR	D5, [X17, #408]

  (3900) 0x520b00 STUR	D5, [X1, #408]

  (3900) 0x520b04 LDUR	D6, [X17, #416]

  (3900) 0x520b08 STUR	D6, [X1, #416]

  (3900) 0x520b0c LDUR	D7, [X17, #424]

  (3900) 0x520b10 STUR	D7, [X1, #424]

  (3900) 0x520b14 LDUR	D14, [X17, #432]

  (3900) 0x520b18 STUR	D14, [X1, #432]

  (3900) 0x520b1c LDUR	D15, [X17, #440]

  (3900) 0x520b20 STUR	D15, [X1, #440]

  (3900) 0x520b24 LDUR	D16, [X17, #448]

  (3900) 0x520b28 STUR	D16, [X1, #448]

  (3900) 0x520b2c LDUR	D17, [X17, #456]

  (3900) 0x520b30 STUR	D17, [X1, #456]

  (3900) 0x520b34 LDUR	D18, [X17, #464]

  (3900) 0x520b38 STUR	D18, [X1, #464]

  (3900) 0x520b3c LDUR	D19, [X17, #472]

  (3900) 0x520b40 STUR	D19, [X1, #472]

  (3900) 0x520b44 LDUR	D20, [X17, #480]

  (3900) 0x520b48 STUR	D20, [X1, #480]

  (3900) 0x520b4c LDUR	D21, [X17, #488]

  (3900) 0x520b50 STUR	D21, [X1, #488]

  (3900) 0x520b54 LDR	D22, [X28, #176]

  (3900) 0x520b58 STR	D22, [X24, #176]

  (3900) 0x520b5c LDR	D23, [X28, #184]

  (3900) 0x520b60 STR	D23, [X24, #184]

  (3900) 0x520b64 CMP	X19, X17

  (3900) 0x520b68 B.NE	520a94

(3893) 0x520b6c LDR	X3, [X22, #8]

(3893) 0x520b70 ADRP	X18,

(3893) 0x520b74 ADD	X6, X18, #2816

(3893) 0x520b78 LDR	X0, [X3, #632]

(3893) 0x520b7c ORR	X4, XZR, X0

(3893) 0x520b80 LDR	X2, [X4], #64

(3893) 0x520b84 LDR	X5, [X2, #72]

(3893) 0x520b88 CMP	X5, X6

(3893) 0x520b8c B.NE	520efc

(3893) 0x520b90 LDR	X21, [X22]

(3893) 0x520b94 ADRP	X7,

(3893) 0x520b98 ADD	X8, X7, #1728

(3893) 0x520b9c LDR	X30, [X22, #16]

(3893) 0x520ba0 LDR	X9, [X22, #72]

(3893) 0x520ba4 LDR	X11, [X21, #136]

(3893) 0x520ba8 ADD	X10, X30, #511

(3893) 0x520bac LDR	X19, [X4, #24]

(3893) 0x520bb0 UBFM	X24, X10, #9, #63

(3893) 0x520bb4 LDR	X21, [X9, #24]

(3893) 0x520bb8 CMP	X11, X8

(3893) 0x520bbc B.NE	520eec

(3893) 0x520bc0 ADD	X0, X30, #3

(3893) 0x520bc4 AND	X13, X0, #8062

(3893) 0x520bc8 UBFM	X12, X13, #62, #61

(3893) 0x520bcc LDR	X28, [X22, #432]

(3893) 0x520bd0 STR	X12, [SP, #120]

(3893) 0x520bd4 ORR	X0, XZR, X28

(3893) 0x520bd8 BL	4be880

(3893) 0x520bdc CMP	W26, #0

(3893) 0x520be0 B.LE	520d54

(3893) 0x520be4 SBFM	X14, X27, #61, #31

(3893) 0x520be8 CBZ	X24, 520d54

(3893) 0x520bec LDR	X15, [SP, #120]

(3893) 0x520bf0 ADD	W26, W26, W26,LSL #1

(3893) 0x520bf4 ORR	X7, XZR, X21

(3893) 0x520bf8 MOVZ	W16, #0

(3893) 0x520bfc SBFM	X27, X27, #60, #30

(3893) 0x520c00 UBFM	X24, X24, #55, #54

(3893) 0x520c04 ADD	X8, X19, X14

(3893) 0x520c08 UBFM	X21, X15, #61, #60

  (3898) 0x520c0c ADD	W17, W16, #1

  (3898) 0x520c10 ADD	W1, W16, #2

  (3898) 0x520c14 ADD	X5, X7, X14,LSL #1

  (3898) 0x520c18 ADD	X18, X25, W16,UXTW #3

  (3898) 0x520c1c ADD	X9, X25, X17,LSL #3

  (3898) 0x520c20 MOVZ	X30, #0

  (3898) 0x520c24 ADD	X3, X14, X7

  (3898) 0x520c28 ADD	X11, X25, X1,LSL #3

  (3898) 0x520c2c ORR	X10, XZR, X27

    (3897) 0x520c30 ADD	W6, W30, #512

    (3897) 0x520c34 LDR	D29, [X11]

    (3897) 0x520c38 CMP	W6, W23

    (3897) 0x520c3c CSEL	W12, W6, W23, #13

    (3897) 0x520c40 LDR	D30, [X9]

    (3897) 0x520c44 LDR	D31, [X18]

    (3897) 0x520c48 CMP	W12, W30

    (3897) 0x520c4c B.LE	520d34

    (3897) 0x520c50 ADD	X4, X22, #200

    (3897) 0x520c54 ORR	X2, XZR, X10

    (3897) 0x520c58 LDR	D20, [X4, #136]

    (3897) 0x520c5c ORR	X0, XZR, X30

    (3897) 0x520c60 LDR	D19, [X22, #200]

    (3897) 0x520c64 LDP	D18, D17, [X4, #8]

    (3897) 0x520c68 LDP	D16, D7, [X4, #24]

    (3897) 0x520c6c LDP	D6, D5, [X4, #40]

    (3897) 0x520c70 LDP	D4, D3, [X4, #56]

    (3897) 0x520c74 LDP	D28, D27, [X4, #72]

    (3897) 0x520c78 LDP	D26, D25, [X4, #88]

    (3897) 0x520c7c LDP	D24, D23, [X4, #104]

    (3897) 0x520c80 LDP	D22, D21, [X4, #120]

      (3899) 0x520c84 LDR	D1, [X8, X0,LSL #3]

      (3899) 0x520c88 LDR	D2, [X19, X0,LSL #3]

      (3899) 0x520c8c LDR	D0, [X19, X2]

      (3899) 0x520c90 FSUB	D1, D1, S30

      (3899) 0x520c94 FSUB	D2, D2, S31

      (3899) 0x520c98 FSUB	D0, D0, S29

      (3899) 0x520c9c FMUL	D14, D1, D24

      (3899) 0x520ca0 FMUL	D15, D1, D27

      (3899) 0x520ca4 FMUL	D1, D1, D21

      (3899) 0x520ca8 FMADD	D14, D2, D25, D14

      (3899) 0x520cac FMADD	D15, D2, D28, D15

      (3899) 0x520cb0 FMADD	D1, D2, D22, D1

      (3899) 0x520cb4 FMADD	D14, D0, D23, D14

      (3899) 0x520cb8 FMADD	D15, D0, D26, D15

      (3899) 0x520cbc FRINTA	D2, D15

      (3899) 0x520cc0 FMADD	D1, D0, D20, D1

      (3899) 0x520cc4 FRINTA	D0, D14

      (3899) 0x520cc8 FSUB	D0, D14, S0

      (3899) 0x520ccc FSUB	D2, D15, S2

      (3899) 0x520cd0 FRINTA	D14, D1

      (3899) 0x520cd4 FSUB	D15, D1, S14

      (3899) 0x520cd8 FMUL	D14, D0, D18

      (3899) 0x520cdc FMUL	D1, D0, D7

      (3899) 0x520ce0 FMUL	D0, D0, D4

      (3899) 0x520ce4 FMADD	D14, D2, D19, D14

      (3899) 0x520ce8 FMADD	D1, D2, D16, D1

      (3899) 0x520cec FMADD	D2, D2, D5, D0

      (3899) 0x520cf0 FMADD	D14, D15, D17, D14

      (3899) 0x520cf4 FMADD	D1, D15, D6, D1

      (3899) 0x520cf8 FMADD	D15, D15, D3, D2

      (3899) 0x520cfc STR	D14, [X3, X0,LSL #3]

      (3899) 0x520d00 STR	D1, [X5, X0,LSL #3]

      (3899) 0x520d04 STR	D15, [X3, X2]

      (3899) 0x520d08 ADD	X2, X2, #8

      (3899) 0x520d0c LDR	D0, [X5, X0,LSL #3]

      (3899) 0x520d10 LDR	D2, [X3, X0,LSL #3]

      (3899) 0x520d14 FMUL	D14, D0, D0

      (3899) 0x520d18 FMADD	D1, D2, D2, D14

      (3899) 0x520d1c FMADD	D15, D15, D15, D1

      (3899) 0x520d20 FSQRT	D0, D15

      (3899) 0x520d24 STR	D0, [X7, X0,LSL #3]

      (3899) 0x520d28 ADD	X0, X0, #1

      (3899) 0x520d2c CMP	W12, W0

      (3899) 0x520d30 B.GT	520c84

    (3897) 0x520d34 ADD	X30, X30, #512

    (3897) 0x520d38 ADD	X10, X10, #1

    (3897) 0x520d3c CMP	X24, X30

    (3897) 0x520d40 B.NE	520c30

  (3898) 0x520d44 ADD	W16, W16, #3

  (3898) 0x520d48 ADD	X7, X7, X21

  (3898) 0x520d4c CMP	W26, W16

  (3898) 0x520d50 B.NE	520c0c

(3893) 0x520d54 ORR	X0, XZR, X28

(3893) 0x520d58 BL	4beb20

(3893) 0x520d5c ORR	X0, XZR, X20

(3893) 0x520d60 BL	4beb20

(3893) 0x520d64 LDP	D14, D15, [SP, #96]

(3893) 0x520d68 LDP	X19, X20, [SP, #16]

(3893) 0x520d6c LDP	X21, X22, [SP, #32]

(3893) 0x520d70 LDP	X23, X24, [SP, #48]

(3893) 0x520d74 LDP	X25, X26, [SP, #64]

(3893) 0x520d78 LDP	X27, X28, [SP, #80]

(3893) 0x520d7c LDP	X29, X30, [SP], #160

(3893) 0x520d80 RET

(3893) 0x520d84 LDR	X9, [X0]

(3893) 0x520d88 ADRP	X6,

(3893) 0x520d8c ADD	X7, X2, #3

(3893) 0x520d90 ADD	X8, X6, #1728

(3893) 0x520d94 AND	X23, X7, #8062

(3893) 0x520d98 LDR	X10, [X9, #136]

(3893) 0x520d9c CMP	X10, X8

(3893) 0x520da0 B.NE	520f2c

(3893) 0x520da4 UBFM	X19, X23, #62, #61

(3893) 0x520da8 ADD	X11, X22, #344

(3893) 0x520dac MOVI	D0, #0

(3893) 0x520db0 MADD	X1, X19, X1, XZR

(3893) 0x520db4 ORR	X0, XZR, X11

(3893) 0x520db8 STR	X11, [SP, #136]

(3893) 0x520dbc BL	4ff380

(3893) 0x520dc0 LDR	X1, [X22, #24]

(3893) 0x520dc4 ORR	X0, XZR, X21

(3893) 0x520dc8 BL	49c420

(3893) 0x520dcc ADD	X12, X22, #96

(3893) 0x520dd0 LDR	X1, [X22, #24]

(3893) 0x520dd4 ORR	X0, XZR, X12

(3893) 0x520dd8 STR	X12, [SP, #128]

(3893) 0x520ddc BL	4b2e00

(3893) 0x520de0 LDR	X0, [X22, #24]

(3893) 0x520de4 CBZ	X0, 520928

(3893) 0x520de8 LDP	X5, X4, [SP, #128]

(3893) 0x520dec MOVZ	X24, #0

(3893) 0x520df0 MOVZ	X26, #0

(3893) 0x520df4 UBFM	X2, X19, #61, #60

(3893) 0x520df8 UBFM	X6, X23, #61, #60

(3893) 0x520dfc MOVZ	W3, #40

  (3894) 0x520e00 UMADDL	X25, W26, W3, XZR

  (3894) 0x520e04 LDR	X13, [X21]

  (3894) 0x520e08 LDR	X15, [X4, #24]

  (3894) 0x520e0c LDR	X20, [X22, #16]

  (3894) 0x520e10 ADD	X19, X13, X25

  (3894) 0x520e14 LDR	X14, [X19, #16]

  (3894) 0x520e18 ADD	X28, X15, X24

  (3894) 0x520e1c CBNZ	X14, 520e84

  (3895) 0x520e20 LDR	X27, [X5]

  (3895) 0x520e24 ADD	X16, X6, X24

  (3895) 0x520e28 STR	X20, [X19, #8]

  (3895) 0x520e2c ADD	X20, X15, X16

  (3895) 0x520e30 STP	XZR, X28, [X19, #16]

  (3895) 0x520e34 ADD	X19, X27, X25

  (3895) 0x520e38 LDR	X28, [X22, #16]

  (3895) 0x520e3c LDR	X17, [X19, #16]

  (3895) 0x520e40 CBNZ	X17, 520ea8

  (3895) 0x520e44 STR	X28, [X27, X25]

  (3895) 0x520e48 ADD	X26, X26, #1

  (3895) 0x520e4c ADD	X24, X24, X2

  (3895) 0x520e50 STR	X23, [X19, #8]

  (3895) 0x520e54 LDR	X18, [X22, #24]

  (3895) 0x520e58 STR	X20, [X19, #24]

  (3895) 0x520e5c CMP	X18, X26

  (3895) 0x520e60 B.LS	520928

  (3895) 0x520e64 LDR	X13, [X21]

  (3895) 0x520e68 UMADDL	X25, W26, W3, XZR

  (3895) 0x520e6c LDR	X15, [X4, #24]

  (3895) 0x520e70 LDR	X20, [X22, #16]

  (3895) 0x520e74 ADD	X19, X13, X25

  (3895) 0x520e78 LDR	X14, [X19, #16]

  (3895) 0x520e7c ADD	X28, X15, X24

  (3895) 0x520e80 CBZ	X14, 520e20

    (3896) 0x520e84 LDR	X0, [X19, #24]

    (3896) 0x520e88 STP	X6, X2, [SP, #128]

    (3896) 0x520e8c STP	X5, X4, [SP, #144]

    (3896) 0x520e90 BL	4044a0

(3893) 0x520e94 LDP	X5, X4, [SP, #144]

(3893) 0x520e98 MOVZ	W3, #40

(3893) 0x520e9c LDP	X6, X2, [SP, #128]

(3893) 0x520ea0 LDR	X15, [X4, #24]

(3893) 0x520ea4 B	520e20

  (3894) 0x520ea8 LDR	X0, [X19, #24]

  (3894) 0x520eac ADD	X26, X26, #1

  (3894) 0x520eb0 STP	X6, X2, [SP, #128]

  (3894) 0x520eb4 STP	X5, X4, [SP, #144]

  (3894) 0x520eb8 BL	4044a0

  (3894) 0x520ebc LDP	X6, X2, [SP, #128]

  (3894) 0x520ec0 MOVZ	W3, #40

  (3894) 0x520ec4 LDP	X5, X4, [SP, #144]

  (3894) 0x520ec8 ADD	X24, X24, X2

  (3894) 0x520ecc STR	XZR, [X19, #16]

  (3894) 0x520ed0 STR	X28, [X27, X25]

  (3894) 0x520ed4 STR	X23, [X19, #8]

  (3894) 0x520ed8 LDR	X7, [X22, #24]

  (3894) 0x520edc STR	X20, [X19, #24]

  (3894) 0x520ee0 CMP	X26, X7

  (3894) 0x520ee4 B.CC	520e00

(3893) 0x520ee8 B	520928

(3893) 0x520eec ORR	X0, XZR, X22

(3893) 0x520ef0 BLR	X11

(3893) 0x520ef4 ORR	X12, XZR, X0

(3893) 0x520ef8 B	520bcc

(3893) 0x520efc BLR	X5

(3893) 0x520f00 ORR	X4, XZR, X0

(3893) 0x520f04 B	520b90

(3893) 0x520f08 LDR	D31, [X17]

(3893) 0x520f0c ADD	X1, X25, #24

(3893) 0x520f10 ADD	X17, X17, #24

(3893) 0x520f14 STR	D31, [X25]

(3893) 0x520f18 LDUR	D0, [X17, #496]

(3893) 0x520f1c STR	D0, [X25, #8]

(3893) 0x520f20 LDUR	D1, [X17, #504]

(3893) 0x520f24 STR	D1, [X25, #16]

(3893) 0x520f28 B	5209cc

(3893) 0x520f2c BLR	X10

(3893) 0x520f30 LDR	X1, [X22, #24]

(3893) 0x520f34 ORR	X19, XZR, X0

(3893) 0x520f38 B	520da8

0x520f3c ORR	X21, XZR, X0

0x520f40 ORR	X0, XZR, X20

0x520f44 BL	4beb20

0x520f48 ORR	X0, XZR, X21

0x520f4c BL	404160

0x520f50 HINT	#0

0x520f54 HINT	#0

0x520f58 HINT	#0

0x520f5c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.75+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	SoaDistanceTableABOMPTarget.h:61-233
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp:46
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:149,156-157,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:78-79
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:154,167,174-176,267
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:61-77,180-199,205-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.17 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 83% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 4.00 to 3.75 cycles (1.07x speedup).

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
12% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Overall L1	4.00

Vectorization ratios

all	8%
load	0%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5208e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X3, X2, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CBZ X3, 520928 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X0, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 520d84 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4beb20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404160 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_4

Source file and lines	SoaDistanceTableABOMPTarget.h:61-233
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp:46
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:149,156-157,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:78-79
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:154,167,174-176,267
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:61-77,180-199,205-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.17 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

8% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
12% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Overall L1	4.00

Vectorization ratios

all	8%
load	0%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 5208e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X3, X2, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CBZ X3, 520928 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X0, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 520d84 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x4a4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4beb20 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404160 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)–	5.76	7.95
▼Loop 3893 - SoaDistanceTableABOMPTarget.h:68-233 - exec–	0.00	0.01
○Loop 3900 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0.00	0.01
▼Loop 3898 - SoaDistanceTableABOMPTarget.h:214-228 - exec–	0.00	0.00
▼Loop 3897 - SoaDistanceTableABOMPTarget.h:215-228 - exec–	0.01	0.01
○Loop 3899 - SoaDistanceTableABOMPTarget.h:228-228 - exec	5.75	7.86
○Loop 3895 - OhmmsVector.h:149-248 - exec	0.00	0.00
▼Loop 3894 - SoaDistanceTableABOMPTarget.h:73-75 - exec–	0.00	0.00
○Loop 3896 - Mallocator.hpp:78-78 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code