OV - exec - Loop 352

	Loop Id: 352	Module: exec	Source: TwoBodyJastrowRef.h:342-347	Coverage: 0.23%

0x419744 LDP	Q3, Q4, [X18, #2032]    [1]

0x419748 LDP	Q5, Q6, [X0, #2032]    [2]

0x41974c ADD	X18, X18, #32

0x419750 SUBS	X4, X4, #4

0x419754 ADD	X0, X0, #32

0x419758 FMUL	V4.2D, V6.2D, V4.2D

0x41975c LDP	Q7, Q16, [X3, #2032]    [5]

0x419760 ADD	X3, X3, #32

0x419764 FMUL	V3.2D, V5.2D, V3.2D

0x419768 FADD	V2.2D, V4.2D, V2.2D

0x41976c LDP	Q5, Q6, [X2, #2032]    [4]

0x419770 ADD	X2, X2, #32

0x419774 FADD	V1.2D, V3.2D, V1.2D

0x419778 FMUL	V6.2D, V16.2D, V6.2D

0x41977c FMUL	V5.2D, V7.2D, V5.2D

0x419780 LDP	Q7, Q16, [X1, #2032]    [3]

0x419784 FSUB	V6.2D, V6.2D, V4.2D

0x419788 FSUB	V5.2D, V5.2D, V3.2D

0x41978c FADD	V6.2D, V6.2D, V16.2D

0x419790 FADD	V5.2D, V5.2D, V7.2D

0x419794 STP	Q5, Q6, [X1, #2032]    [3]

0x419798 ADD	X1, X1, #32

0x41979c B.NE	419744

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 342 - 347

--------------------------------------------------------------------------------

342:     for (int jat = 0; jat < N; jat++)

343:     {

344:       const valT newg = cur_du_pt[jat] * new_dX[jat];

345:       const valT dg   = newg - old_du_pt[jat] * old_dX[jat];

346:       save_g[jat] -= dg;

347:       cur_g += newg;

Coverage (%)	Name	Source Location	Module
►100.00+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	2.88
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.88
CQA cycles if fully vectorized	2.81
Front-end cycles	2.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.08
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.92
P7 cycles	0.92
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	2.75
P11 cycles	2.75
P12 cycles	2.17
P13 cycles	1.83
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	6.96
Nb FLOP add-sub	12.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	66.78
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	85.71
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	97.06
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	92.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.02
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	micro-operation queue,
Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source	TwoBodyJastrowRef.h:342-347
Source loop unroll info	unrolled by 4
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	4
CQA cycles	2.88
CQA cycles if no scalar integer	2.75
CQA cycles if FP arith vectorized	2.88
CQA cycles if fully vectorized	2.81
Front-end cycles	2.88
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	1.08
P3 cycles	1.08
P4 cycles	1.00
P5 cycles	1.00
P6 cycles	0.92
P7 cycles	0.92
P8 cycles	2.75
P9 cycles	2.75
P10 cycles	2.75
P11 cycles	2.75
P12 cycles	2.17
P13 cycles	1.83
P14 cycles	2.00
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	2
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	23.00
Nb uops	23.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	6.96
Nb FLOP add-sub	12.00
Nb FLOP mul	8.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	66.78
Bytes prefetched	0.00
Bytes loaded	160.00
Bytes stored	32.00
Stride 0	0.00
Stride 1	5.00
Stride n	0.00
Stride unknown	0.00
Stride indirect	0.00
Vectorization ratio all	94.12
Vectorization ratio load	100.00
Vectorization ratio store	100.00
Vectorization ratio mul	100.00
Vectorization ratio add_sub	85.71
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	97.06
Vector-efficiency ratio load	100.00
Vector-efficiency ratio store	100.00
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	92.86
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:342-347.

The related source loop is unrolled by 4 (including vectorization).

gain
potential
hint
expert

Vectorization

Your loop is highly vectorized. 97% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 2.88 to 2.81 cycles (1.02x speedup).

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

85% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

12: addition or subtraction
8: multiply

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00
cycles	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.88
Data deps.	2.00
Overall L1	2.88

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.88 cycles. At this rate:

57% of peak load performance is reached (55.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419744

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q3, Q4, [X18, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q5, Q6, [X0, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X4, X4, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V4.2D, V6.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q7, Q16, [X3, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X3, X3, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V3.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V2.2D, V4.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q5, Q6, [X2, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V1.2D, V3.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V6.2D, V16.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V5.2D, V7.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q7, Q16, [X1, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FSUB V6.2D, V6.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V5.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V6.2D, V6.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V5.2D, V5.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STP Q5, Q6, [X1, #2032]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.NE 419744 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x704>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::acceptMove(qmcplusplus::ParticleSet&, int)
Source file and lines	TwoBodyJastrowRef.h:342-347
Module	exec

gain
potential
hint
expert

Vectorization

Details

94% of VPU instructions are used in vector version (process two or more data elements in vector registers):

85% of VPU addition or subtraction instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

FMA

Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 20 FP arithmetical operations:

12: addition or subtraction
8: multiply

The binary loop is loading 160 bytes. The binary loop is storing 32 bytes.

Arithmetic intensity

Arithmetic intensity is 0.10 FP operations per loaded or stored byte.

General properties

nb instructions	23
loop length	92
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00
cycles	0.50	0.50	1.08	1.08	1.00	1.00	0.92	0.92	2.75	2.75	2.75	2.75	2.17	1.83	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	2.00

Cycles summary

Front-end	2.88
Data deps.	2.00
Overall L1	2.88

Vectorization ratios

INT

all	85%
load	100%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

all	100%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	94%
load	100%
store	100%
mul	100%
add-sub	85%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 2.88 cycles. At this rate:

57% of peak load performance is reached (55.65 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
23% of peak store performance is reached (11.13 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 419744

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q3, Q4, [X18, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q5, Q6, [X0, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X18, X18, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SUBS X4, X4, #4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
ADD X0, X0, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V4.2D, V6.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q7, Q16, [X3, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X3, X3, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V3.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V2.2D, V4.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q5, Q6, [X2, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ADD X2, X2, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FADD V1.2D, V3.2D, V1.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V6.2D, V16.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V5.2D, V7.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q7, Q16, [X1, #2032]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FSUB V6.2D, V6.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V5.2D, V5.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V6.2D, V6.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V5.2D, V5.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STP Q5, Q6, [X1, #2032]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	1	vect (100.0%)
ADD X1, X1, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
B.NE 419744 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE10acceptMoveERNS1_11ParticleSetEi+0x704>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

FMA

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code