OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:234-257	Coverage (incl. loops): 1.81% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 234 - 257

--------------------------------------------------------------------------------

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x4530e0 SUBS	W15, W6, W5

0x4530e4 B.LE	453318

0x4530e8 LDP	D0, D1, [X1]

0x4530ec LDR	D2, [X1, #16]

0x4530f0 LDR	X8, [X2, #24]

0x4530f4 ORR	W14, WZR, WZR

0x4530f8 LDR	X10, [X2, #8]

0x4530fc ADD	X9, X8, X10,LSL #3

0x453100 LDR	X11, [X4, #24]

0x453104 LDR	X13, [X4, #8]

0x453108 ADD	X10, X8, X10,LSL #4

0x45310c ADD	X12, X11, X13,LSL #3

0x453110 ADD	X13, X11, X13,LSL #4

0x453114 CMP	W15, #2

0x453118 B.CC	45323c

0x45311c SUB	W16, W6, #1

0x453120 CMP	W16, W5

0x453124 B.LT	45323c

0x453128 DUP	V3.2D, V0.D[0]

0x45312c DUP	V4.2D, V1.D[0]

0x453130 DUP	V5.2D, V2.D[0]

0x453134 AND	W14, W15, #1951

0x453138 ORR	W17, WZR, W5

0x45313c ORR	W16, WZR, W14

(1341) 0x453140 SBFM	X18, X17, #61, #31

(1341) 0x453144 LDUR	Q17, [X0, #72]

(1341) 0x453148 LDP	Q19, Q18, [X0, #80]

(1341) 0x45314c ADD	W17, W17, #2

(1341) 0x453150 SUBS	W16, W16, #2

(1341) 0x453154 LDR	Q6, [X8, X18]

(1341) 0x453158 LDR	Q7, [X9, X18]

(1341) 0x45315c LDR	Q16, [X10, X18]

(1341) 0x453160 FSUB	V6.2D, V6.2D, V3.2D

(1341) 0x453164 FSUB	V7.2D, V7.2D, V4.2D

(1341) 0x453168 FSUB	V16.2D, V16.2D, V5.2D

(1341) 0x45316c FMUL	V17.2D, V6.2D, V17.D[0]

(1341) 0x453170 FMUL	V18.2D, V6.2D, V18.D[0]

(1341) 0x453174 FMLA	V17.2D, V7.2D, V19.D[0]

(1341) 0x453178 LDUR	Q19, [X0, #104]

(1341) 0x45317c FMLA	V18.2D, V7.2D, V19.D[0]

(1341) 0x453180 LDUR	Q19, [X0, #88]

(1341) 0x453184 FMLA	V17.2D, V16.2D, V19.D[0]

(1341) 0x453188 LDR	Q19, [X0, #112]

(1341) 0x45318c FMLA	V18.2D, V16.2D, V19.D[0]

(1341) 0x453190 LDUR	Q19, [X0, #120]

(1341) 0x453194 FMUL	V6.2D, V6.2D, V19.D[0]

(1341) 0x453198 LDR	Q19, [X0, #128]

(1341) 0x45319c FMLA	V6.2D, V7.2D, V19.D[0]

(1341) 0x4531a0 LDR	D7, [X0, #136]

(1341) 0x4531a4 FMLA	V6.2D, V16.2D, V7.D[0]

(1341) 0x4531a8 FRINTA	V7.2D, V17.2D

(1341) 0x4531ac FRINTA	V16.2D, V18.2D

(1341) 0x4531b0 FSUB	V7.2D, V17.2D, V7.2D

(1341) 0x4531b4 FSUB	V16.2D, V18.2D, V16.2D

(1341) 0x4531b8 LDUR	Q18, [X0, #8]

(1341) 0x4531bc FRINTA	V17.2D, V6.2D

(1341) 0x4531c0 FSUB	V6.2D, V6.2D, V17.2D

(1341) 0x4531c4 LDR	Q17, [X0]

(1341) 0x4531c8 FMUL	V17.2D, V7.2D, V17.D[0]

(1341) 0x4531cc FMLA	V17.2D, V16.2D, V18.D[0]

(1341) 0x4531d0 LDR	Q18, [X0, #16]

(1341) 0x4531d4 FMLA	V17.2D, V6.2D, V18.D[0]

(1341) 0x4531d8 STR	Q17, [X11, X18]

(1341) 0x4531dc LDUR	Q17, [X0, #24]

(1341) 0x4531e0 LDR	Q18, [X0, #32]

(1341) 0x4531e4 FMUL	V17.2D, V7.2D, V17.D[0]

(1341) 0x4531e8 FMLA	V17.2D, V16.2D, V18.D[0]

(1341) 0x4531ec LDUR	Q18, [X0, #40]

(1341) 0x4531f0 FMLA	V17.2D, V6.2D, V18.D[0]

(1341) 0x4531f4 STR	Q17, [X12, X18]

(1341) 0x4531f8 LDR	Q17, [X0, #48]

(1341) 0x4531fc FMUL	V7.2D, V7.2D, V17.D[0]

(1341) 0x453200 LDUR	Q17, [X0, #56]

(1341) 0x453204 FMLA	V7.2D, V16.2D, V17.D[0]

(1341) 0x453208 LDR	Q16, [X0, #64]

(1341) 0x45320c FMLA	V7.2D, V6.2D, V16.D[0]

(1341) 0x453210 STR	Q7, [X13, X18]

(1341) 0x453214 LDR	Q6, [X11, X18]

(1341) 0x453218 LDR	Q16, [X12, X18]

(1341) 0x45321c FMUL	V6.2D, V6.2D, V6.2D

(1341) 0x453220 FMLA	V6.2D, V7.2D, V7.2D

(1341) 0x453224 FMLA	V6.2D, V16.2D, V16.2D

(1341) 0x453228 FSQRT	V6.2D, V6.2D

(1341) 0x45322c STR	Q6, [X3, X18]

(1341) 0x453230 B.NE	453140

0x453234 CMP	W15, W14

0x453238 B.EQ	453318

0x45323c ADD	W14, W14, W5

(1340) 0x453240 LDR	D3, [X8, X14,SXTW #3]

(1340) 0x453244 LDR	D4, [X9, X14,SXTW #3]

(1340) 0x453248 LDP	D6, D7, [X0, #72]

(1340) 0x45324c FSUB	D3, D3, S0

(1340) 0x453250 FSUB	D4, D4, S1

(1340) 0x453254 LDR	D5, [X10, X14,SXTW #3]

(1340) 0x453258 FSUB	D5, D5, S2

(1340) 0x45325c FMUL	D6, D6, D3

(1340) 0x453260 FMADD	D6, D7, D4, D6

(1340) 0x453264 LDP	D7, D16, [X0, #88]

(1340) 0x453268 FMADD	D6, D7, D5, D6

(1340) 0x45326c FMUL	D7, D16, D3

(1340) 0x453270 LDP	D16, D17, [X0, #104]

(1340) 0x453274 FMADD	D7, D16, D4, D7

(1340) 0x453278 FMADD	D7, D17, D5, D7

(1340) 0x45327c LDP	D16, D17, [X0, #120]

(1340) 0x453280 FMUL	D3, D16, D3

(1340) 0x453284 FMADD	D3, D17, D4, D3

(1340) 0x453288 LDR	D4, [X0, #136]

(1340) 0x45328c FMADD	D3, D4, D5, D3

(1340) 0x453290 FRINTA	D4, D6

(1340) 0x453294 FRINTA	D5, D7

(1340) 0x453298 FSUB	D4, D6, S4

(1340) 0x45329c FSUB	D5, D7, S5

(1340) 0x4532a0 FRINTA	D6, D3

(1340) 0x4532a4 FSUB	D3, D3, S6

(1340) 0x4532a8 LDP	D6, D7, [X0]

(1340) 0x4532ac FMUL	D6, D6, D4

(1340) 0x4532b0 FMADD	D6, D7, D5, D6

(1340) 0x4532b4 LDR	D7, [X0, #16]

(1340) 0x4532b8 FMADD	D6, D3, D7, D6

(1340) 0x4532bc STR	D6, [X11, X14,SXTW #3]

(1340) 0x4532c0 LDP	D6, D7, [X0, #24]

(1340) 0x4532c4 FMUL	D6, D6, D4

(1340) 0x4532c8 FMADD	D6, D7, D5, D6

(1340) 0x4532cc LDR	D7, [X0, #40]

(1340) 0x4532d0 FMADD	D6, D7, D3, D6

(1340) 0x4532d4 STR	D6, [X12, X14,SXTW #3]

(1340) 0x4532d8 LDP	D6, D7, [X0, #48]

(1340) 0x4532dc FMUL	D4, D6, D4

(1340) 0x4532e0 FMADD	D4, D7, D5, D4

(1340) 0x4532e4 LDR	D5, [X0, #64]

(1340) 0x4532e8 FMADD	D3, D5, D3, D4

(1340) 0x4532ec STR	D3, [X13, X14,SXTW #3]

(1340) 0x4532f0 LDR	D4, [X11, X14,SXTW #3]

(1340) 0x4532f4 LDR	D5, [X12, X14,SXTW #3]

(1340) 0x4532f8 FMUL	D4, D4, D4

(1340) 0x4532fc FMADD	D3, D3, D3, D4

(1340) 0x453300 FMADD	D3, D5, D5, D3

(1340) 0x453304 FSQRT	D3, D3

(1340) 0x453308 STR	D3, [X3, X14,SXTW #3]

(1340) 0x45330c ADD	W14, W14, #1

(1340) 0x453310 CMP	W6, W14

(1340) 0x453314 B.NE	453240

0x453318 RET

0x45331c HINT	#0

Coverage (%)	Name	Source Location	Module
►95.60+	qmcplusplus::ParticleSet::comp[...]	stl_vector.h:993	exec
○	main.omp_outlined.63	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so
►4.40+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	ParticleBConds3DSoa.h:234-257
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 2.50 cycles (1.40x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00
cycles	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.50

Vectorization ratios

all	20%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4530e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUBS W15, W6, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 453318 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W14, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X9, X8, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X8, X10,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X11, X13,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, X13,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 45323c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W16, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 45323c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V4.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V5.2D, V2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND W14, W15, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W17, WZR, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W16, WZR, W14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W15, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 453318 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	ParticleBConds3DSoa.h:234-257
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00
cycles	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.50

Vectorization ratios

all	20%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4530e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUBS W15, W6, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 453318 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W14, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X9, X8, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X8, X10,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X11, X13,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, X13,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 45323c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W16, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 45323c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V4.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V5.2D, V2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND W14, W15, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W17, WZR, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W16, WZR, W14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W15, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 453318 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	1.81	2.50
○Loop 1341 - ParticleBConds3DSoa.h:234-255 - exec	1.81	2.48
○Loop 1340 - ParticleBConds3DSoa.h:234-255 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code