OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::recompute(qmcplusplus::ParticleSet&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::recompute(qmcpl ...	Module: exec	Source: TwoBodyJastrowRef.h:268-402 [...]	Coverage (incl. loops): 0.09% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h: 952 - 1146

--------------------------------------------------------------------------------

952: 	*__first = __tmp;

[...]

1146:       if (__n <= 0)

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_iterator.h: 1068 - 1068

--------------------------------------------------------------------------------

1068:       : _M_current(__i) { }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 268 - 402

--------------------------------------------------------------------------------

268:   const int igt = P.GroupID[iat] * NumGroups;

269:   for (int jg = 0; jg < NumGroups; ++jg)

270:   {

271:     const FuncType& f2(*F[igt + jg]);

272:     int iStart = P.first(jg);

273:     int iEnd   = std::min(jelmax, P.last(jg));

274:     f2.evaluateVGL(iat, iStart, iEnd, dist, u, du, d2u, DistCompressed.data(), DistIndice.data());

[...]

359: {

360:   const auto& d_table = P.getDistTableAA(myTableID);

361:   for (int ig = 0; ig < NumGroups; ++ig)

362:   {

363:     const int igt = ig * NumGroups;

364:     for (int iat = P.first(ig), last = P.last(ig); iat < last; ++iat)

365:     {

366:       computeU3(P, iat, d_table.getDistRow(iat).data(), cur_u.data(), cur_du.data(), cur_d2u.data(), true);

367:       Uat[iat] = std::accumulate(cur_u.begin(), cur_u.begin() + iat, valT());

[...]

375:       for (int jat = 0; jat < iat; ++jat)

376:         lap += d2u[jat] + lapfac * du[jat];

377:       for (int idim = 0; idim < OHMMS_DIM; ++idim)

378:       {

379:         const valT* restrict dX = displ.data(idim);

380:         valT s                  = valT();

381:         for (int jat = 0; jat < iat; ++jat)

382:           s += du[jat] * dX[jat];

383:         grad[idim] = s;

384:       }

385:       dUat(iat)  = grad;

386:       d2Uat[iat] = -lap;

387:       // add the contribution from the upper triangle

388:       for (int jat = 0; jat < iat; jat++)

389:       {

390:         Uat[jat] += u[jat];

391:         d2Uat[jat] -= d2u[jat] + lapfac * du[jat];

[...]

397:         for (int jat = 0; jat < iat; jat++)

398:           save_g[jat] -= du[jat] * dX[jat];

399:       }

400:     }

401:   }

402: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 313

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h: 1131 - 1263

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1150: 	return *(this->_M_impl._M_start + __n);

[...]

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 244 - 273

--------------------------------------------------------------------------------

244:         *(_base + M * i) = rhs[i];

[...]

263:   inline Accessor operator()(size_t i) { return Accessor(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

272:   ///return the const pointer of the i-th components

273:   inline const T* restrict data(size_t i) const { return myData + i * nGhosts; }

0x419f20 SUB	SP, SP, #208

0x419f24 STR	D8, [SP, #96]

0x419f28 STP	X29, X30, [SP, #112]

0x419f2c STP	X28, X27, [SP, #128]

0x419f30 STP	X26, X25, [SP, #144]

0x419f34 STP	X24, X23, [SP, #160]

0x419f38 STP	X22, X21, [SP, #176]

0x419f3c STP	X20, X19, [SP, #192]

0x419f40 ADD	X29, SP, #112

0x419f44 ORR	X19, XZR, X1

0x419f48 LDR	W1, [X0, #584]

0x419f4c ORR	X20, XZR, X0

0x419f50 ORR	X0, XZR, X19

0x419f54 BL	447670

0x419f58 LDR	X28, [X20, #160]

0x419f5c CBZ	X28, 41ab10

0x419f60 FMOV	D8, #-2.0000000

0x419f64 MOVZ	W6, #40

0x419f68 ORR	X30, XZR, X19

0x419f6c ORR	X21, XZR, X0

0x419f70 ORR	X9, XZR, XZR

0x419f74 STUR	X28, [X29, #464]

0x419f78 STR	X0, [SP, #32]

0x419f7c STUR	X19, [X29, #504]

0x419f80 B	419f9c

      (366) 0x419f84 LDUR	X8, [X29, #464]

      (366) 0x419f88 LDR	X9, [SP, #16]

      (366) 0x419f8c STUR	X8, [X29, #464]

      (366) 0x419f90 ADD	X9, X9, #1

      (366) 0x419f94 CMP	X8, X9

      (366) 0x419f98 B.LS	41ab10

      (366) 0x419f9c LDR	X8, [X30, #616]

      (366) 0x419fa0 STR	X9, [SP, #16]

      (366) 0x419fa4 LDR	X8, [X8, #24]

      (366) 0x419fa8 ADD	X8, X8, X9,LSL #2

      (366) 0x419fac LDP	W27, W8, [X8]

      (366) 0x419fb0 STR	W8, [SP, #52]

      (366) 0x419fb4 CMP	W27, W8

      (366) 0x419fb8 B.GE	419f84

    (368) 0x419fbc LDR	X22, [X20, #320]

    (368) 0x419fc0 LDR	X24, [X20, #344]

    (368) 0x419fc4 LDR	X25, [X20, #368]

    (368) 0x419fc8 MOVN	X8, #57344

    (368) 0x419fcc SBFM	X23, X27, #0, #31

    (368) 0x419fd0 ORR	X19, XZR, XZR

    (368) 0x419fd4 ADD	X9, X8, W27,SXTW

    (368) 0x419fd8 STUR	WZR, [X29, #492]

    (368) 0x419fdc ORR	W8, WZR, W27

    (368) 0x419fe0 STR	X23, [SP, #24]

    (368) 0x419fe4 STR	X27, [SP, #40]

    (368) 0x419fe8 STP	X9, X8, [X29, #984]

    (368) 0x419fec B	41a034

0x419ff0 HINT	#0

0x419ff4 HINT	#0

0x419ff8 HINT	#0

0x419ffc HINT	#0

    (368) 0x41a000 LDUR	W9, [X29, #492]

    (368) 0x41a004 ADD	W8, W8, #1

    (368) 0x41a008 ADD	X23, X23, #1

    (368) 0x41a00c ADD	X19, X19, #1

    (368) 0x41a010 ADD	W9, W9, #1

    (368) 0x41a014 STUR	W9, [X29, #492]

    (368) 0x41a018 LDUR	X9, [X29, #472]

    (368) 0x41a01c ADD	X9, X9, #1

    (368) 0x41a020 STP	X9, X8, [X29, #984]

    (368) 0x41a024 LDR	W9, [SP, #52]

    (368) 0x41a028 ORR	X8, XZR, X28

    (368) 0x41a02c CMP	W9, W23

    (368) 0x41a030 B.EQ	419f88

    (368) 0x41a034 LDR	X8, [X21, #72]

    (368) 0x41a038 UBFM	X26, X23, #61, #60

    (368) 0x41a03c STR	X19, [SP, #56]

    (368) 0x41a040 MADD	X8, X23, X6, X8

    (368) 0x41a044 LDR	X27, [X8, #24]

    (368) 0x41a048 CMP	X23, #1

    (368) 0x41a04c B.LT	41a088

    (368) 0x41a050 ORR	X0, XZR, X22

    (368) 0x41a054 ORR	W1, WZR, WZR

    (368) 0x41a058 ORR	X2, XZR, X26

    (368) 0x41a05c BL	4049f0

    (368) 0x41a060 ORR	X0, XZR, X24

    (368) 0x41a064 ORR	W1, WZR, WZR

    (368) 0x41a068 ORR	X2, XZR, X26

    (368) 0x41a06c BL	4049f0

    (368) 0x41a070 ORR	X0, XZR, X25

    (368) 0x41a074 ORR	W1, WZR, WZR

    (368) 0x41a078 ORR	X2, XZR, X26

    (368) 0x41a07c BL	4049f0

    (368) 0x41a080 LDUR	X30, [X29, #504]

    (368) 0x41a084 MOVZ	W6, #40

    (368) 0x41a088 LDUR	X9, [X29, #464]

    (368) 0x41a08c CBZ	X9, 41a1c0

    (368) 0x41a090 LDR	X8, [X30, #24]

    (368) 0x41a094 ORR	X19, XZR, X26

    (368) 0x41a098 ORR	X21, XZR, XZR

    (368) 0x41a09c LDR	W8, [X8, X23,LSL #2]

    (368) 0x41a0a0 MADD	W8, W8, W9, WZR

    (368) 0x41a0a4 SBFM	X26, X8, #61, #31

      (373) 0x41a0a8 LDR	X8, [X20, #512]

      (373) 0x41a0ac LDR	X9, [X20, #488]

      (373) 0x41a0b0 ORR	W1, WZR, W23

      (373) 0x41a0b4 ORR	X4, XZR, X27

      (373) 0x41a0b8 ORR	X5, XZR, X22

      (373) 0x41a0bc ORR	X6, XZR, X24

      (373) 0x41a0c0 ORR	X7, XZR, X25

      (373) 0x41a0c4 ADD	X8, X8, X26

      (373) 0x41a0c8 LDR	X0, [X8, X21,LSL #3]

      (373) 0x41a0cc LDR	X8, [X30, #616]

      (373) 0x41a0d0 LDR	X8, [X8, #24]

      (373) 0x41a0d4 ADD	X8, X8, X21,LSL #2

      (373) 0x41a0d8 LDP	W2, W8, [X8]

      (373) 0x41a0dc CMP	W8, W23

      (373) 0x41a0e0 CSEL	W3, W8, W23, #11

      (373) 0x41a0e4 LDR	X8, [X20, #464]

      (373) 0x41a0e8 STP	X8, X9, [SP]

      (373) 0x41a0ec BL	416ec0

      (373) 0x41a0f0 LDUR	X30, [X29, #504]

      (373) 0x41a0f4 LDR	X28, [X20, #160]

      (373) 0x41a0f8 ADD	X21, X21, #1

      (373) 0x41a0fc CMP	X28, X21

      (373) 0x41a100 B.HI	41a0a8

    (368) 0x41a104 LDR	X22, [X20, #320]

    (368) 0x41a108 LDP	X21, X27, [SP, #32]

    (368) 0x41a10c MOVZ	W6, #40

    (368) 0x41a110 ORR	X26, XZR, X19

    (368) 0x41a114 STUR	X28, [X29, #464]

    (368) 0x41a118 CBZ	X23, 41a1cc

    (368) 0x41a11c LDR	X19, [SP, #56]

    (368) 0x41a120 LDR	X8, [SP, #24]

    (368) 0x41a124 MOVI	D0, #0

    (368) 0x41a128 ADD	X8, X19, X8

    (368) 0x41a12c SUB	X8, X8, #1

    (368) 0x41a130 AND	X9, X8, #7936

    (368) 0x41a134 ORR	X8, XZR, X22

    (368) 0x41a138 CMP	X9, #3

    (368) 0x41a13c B.CC	41a190

    (368) 0x41a140 LDUR	X8, [X29, #472]

    (368) 0x41a144 ADD	X9, X9, #1

    (368) 0x41a148 ADD	X12, X22, #16

    (368) 0x41a14c MOVI	V0.2D, #0

    (368) 0x41a150 MOVI	V1.2D, #0

    (368) 0x41a154 AND	X10, X9, #7934

    (368) 0x41a158 AND	X8, X8, #7936

    (368) 0x41a15c ADD	X8, X8, #1

    (368) 0x41a160 AND	X11, X8, #7934

    (368) 0x41a164 ADD	X8, X22, X10,LSL #3

      (372) 0x41a168 LDP	Q2, Q3, [X12, #2032]

      (372) 0x41a16c ADD	X12, X12, #32

      (372) 0x41a170 SUBS	X11, X11, #4

      (372) 0x41a174 FADD	V1.2D, V3.2D, V1.2D

      (372) 0x41a178 FADD	V0.2D, V2.2D, V0.2D

      (372) 0x41a17c B.NE	41a168

    (368) 0x41a180 FADD	V0.2D, V1.2D, V0.2D

    (368) 0x41a184 FADDP	D0, V0.2D

    (368) 0x41a188 CMP	X9, X10

    (368) 0x41a18c B.EQ	41a1d4

    (368) 0x41a190 ADD	X9, X22, X23,LSL #3

    (368) 0x41a194 HINT	#0

    (368) 0x41a198 HINT	#0

    (368) 0x41a19c HINT	#0

      (367) 0x41a1a0 LDR	D1, [X8], #8

      (367) 0x41a1a4 FADD	D0, D1, D0

      (367) 0x41a1a8 CMP	X8, X9

      (367) 0x41a1ac B.NE	41a1a0

    (368) 0x41a1b0 B	41a1d4

0x41a1b4 HINT	#0

0x41a1b8 HINT	#0

0x41a1bc HINT	#0

    (368) 0x41a1c0 LDR	X27, [SP, #40]

    (368) 0x41a1c4 STUR	XZR, [X29, #464]

    (368) 0x41a1c8 CBNZ	X23, 41a11c

    (368) 0x41a1cc LDR	X19, [SP, #56]

    (368) 0x41a1d0 MOVI	D0, #0

    (368) 0x41a1d4 LDR	X11, [X21, #96]

    (368) 0x41a1d8 LDUR	X8, [X29, #480]

    (368) 0x41a1dc LDUR	W9, [X29, #492]

    (368) 0x41a1e0 MADD	X12, X23, X6, X11

    (368) 0x41a1e4 LDR	X16, [X20, #216]

    (368) 0x41a1e8 LDR	X24, [X20, #344]

    (368) 0x41a1ec LDR	X25, [X20, #368]

    (368) 0x41a1f0 ORR	W8, WZR, W8

    (368) 0x41a1f4 AND	X10, X8, #6014

    (368) 0x41a1f8 ADD	W9, W27, W9

    (368) 0x41a1fc STR	D0, [X16, X23,LSL #3]

    (368) 0x41a200 CMP	X23, #0

    (368) 0x41a204 B.LE	41a220

  (371) 0x41a208 CMP	W9, #3

  (371) 0x41a20c B.HI	41a240

  (371) 0x41a210 MOVI	D0, #0

  (371) 0x41a214 ORR	X11, XZR, XZR

  (371) 0x41a218 B	41a2a0

0x41a21c HINT	#0

    (368) 0x41a220 LDR	X11, [X12, #24]

    (368) 0x41a224 LDR	X12, [X12, #8]

    (368) 0x41a228 MOVI	D0, #0

    (368) 0x41a22c B	41a2ec

0x41a230 HINT	#0

0x41a234 HINT	#0

0x41a238 HINT	#0

0x41a23c HINT	#0

(369) 0x41a240 AND	X11, X9, #6014

(369) 0x41a244 ADD	X13, X25, #16

(369) 0x41a248 ADD	X14, X24, #16

(369) 0x41a24c MOVI	V0.2D, #0

(369) 0x41a250 ORR	X15, XZR, X10

(369) 0x41a254 MOVI	V1.2D, #0

(369) 0x41a258 HINT	#0

(369) 0x41a25c HINT	#0

  (365) 0x41a260 LDP	Q2, Q3, [X13, #2032]

  (365) 0x41a264 LDP	Q4, Q5, [X14, #2032]

  (365) 0x41a268 ADD	X13, X13, #32

  (365) 0x41a26c ADD	X14, X14, #32

  (365) 0x41a270 SUBS	X15, X15, #4

  (365) 0x41a274 FADD	V5.2D, V5.2D, V5.2D

  (365) 0x41a278 FADD	V1.2D, V3.2D, V1.2D

  (365) 0x41a27c FADD	V4.2D, V4.2D, V4.2D

  (365) 0x41a280 FADD	V0.2D, V2.2D, V0.2D

  (365) 0x41a284 FADD	V1.2D, V1.2D, V5.2D

  (365) 0x41a288 FADD	V0.2D, V0.2D, V4.2D

  (365) 0x41a28c B.NE	41a260

(369) 0x41a290 FADD	V0.2D, V1.2D, V0.2D

(369) 0x41a294 FADDP	D0, V0.2D

(369) 0x41a298 CMP	X11, X9

(369) 0x41a29c B.EQ	41a2c8

  (371) 0x41a2a0 ADD	X13, X24, X11,LSL #3

  (371) 0x41a2a4 ADD	X14, X25, X11,LSL #3

  (371) 0x41a2a8 SUB	X11, X8, X11

    (370) 0x41a2ac LDR	D1, [X14], #8

    (370) 0x41a2b0 LDR	D2, [X13], #8

    (370) 0x41a2b4 SUBS	X11, X11, #1

    (370) 0x41a2b8 FADD	D2, D2, D2

    (370) 0x41a2bc FADD	D0, D1, D0

    (370) 0x41a2c0 FADD	D0, D0, D2

    (370) 0x41a2c4 B.NE	41a2ac

  (371) 0x41a2c8 LDR	X11, [X12, #24]

  (371) 0x41a2cc LDR	X12, [X12, #8]

  (371) 0x41a2d0 CMP	X23, #1

  (371) 0x41a2d4 B.LT	41a2ec

  (371) 0x41a2d8 CMP	W9, #4

  (371) 0x41a2dc B.CS	41a2fc

  (371) 0x41a2e0 ORR	X13, XZR, XZR

  (371) 0x41a2e4 MOVI	D1, #0

  (371) 0x41a2e8 B	41a350

    (368) 0x41a2ec MOVI	D1, #0

    (368) 0x41a2f0 MOVI	D2, #0

    (368) 0x41a2f4 MOVI	D3, #0

    (368) 0x41a2f8 B	41a498

  (371) 0x41a2fc AND	X13, X9, #6014

  (371) 0x41a300 ADD	X14, X24, #16

  (371) 0x41a304 ADD	X15, X11, #16

  (371) 0x41a308 MOVI	V1.2D, #0

  (371) 0x41a30c ORR	X17, XZR, X10

  (371) 0x41a310 MOVI	V2.2D, #0

  (371) 0x41a314 HINT	#0

  (371) 0x41a318 HINT	#0

  (371) 0x41a31c HINT	#0

    (385) 0x41a320 LDP	Q3, Q4, [X14, #2032]

    (385) 0x41a324 LDP	Q5, Q6, [X15, #2032]

    (385) 0x41a328 ADD	X14, X14, #32

    (385) 0x41a32c ADD	X15, X15, #32

    (385) 0x41a330 SUBS	X17, X17, #4

    (385) 0x41a334 FMLA	V2.2D, V6.2D, V4.2D

    (385) 0x41a338 FMLA	V1.2D, V5.2D, V3.2D

    (385) 0x41a33c B.NE	41a320

  (371) 0x41a340 FADD	V1.2D, V2.2D, V1.2D

  (371) 0x41a344 FADDP	D1, V1.2D

  (371) 0x41a348 CMP	X13, X9

  (371) 0x41a34c B.EQ	41a374

  (371) 0x41a350 ADD	X14, X24, X13,LSL #3

  (371) 0x41a354 ADD	X15, X11, X13,LSL #3

  (371) 0x41a358 SUB	X13, X8, X13

  (371) 0x41a35c HINT	#0

    (390) 0x41a360 LDR	D2, [X14], #8

    (390) 0x41a364 LDR	D3, [X15], #8

    (390) 0x41a368 SUBS	X13, X13, #1

    (390) 0x41a36c FMADD	D1, D3, D2, D1

    (390) 0x41a370 B.NE	41a360

  (371) 0x41a374 CMP	W9, #4

  (371) 0x41a378 B.CS	41a388

  (371) 0x41a37c ORR	X13, XZR, XZR

  (371) 0x41a380 MOVI	D2, #0

  (371) 0x41a384 B	41a3d4

  (371) 0x41a388 ADD	X15, X11, X12,LSL #3

  (371) 0x41a38c AND	X13, X9, #6014

  (371) 0x41a390 ADD	X14, X24, #16

  (371) 0x41a394 MOVI	V2.2D, #0

  (371) 0x41a398 ORR	X17, XZR, X10

  (371) 0x41a39c MOVI	V3.2D, #0

  (371) 0x41a3a0 ADD	X15, X15, #16

    (386) 0x41a3a4 LDP	Q4, Q5, [X14, #2032]

    (386) 0x41a3a8 LDP	Q6, Q7, [X15, #2032]

    (386) 0x41a3ac ADD	X14, X14, #32

    (386) 0x41a3b0 ADD	X15, X15, #32

    (386) 0x41a3b4 SUBS	X17, X17, #4

    (386) 0x41a3b8 FMLA	V3.2D, V7.2D, V5.2D

    (386) 0x41a3bc FMLA	V2.2D, V6.2D, V4.2D

    (386) 0x41a3c0 B.NE	41a3a4

  (371) 0x41a3c4 FADD	V2.2D, V3.2D, V2.2D

  (371) 0x41a3c8 FADDP	D2, V2.2D

  (371) 0x41a3cc CMP	X13, X9

  (371) 0x41a3d0 B.EQ	41a3fc

  (371) 0x41a3d4 UBFM	X15, X13, #61, #60

  (371) 0x41a3d8 SUB	X14, X8, X13

  (371) 0x41a3dc ADD	X13, X24, X13,LSL #3

  (371) 0x41a3e0 ADD	X15, X15, X12,LSL #3

  (371) 0x41a3e4 ADD	X15, X11, X15

    (389) 0x41a3e8 LDR	D3, [X13], #8

    (389) 0x41a3ec LDR	D4, [X15], #8

    (389) 0x41a3f0 SUBS	X14, X14, #1

    (389) 0x41a3f4 FMADD	D2, D4, D3, D2

    (389) 0x41a3f8 B.NE	41a3e8

  (371) 0x41a3fc UBFM	X13, X12, #60, #59

  (371) 0x41a400 CMP	W9, #4

  (371) 0x41a404 B.CS	41a414

  (371) 0x41a408 ORR	X14, XZR, XZR

  (371) 0x41a40c MOVI	D3, #0

  (371) 0x41a410 B	41a470

  (371) 0x41a414 ADD	X17, X11, X13

  (371) 0x41a418 AND	X14, X9, #6014

  (371) 0x41a41c ADD	X15, X24, #16

  (371) 0x41a420 MOVI	V3.2D, #0

  (371) 0x41a424 ORR	X18, XZR, X10

  (371) 0x41a428 MOVI	V4.2D, #0

  (371) 0x41a42c ADD	X17, X17, #16

  (371) 0x41a430 HINT	#0

  (371) 0x41a434 HINT	#0

  (371) 0x41a438 HINT	#0

  (371) 0x41a43c HINT	#0

    (387) 0x41a440 LDP	Q5, Q6, [X15, #2032]

    (387) 0x41a444 LDP	Q7, Q16, [X17, #2032]

    (387) 0x41a448 ADD	X15, X15, #32

    (387) 0x41a44c ADD	X17, X17, #32

    (387) 0x41a450 SUBS	X18, X18, #4

    (387) 0x41a454 FMLA	V4.2D, V16.2D, V6.2D

    (387) 0x41a458 FMLA	V3.2D, V7.2D, V5.2D

    (387) 0x41a45c B.NE	41a440

  (371) 0x41a460 FADD	V3.2D, V4.2D, V3.2D

  (371) 0x41a464 FADDP	D3, V3.2D

  (371) 0x41a468 CMP	X14, X9

  (371) 0x41a46c B.EQ	41a498

  (371) 0x41a470 SUB	X15, X8, X14

  (371) 0x41a474 ADD	X13, X13, X14,LSL #3

  (371) 0x41a478 ADD	X14, X24, X14,LSL #3

  (371) 0x41a47c HINT	#0

    (388) 0x41a480 LDR	D4, [X14], #8

    (388) 0x41a484 LDR	D5, [X11, X13]

    (388) 0x41a488 SUBS	X15, X15, #1

    (388) 0x41a48c ADD	X13, X13, #8

    (388) 0x41a490 FMADD	D3, D5, D4, D3

    (388) 0x41a494 B.NE	41a480

    (368) 0x41a498 LDR	X13, [X20, #256]

    (368) 0x41a49c LDR	X17, [X20, #240]

    (368) 0x41a4a0 LDR	X0, [X20, #296]

    (368) 0x41a4a4 FNEG	D0, D0

    (368) 0x41a4a8 ADD	X15, X13, X23,LSL #3

    (368) 0x41a4ac UBFM	X14, X17, #60, #59

    (368) 0x41a4b0 STR	D1, [X15]

    (368) 0x41a4b4 STR	D2, [X15, X17,LSL #3]

    (368) 0x41a4b8 STR	D3, [X15, X14]

    (368) 0x41a4bc STR	D0, [X0, X26]

    (368) 0x41a4c0 CMP	X23, #1

    (368) 0x41a4c4 B.LT	41a000

    (368) 0x41a4c8 ADD	W15, W27, W19

    (368) 0x41a4cc UBFM	X18, X9, #61, #31

    (368) 0x41a4d0 CMP	W9, #7

    (368) 0x41a4d4 B.HI	41a5a4

    (368) 0x41a4d8 ORR	X1, XZR, XZR

    (368) 0x41a4dc ORR	X5, XZR, X1

    (368) 0x41a4e0 TBZ	W15, #0, 41a510

    (368) 0x41a4e4 LDR	D0, [X22, X1,LSL #3]

    (368) 0x41a4e8 LDR	D1, [X16, X1,LSL #3]

    (368) 0x41a4ec ORR	X5, X1, #4096

    (368) 0x41a4f0 FADD	D0, D1, D0

    (368) 0x41a4f4 STR	D0, [X16, X1,LSL #3]

    (368) 0x41a4f8 LDR	D0, [X25, X1,LSL #3]

    (368) 0x41a4fc LDR	D1, [X24, X1,LSL #3]

    (368) 0x41a500 LDR	D2, [X0, X1,LSL #3]

    (368) 0x41a504 FNMSUB	D0, D1, D8, D0

    (368) 0x41a508 FADD	D0, D0, D2

    (368) 0x41a50c STR	D0, [X0, X1,LSL #3]

    (368) 0x41a510 SUB	X2, X15, #1

    (368) 0x41a514 CMP	X1, X2

    (368) 0x41a518 B.EQ	41a6c0

    (368) 0x41a51c ADD	X2, X24, X5,LSL #3

    (368) 0x41a520 ADD	X3, X25, X5,LSL #3

    (368) 0x41a524 ADD	X4, X22, X5,LSL #3

    (368) 0x41a528 ADD	X16, X16, X5,LSL #3

    (368) 0x41a52c ADD	X0, X0, X5,LSL #3

    (368) 0x41a530 SUB	X1, X8, X5

    (368) 0x41a534 ADD	X2, X2, #8

    (368) 0x41a538 ADD	X3, X3, #8

    (368) 0x41a53c ADD	X4, X4, #8

    (368) 0x41a540 ADD	X16, X16, #8

    (368) 0x41a544 ADD	X0, X0, #8

      (383) 0x41a548 LDUR	D0, [X4, #504]

      (383) 0x41a54c LDUR	D1, [X16, #504]

      (383) 0x41a550 SUBS	X1, X1, #2

      (383) 0x41a554 FADD	D0, D1, D0

      (383) 0x41a558 STUR	D0, [X16, #504]

      (383) 0x41a55c LDUR	D0, [X3, #504]

      (383) 0x41a560 LDUR	D1, [X2, #504]

      (383) 0x41a564 LDUR	D2, [X0, #504]

      (383) 0x41a568 FNMSUB	D0, D1, D8, D0

      (383) 0x41a56c FADD	D0, D0, D2

      (383) 0x41a570 STUR	D0, [X0, #504]

      (383) 0x41a574 LDR	D0, [X4], #16

      (383) 0x41a578 LDR	D1, [X16]

      (383) 0x41a57c FADD	D0, D1, D0

      (383) 0x41a580 STR	D0, [X16], #16

      (383) 0x41a584 LDR	D0, [X3], #16

      (383) 0x41a588 LDR	D1, [X2], #16

      (383) 0x41a58c LDR	D2, [X0]

      (383) 0x41a590 FNMSUB	D0, D1, D8, D0

      (383) 0x41a594 FADD	D0, D0, D2

      (383) 0x41a598 STR	D0, [X0], #16

      (383) 0x41a59c B.NE	41a548

    (368) 0x41a5a0 B	41a6c0

    (368) 0x41a5a4 ADD	X5, X22, X18

    (368) 0x41a5a8 ADD	X21, X16, X18

    (368) 0x41a5ac ADD	X6, X25, X18

    (368) 0x41a5b0 ADD	X7, X24, X18

    (368) 0x41a5b4 ADD	X26, X0, X18

    (368) 0x41a5b8 ORR	X1, XZR, XZR

    (368) 0x41a5bc CMP	X16, X5

    (368) 0x41a5c0 CCMP	X22, X21, #2, #3

    (368) 0x41a5c4 CSINC	W2, WZR, WZR, #2

    (368) 0x41a5c8 CMP	X16, X6

    (368) 0x41a5cc CCMP	X25, X21, #2, #3

    (368) 0x41a5d0 CSINC	W3, WZR, WZR, #2

    (368) 0x41a5d4 CMP	X16, X7

    (368) 0x41a5d8 CCMP	X24, X21, #2, #3

    (368) 0x41a5dc CSINC	W4, WZR, WZR, #2

    (368) 0x41a5e0 CMP	X0, X5

    (368) 0x41a5e4 CCMP	X22, X26, #2, #3

    (368) 0x41a5e8 CSINC	W5, WZR, WZR, #2

    (368) 0x41a5ec CMP	X0, X6

    (368) 0x41a5f0 CCMP	X25, X26, #2, #3

    (368) 0x41a5f4 CSINC	W6, WZR, WZR, #2

    (368) 0x41a5f8 CMP	X0, X7

    (368) 0x41a5fc CCMP	X24, X26, #2, #3

    (368) 0x41a600 CSINC	W7, WZR, WZR, #2

    (368) 0x41a604 CMP	X0, X21

    (368) 0x41a608 CCMP	X16, X26, #2, #3

    (368) 0x41a60c B.CC	41ab04

    (368) 0x41a610 LDR	X21, [SP, #32]

    (368) 0x41a614 TBNZ	W2, #0, 41ab08

    (368) 0x41a618 TBNZ	W3, #0, 41ab08

    (368) 0x41a61c TBNZ	W4, #0, 41ab08

    (368) 0x41a620 TBNZ	W5, #0, 41ab08

    (368) 0x41a624 TBNZ	W6, #0, 41ab08

    (368) 0x41a628 MOVZ	W6, #40

    (368) 0x41a62c TBNZ	W7, #0, 41a4dc

    (368) 0x41a630 AND	X1, X9, #6014

    (368) 0x41a634 ADD	X2, X22, #16

    (368) 0x41a638 ADD	X3, X0, #16

    (368) 0x41a63c ADD	X4, X16, #16

    (368) 0x41a640 ADD	X5, X24, #16

    (368) 0x41a644 ADD	X6, X25, #16

    (368) 0x41a648 ORR	X7, XZR, X10

      (384) 0x41a64c LDP	Q0, Q1, [X2, #2032]

      (384) 0x41a650 LDP	Q2, Q3, [X4, #2032]

      (384) 0x41a654 FMOV	V6.2D, #-2.0000000

      (384) 0x41a658 SUBS	X7, X7, #4

      (384) 0x41a65c ADD	X2, X2, #32

      (384) 0x41a660 FADD	V1.2D, V3.2D, V1.2D

      (384) 0x41a664 LDP	Q4, Q5, [X3, #2032]

      (384) 0x41a668 FADD	V0.2D, V2.2D, V0.2D

      (384) 0x41a66c LDP	Q2, Q3, [X5, #2032]

      (384) 0x41a670 ADD	X5, X5, #32

      (384) 0x41a674 STP	Q0, Q1, [X4, #2032]

      (384) 0x41a678 LDP	Q0, Q1, [X6, #2032]

      (384) 0x41a67c ADD	X4, X4, #32

      (384) 0x41a680 ADD	X6, X6, #32

      (384) 0x41a684 FNEG	V1.2D, V1.2D

      (384) 0x41a688 FNEG	V0.2D, V0.2D

      (384) 0x41a68c FMLA	V1.2D, V3.2D, V6.2D

      (384) 0x41a690 FMLA	V0.2D, V2.2D, V6.2D

      (384) 0x41a694 FADD	V1.2D, V1.2D, V5.2D

      (384) 0x41a698 FADD	V0.2D, V0.2D, V4.2D

      (384) 0x41a69c STP	Q0, Q1, [X3, #2032]

      (384) 0x41a6a0 ADD	X3, X3, #32

      (384) 0x41a6a4 B.NE	41a64c

    (368) 0x41a6a8 MOVZ	W6, #40

    (368) 0x41a6ac CMP	X1, X9

    (368) 0x41a6b0 B.NE	41a4dc

    (368) 0x41a6b4 HINT	#0

    (368) 0x41a6b8 HINT	#0

    (368) 0x41a6bc HINT	#0

    (368) 0x41a6c0 CMP	X23, #1

    (368) 0x41a6c4 B.LT	41a000

    (368) 0x41a6c8 LDUR	X16, [X29, #480]

    (368) 0x41a6cc AND	X16, X16, #4160

    (368) 0x41a6d0 CMP	W9, #4

    (368) 0x41a6d4 B.CS	41a7a8

    (368) 0x41a6d8 ORR	X0, XZR, XZR

    (368) 0x41a6dc ORR	X3, XZR, X0

    (368) 0x41a6e0 ANDS	XZR, X15, #4160

    (368) 0x41a6e4 B.EQ	41a720

    (368) 0x41a6e8 ORR	X1, XZR, X16

    (368) 0x41a6ec ORR	X3, XZR, X0

    (368) 0x41a6f0 HINT	#0

    (368) 0x41a6f4 HINT	#0

    (368) 0x41a6f8 HINT	#0

    (368) 0x41a6fc HINT	#0

      (381) 0x41a700 LDR	D0, [X24, X3,LSL #3]

      (381) 0x41a704 LDR	D1, [X11, X3,LSL #3]

      (381) 0x41a708 LDR	D2, [X13, X3,LSL #3]

      (381) 0x41a70c SUBS	X1, X1, #1

      (381) 0x41a710 FMSUB	D0, D1, D0, D2

      (381) 0x41a714 STR	D0, [X13, X3,LSL #3]

      (381) 0x41a718 ADD	X3, X3, #1

      (381) 0x41a71c B.NE	41a700

    (368) 0x41a720 SUB	X0, X0, X15

    (368) 0x41a724 CMN	X0, #4

    (368) 0x41a728 B.HI	41a820

    (368) 0x41a72c SUB	X0, X8, X3

    (368) 0x41a730 ADD	X1, X13, X3,LSL #3

    (368) 0x41a734 ADD	X2, X11, X3,LSL #3

    (368) 0x41a738 ADD	X3, X24, X3,LSL #3

    (368) 0x41a73c ADD	X1, X1, #16

    (368) 0x41a740 ADD	X2, X2, #16

    (368) 0x41a744 ADD	X3, X3, #16

      (380) 0x41a748 LDUR	D0, [X3, #496]

      (380) 0x41a74c LDUR	D1, [X2, #496]

      (380) 0x41a750 LDP	D2, D3, [X1, #1008]

      (380) 0x41a754 SUBS	X0, X0, #4

      (380) 0x41a758 FMSUB	D0, D1, D0, D2

      (380) 0x41a75c STUR	D0, [X1, #496]

      (380) 0x41a760 LDUR	D0, [X3, #504]

      (380) 0x41a764 LDUR	D1, [X2, #504]

      (380) 0x41a768 FMSUB	D0, D1, D0, D3

      (380) 0x41a76c LDP	D2, D3, [X1]

      (380) 0x41a770 STUR	D0, [X1, #504]

      (380) 0x41a774 LDR	D0, [X3]

      (380) 0x41a778 LDR	D1, [X2]

      (380) 0x41a77c FMSUB	D0, D1, D0, D2

      (380) 0x41a780 STR	D0, [X1]

      (380) 0x41a784 LDR	D0, [X3, #8]

      (380) 0x41a788 LDR	D1, [X2, #8]

      (380) 0x41a78c ADD	X2, X2, #32

      (380) 0x41a790 ADD	X3, X3, #32

      (380) 0x41a794 FMSUB	D0, D1, D0, D3

      (380) 0x41a798 STR	D0, [X1, #8]

      (380) 0x41a79c ADD	X1, X1, #32

      (380) 0x41a7a0 B.NE	41a748

    (368) 0x41a7a4 B	41a820

    (368) 0x41a7a8 ADD	X1, X11, X18

    (368) 0x41a7ac ADD	X2, X13, X18

    (368) 0x41a7b0 ADD	X3, X24, X18

    (368) 0x41a7b4 ORR	X0, XZR, XZR

    (368) 0x41a7b8 CMP	X13, X1

    (368) 0x41a7bc CCMP	X11, X2, #2, #3

    (368) 0x41a7c0 CSINC	W1, WZR, WZR, #2

    (368) 0x41a7c4 CMP	X24, X2

    (368) 0x41a7c8 CCMP	X13, X3, #2, #3

    (368) 0x41a7cc B.CC	41a6dc

    (368) 0x41a7d0 TBNZ	W1, #0, 41a6dc

    (368) 0x41a7d4 AND	X0, X9, #6014

    (368) 0x41a7d8 ADD	X1, X24, #16

    (368) 0x41a7dc ADD	X2, X11, #16

    (368) 0x41a7e0 ADD	X3, X13, #16

    (368) 0x41a7e4 ORR	X4, XZR, X10

      (382) 0x41a7e8 LDP	Q0, Q1, [X1, #2032]

      (382) 0x41a7ec LDP	Q2, Q3, [X2, #2032]

      (382) 0x41a7f0 ADD	X1, X1, #32

      (382) 0x41a7f4 ADD	X2, X2, #32

      (382) 0x41a7f8 SUBS	X4, X4, #4

      (382) 0x41a7fc LDP	Q4, Q5, [X3, #2032]

      (382) 0x41a800 FMLS	V5.2D, V3.2D, V1.2D

      (382) 0x41a804 FMLS	V4.2D, V2.2D, V0.2D

      (382) 0x41a808 STP	Q4, Q5, [X3, #2032]

      (382) 0x41a80c ADD	X3, X3, #32

      (382) 0x41a810 B.NE	41a7e8

    (368) 0x41a814 CMP	X0, X9

    (368) 0x41a818 B.NE	41a6dc

    (368) 0x41a81c HINT	#0

    (368) 0x41a820 ADD	X0, X13, X17,LSL #3

    (368) 0x41a824 ADD	X1, X11, X12,LSL #3

    (368) 0x41a828 CMP	W9, #4

    (368) 0x41a82c B.CS	41a900

    (368) 0x41a830 ORR	X2, XZR, XZR

    (368) 0x41a834 ORR	X3, XZR, X2

    (368) 0x41a838 ANDS	XZR, X15, #4160

    (368) 0x41a83c B.EQ	41a868

    (368) 0x41a840 ORR	X4, XZR, X16

    (368) 0x41a844 ORR	X3, XZR, X2

      (378) 0x41a848 LDR	D0, [X24, X3,LSL #3]

      (378) 0x41a84c LDR	D1, [X1, X3,LSL #3]

      (378) 0x41a850 LDR	D2, [X0, X3,LSL #3]

      (378) 0x41a854 SUBS	X4, X4, #1

      (378) 0x41a858 FMSUB	D0, D1, D0, D2

      (378) 0x41a85c STR	D0, [X0, X3,LSL #3]

      (378) 0x41a860 ADD	X3, X3, #1

      (378) 0x41a864 B.NE	41a848

    (368) 0x41a868 SUB	X0, X2, X15

    (368) 0x41a86c CMN	X0, #4

    (368) 0x41a870 B.HI	41a9a0

    (368) 0x41a874 UBFM	X1, X3, #61, #60

    (368) 0x41a878 UBFM	X2, X12, #61, #60

    (368) 0x41a87c SUB	X0, X8, X3

    (368) 0x41a880 ADD	X1, X1, X17,LSL #3

    (368) 0x41a884 ADD	X2, X2, X3,LSL #3

    (368) 0x41a888 ADD	X3, X24, X3,LSL #3

    (368) 0x41a88c ADD	X1, X13, X1

    (368) 0x41a890 ADD	X2, X11, X2

    (368) 0x41a894 ADD	X3, X3, #16

    (368) 0x41a898 ADD	X1, X1, #16

    (368) 0x41a89c ADD	X2, X2, #16

      (377) 0x41a8a0 LDUR	D0, [X3, #496]

      (377) 0x41a8a4 LDUR	D1, [X2, #496]

      (377) 0x41a8a8 LDP	D2, D3, [X1, #1008]

      (377) 0x41a8ac SUBS	X0, X0, #4

      (377) 0x41a8b0 FMSUB	D0, D1, D0, D2

      (377) 0x41a8b4 STUR	D0, [X1, #496]

      (377) 0x41a8b8 LDUR	D0, [X3, #504]

      (377) 0x41a8bc LDUR	D1, [X2, #504]

      (377) 0x41a8c0 FMSUB	D0, D1, D0, D3

      (377) 0x41a8c4 LDP	D2, D3, [X1]

      (377) 0x41a8c8 STUR	D0, [X1, #504]

      (377) 0x41a8cc LDR	D0, [X3]

      (377) 0x41a8d0 LDR	D1, [X2]

      (377) 0x41a8d4 FMSUB	D0, D1, D0, D2

      (377) 0x41a8d8 STR	D0, [X1]

      (377) 0x41a8dc LDR	D0, [X3, #8]

      (377) 0x41a8e0 LDR	D1, [X2, #8]

      (377) 0x41a8e4 ADD	X2, X2, #32

      (377) 0x41a8e8 ADD	X3, X3, #32

      (377) 0x41a8ec FMSUB	D0, D1, D0, D3

      (377) 0x41a8f0 STR	D0, [X1, #8]

      (377) 0x41a8f4 ADD	X1, X1, #32

      (377) 0x41a8f8 B.NE	41a8a0

    (368) 0x41a8fc B	41a9a0

    (368) 0x41a900 ADD	X3, X17, X9

    (368) 0x41a904 ADD	X5, X24, X18

    (368) 0x41a908 ORR	X2, XZR, XZR

    (368) 0x41a90c ADD	X4, X13, X3,LSL #3

    (368) 0x41a910 ADD	X3, X12, X9

    (368) 0x41a914 ADD	X3, X11, X3,LSL #3

    (368) 0x41a918 CMP	X0, X3

    (368) 0x41a91c CCMP	X1, X4, #2, #3

    (368) 0x41a920 CSINC	W3, WZR, WZR, #2

    (368) 0x41a924 CMP	X24, X4

    (368) 0x41a928 CCMP	X0, X5, #2, #3

    (368) 0x41a92c B.CC	41a834

    (368) 0x41a930 TBNZ	W3, #0, 41a834

    (368) 0x41a934 ADD	X4, X13, X17,LSL #3

    (368) 0x41a938 ADD	X5, X11, X12,LSL #3

    (368) 0x41a93c AND	X2, X9, #6014

    (368) 0x41a940 ADD	X3, X24, #16

    (368) 0x41a944 ORR	X6, XZR, X10

    (368) 0x41a948 ADD	X4, X4, #16

    (368) 0x41a94c ADD	X5, X5, #16

    (368) 0x41a950 HINT	#0

    (368) 0x41a954 HINT	#0

    (368) 0x41a958 HINT	#0

    (368) 0x41a95c HINT	#0

      (379) 0x41a960 LDP	Q0, Q1, [X3, #2032]

      (379) 0x41a964 LDP	Q2, Q3, [X5, #2032]

      (379) 0x41a968 SUBS	X6, X6, #4

      (379) 0x41a96c ADD	X3, X3, #32

      (379) 0x41a970 ADD	X5, X5, #32

      (379) 0x41a974 LDP	Q4, Q5, [X4, #2032]

      (379) 0x41a978 FMLS	V5.2D, V3.2D, V1.2D

      (379) 0x41a97c FMLS	V4.2D, V2.2D, V0.2D

      (379) 0x41a980 STP	Q4, Q5, [X4, #2032]

      (379) 0x41a984 ADD	X4, X4, #32

      (379) 0x41a988 B.NE	41a960

    (368) 0x41a98c MOVZ	W6, #40

    (368) 0x41a990 CMP	X2, X9

    (368) 0x41a994 B.NE	41a834

    (368) 0x41a998 HINT	#0

    (368) 0x41a99c HINT	#0

    (368) 0x41a9a0 ADD	X0, X13, X17,LSL #4

    (368) 0x41a9a4 UBFM	X17, X12, #60, #59

    (368) 0x41a9a8 ADD	X12, X11, X12,LSL #4

    (368) 0x41a9ac CMP	W9, #4

    (368) 0x41a9b0 B.CS	41aa80

    (368) 0x41a9b4 ORR	X1, XZR, XZR

    (368) 0x41a9b8 ORR	X18, XZR, X1

    (368) 0x41a9bc ANDS	XZR, X15, #4160

    (368) 0x41a9c0 B.EQ	41a9e8

    (368) 0x41a9c4 ORR	X18, XZR, X1

      (375) 0x41a9c8 LDR	D0, [X24, X18,LSL #3]

      (375) 0x41a9cc LDR	D1, [X12, X18,LSL #3]

      (375) 0x41a9d0 LDR	D2, [X0, X18,LSL #3]

      (375) 0x41a9d4 SUBS	X16, X16, #1

      (375) 0x41a9d8 FMSUB	D0, D1, D0, D2

      (375) 0x41a9dc STR	D0, [X0, X18,LSL #3]

      (375) 0x41a9e0 ADD	X18, X18, #1

      (375) 0x41a9e4 B.NE	41a9c8

    (368) 0x41a9e8 SUB	X9, X1, X15

    (368) 0x41a9ec CMN	X9, #4

    (368) 0x41a9f0 B.HI	41a000

    (368) 0x41a9f4 ADD	X10, X14, X18,LSL #3

    (368) 0x41a9f8 ADD	X12, X17, X18,LSL #3

    (368) 0x41a9fc SUB	X9, X8, X18

    (368) 0x41aa00 ADD	X10, X13, X10

    (368) 0x41aa04 ADD	X11, X11, X12

    (368) 0x41aa08 ADD	X12, X24, X18,LSL #3

    (368) 0x41aa0c ADD	X10, X10, #16

    (368) 0x41aa10 ADD	X11, X11, #16

    (368) 0x41aa14 ADD	X12, X12, #16

    (368) 0x41aa18 HINT	#0

    (368) 0x41aa1c HINT	#0

      (374) 0x41aa20 LDUR	D0, [X12, #496]

      (374) 0x41aa24 LDUR	D1, [X11, #496]

      (374) 0x41aa28 LDP	D2, D3, [X10, #1008]

      (374) 0x41aa2c SUBS	X9, X9, #4

      (374) 0x41aa30 FMSUB	D0, D1, D0, D2

      (374) 0x41aa34 STUR	D0, [X10, #496]

      (374) 0x41aa38 LDUR	D0, [X12, #504]

      (374) 0x41aa3c LDUR	D1, [X11, #504]

      (374) 0x41aa40 FMSUB	D0, D1, D0, D3

      (374) 0x41aa44 LDP	D2, D3, [X10]

      (374) 0x41aa48 STUR	D0, [X10, #504]

      (374) 0x41aa4c LDR	D0, [X12]

      (374) 0x41aa50 LDR	D1, [X11]

      (374) 0x41aa54 FMSUB	D0, D1, D0, D2

      (374) 0x41aa58 STR	D0, [X10]

      (374) 0x41aa5c LDR	D0, [X12, #8]

      (374) 0x41aa60 LDR	D1, [X11, #8]

      (374) 0x41aa64 ADD	X11, X11, #32

      (374) 0x41aa68 ADD	X12, X12, #32

      (374) 0x41aa6c FMSUB	D0, D1, D0, D3

      (374) 0x41aa70 STR	D0, [X10, #8]

      (374) 0x41aa74 ADD	X10, X10, #32

      (374) 0x41aa78 B.NE	41aa20

    (368) 0x41aa7c B	41a000

    (368) 0x41aa80 ADD	X2, X13, X14

    (368) 0x41aa84 ADD	X3, X24, X18

    (368) 0x41aa88 ORR	X1, XZR, XZR

    (368) 0x41aa8c ADD	X2, X2, X18

    (368) 0x41aa90 ADD	X18, X17, X18

    (368) 0x41aa94 ADD	X18, X11, X18

    (368) 0x41aa98 CMP	X0, X18

    (368) 0x41aa9c CCMP	X12, X2, #2, #3

    (368) 0x41aaa0 CSINC	W18, WZR, WZR, #2

    (368) 0x41aaa4 CMP	X24, X2

    (368) 0x41aaa8 CCMP	X0, X3, #2, #3

    (368) 0x41aaac B.CC	41a9b8

    (368) 0x41aab0 TBNZ	W18, #0, 41a9b8

    (368) 0x41aab4 ADD	X2, X13, X14

    (368) 0x41aab8 ADD	X3, X11, X17

    (368) 0x41aabc AND	X1, X9, #6014

    (368) 0x41aac0 ADD	X18, X24, #16

    (368) 0x41aac4 ADD	X2, X2, #16

    (368) 0x41aac8 ADD	X3, X3, #16

      (376) 0x41aacc LDP	Q0, Q1, [X18, #2032]

      (376) 0x41aad0 LDP	Q2, Q3, [X3, #2032]

      (376) 0x41aad4 SUBS	X10, X10, #4

      (376) 0x41aad8 ADD	X18, X18, #32

      (376) 0x41aadc ADD	X3, X3, #32

      (376) 0x41aae0 LDP	Q4, Q5, [X2, #2032]

      (376) 0x41aae4 FMLS	V5.2D, V3.2D, V1.2D

      (376) 0x41aae8 FMLS	V4.2D, V2.2D, V0.2D

      (376) 0x41aaec STP	Q4, Q5, [X2, #2032]

      (376) 0x41aaf0 ADD	X2, X2, #32

      (376) 0x41aaf4 B.NE	41aacc

    (368) 0x41aaf8 CMP	X1, X9

    (368) 0x41aafc B.EQ	41a000

    (368) 0x41ab00 B	41a9b8

    (368) 0x41ab04 LDR	X21, [SP, #32]

    (368) 0x41ab08 MOVZ	W6, #40

    (368) 0x41ab0c B	41a4dc

0x41ab10 LDR	D8, [SP, #96]

0x41ab14 LDP	X20, X19, [SP, #192]

0x41ab18 LDP	X22, X21, [SP, #176]

0x41ab1c LDP	X24, X23, [SP, #160]

0x41ab20 LDP	X26, X25, [SP, #144]

0x41ab24 LDP	X28, X27, [SP, #128]

0x41ab28 LDP	X29, X30, [SP, #112]

0x41ab2c ADD	SP, SP, #208

0x41ab30 RET

0x41ab34 HINT	#0

0x41ab38 HINT	#0

0x41ab3c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	TwoBodyJastrowRef.h:268-402
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_numeric.h:140-141
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/shared_ptr_base.h:1667
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:952,1146
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_iterator.h:1068
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:268-274,359-367,375-391,397-402
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131,1150,1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263,271-273

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.33 to 0.83 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 69% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.33 to 5.25 cycles (1.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.33 to 0.50 cycles (12.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Overall L1	6.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.33 cycles. At this rate:

19% of peak load performance is reached (18.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 419f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W1, [X0, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 447670 <_ZNK11qmcplusplus11ParticleSet14getDistTableAAEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X28, 41ab10 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0xbf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D8, #-2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W6, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X28, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X19, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 419f9c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	TwoBodyJastrowRef.h:268-402
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_numeric.h:140-141
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/shared_ptr_base.h:1667
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:952,1146
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_iterator.h:1068
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:268-274,359-367,375-391,397-402
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131,1150,1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263,271-273

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.33 to 0.83 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.33 to 0.50 cycles (12.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Overall L1	6.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.33 cycles. At this rate:

19% of peak load performance is reached (18.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 419f20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W1, [X0, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 447670 <_ZNK11qmcplusplus11ParticleSet14getDistTableAAEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X28, 41ab10 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0xbf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D8, #-2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W6, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X28, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X19, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 419f9c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)–	0.09	0.12
▼Loop 369 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
○Loop 365 - TwoBodyJastrowRef.h:375-376 - exec	0.00	0.01
▼Loop 371 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
○Loop 385 - TwoBodyJastrowRef.h:381-382 - exec	0.02	0.02
○Loop 386 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.02
○Loop 387 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.02
▼Loop 368 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
○Loop 384 - TwoBodyJastrowRef.h:388-391 - exec	0.02	0.02
○Loop 382 - TwoBodyJastrowRef.h:397-398 - exec	0.01	0.01
○Loop 376 - TwoBodyJastrowRef.h:397-398 - exec	0.01	0.01
○Loop 379 - TwoBodyJastrowRef.h:397-398 - exec	0.01	0.01
○Loop 372 - stl_numeric.h:141-141 - exec	0.00	0.01
○Loop 373 - TwoBodyJastrowRef.h:269-274 - exec	0.00	0.00
○Loop 378 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 374 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 375 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 367 - stl_numeric.h:140-141 - exec	0.00	0.00
○Loop 366 - TwoBodyJastrowRef.h:361-364 - exec	0.00	0.00
○Loop 377 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 381 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 380 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 383 - TwoBodyJastrowRef.h:388-391 - exec	0.00	0.00
○Loop 370 - TwoBodyJastrowRef.h:375-376 - exec	0.00	0.00
○Loop 388 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 389 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 390 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code