OV - exec - Function qmcplusplus::BsplineFunctor<double>::evaluateV(int, int, int, double const*, double*) const

	Function: qmcplusplus::BsplineFunctor<double>::evaluateV(int, int, int, double const, double) cons ...	Module: exec	Source: BsplineFunctor.h:228-262	Coverage (incl. loops): 0.03% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 228 - 262

--------------------------------------------------------------------------------

228: {

229:   const real_type* restrict distArray = _distArray + iStart;

230:

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

261:   }

262:   return d;

0x417960 MOVI	D0, #0

0x417964 SUB	W8, W3, W2

0x417968 CMP	W8, #1

0x41796c B.LT	417a8c

0x417970 STP	D11, D10, [SP, #992]!

0x417974 STP	D9, D8, [SP, #16]

0x417978 LDR	D1, [X0, #8]

0x41797c ADD	X10, X4, W2,SXTW #3

0x417980 SUB	W11, W1, W2

0x417984 ORR	W9, WZR, WZR

0x417988 B	41799c

(312) 0x41798c SUB	W11, W11, #1

(312) 0x417990 ADD	X10, X10, #8

(312) 0x417994 SUBS	X8, X8, #1

(312) 0x417998 B.EQ	4179b8

(312) 0x41799c LDR	D2, [X10]

(312) 0x4179a0 FCMP	D2, D1

(312) 0x4179a4 CCMP	W11, #0, #4, #11

(312) 0x4179a8 B.EQ	41798c

(312) 0x4179ac STR	D2, [X5, X9,SXTW #3]

(312) 0x4179b0 ADD	W9, W9, #1

(312) 0x4179b4 B	41798c

0x4179b8 CMP	W9, #1

0x4179bc B.LT	417a84

0x4179c0 LDR	D1, [X0, #568]

0x4179c4 LDP	D2, D3, [X0, #24]

0x4179c8 LDP	D4, D5, [X0, #40]

0x4179cc MOVI	D0, #0

0x4179d0 ORR	W9, WZR, W9

0x4179d4 LDP	D6, D7, [X0, #56]

0x4179d8 LDP	D16, D17, [X0, #72]

0x4179dc LDP	D18, D19, [X0, #88]

0x4179e0 LDP	D20, D21, [X0, #104]

0x4179e4 LDR	X8, [X0, #536]

0x4179e8 ADD	X10, X8, #8

0x4179ec LDP	D22, D23, [X0, #120]

0x4179f0 LDP	D24, D25, [X0, #136]

0x4179f4 ADD	X11, X8, #16

0x4179f8 ADD	X12, X8, #24

0x4179fc HINT	#0

(311) 0x417a00 LDR	D26, [X5], #8

(311) 0x417a04 SUBS	X9, X9, #1

(311) 0x417a08 FMUL	D26, D1, D26

(311) 0x417a0c FRINTZ	D27, D26

(311) 0x417a10 FCVTZS	W13, D26

(311) 0x417a14 FSUB	D26, D26, S27

(311) 0x417a18 LDR	D29, [X8, X13,SXTW #3]

(311) 0x417a1c LDR	D31, [X10, X13,SXTW #3]

(311) 0x417a20 LDR	D9, [X11, X13,SXTW #3]

(311) 0x417a24 LDR	D11, [X12, X13,SXTW #3]

(311) 0x417a28 FMUL	D27, D26, D26

(311) 0x417a2c FMUL	D30, D27, D3

(311) 0x417a30 FMUL	D28, D27, D26

(311) 0x417a34 FMADD	D30, D4, D26, D30

(311) 0x417a38 FMUL	D8, D6, D28

(311) 0x417a3c FMUL	D10, D18, D28

(311) 0x417a40 FMADD	D8, D7, D27, D8

(311) 0x417a44 FMADD	D10, D19, D27, D10

(311) 0x417a48 FADD	D30, D30, D5

(311) 0x417a4c FMADD	D8, D16, D26, D8

(311) 0x417a50 FMADD	D10, D20, D26, D10

(311) 0x417a54 FMADD	D30, D28, D2, D30

(311) 0x417a58 FMUL	D28, D22, D28

(311) 0x417a5c FMADD	D27, D23, D27, D28

(311) 0x417a60 FADD	D8, D8, D17

(311) 0x417a64 FMADD	D26, D24, D26, D27

(311) 0x417a68 FADD	D10, D10, D21

(311) 0x417a6c FMADD	D0, D30, D29, D0

(311) 0x417a70 FMADD	D0, D8, D31, D0

(311) 0x417a74 FADD	D26, D26, D25

(311) 0x417a78 FMADD	D0, D10, D9, D0

(311) 0x417a7c FMADD	D0, D26, D11, D0

(311) 0x417a80 B.NE	417a00

0x417a84 LDP	D9, D8, [SP, #16]

0x417a88 LDP	D11, D10, [SP], #32

0x417a8c RET

0x417a90 HINT	#0

0x417a94 HINT	#0

0x417a98 HINT	#0

0x417a9c HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:135	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:272	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:126	exec
○	main.omp_outlined.63	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	BsplineFunctor.h:228-262
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:228-262.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is partially vectorized. Only 69% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.00 to 4.67 cycles (1.07x speedup).

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.08	2.08	2.00	2.00	1.92	1.92	1.00	1.00	1.00	1.00	5.00	5.00	5.00	0.00	0.00
cycles	2.00	2.00	2.08	2.08	2.00	2.00	1.92	1.92	1.00	1.00	1.00	1.00	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.88
Overall L1	5.00

Vectorization ratios

all	50%
load	83%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.00 cycles. At this rate:

38% of peak load performance is reached (36.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 417960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417a8c <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D11, D10, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X10, X4, W2,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
SUB W11, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 41799c <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417a84 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D2, D3, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D4, D5, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR W9, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D6, D7, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D16, D17, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D18, D19, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D20, D21, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X8, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X8, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP D22, D23, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D24, D25, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X11, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X8, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	BsplineFunctor.h:228-262
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:228-262.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

50% of VPU instructions are used in vector version (process two or more data elements in vector registers):

83% of VPU loads are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 184 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	36
loop length	144
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.08	2.08	2.00	2.00	1.92	1.92	1.00	1.00	1.00	1.00	5.00	5.00	5.00	0.00	0.00
cycles	2.00	2.00	2.08	2.08	2.00	2.00	1.92	1.92	1.00	1.00	1.00	1.00	5.00	5.00	5.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.88
Overall L1	5.00

Vectorization ratios

all	50%
load	83%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.00 cycles. At this rate:

38% of peak load performance is reached (36.80 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
13% of peak store performance is reached (6.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 417960

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
SUB W8, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417a8c <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x12c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D11, D10, [SP, #992]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
ADD X10, X4, W2,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
SUB W11, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W9, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
B 41799c <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x3c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W9, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417a84 <_ZNK11qmcplusplus14BsplineFunctorIdE9evaluateVEiiiPKdPd+0x124>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D1, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D2, D3, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D4, D5, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ORR W9, WZR, W9	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D6, D7, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D16, D17, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D18, D19, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D20, D21, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X8, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X10, X8, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP D22, D23, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D24, D25, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ADD X11, X8, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X8, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
HINT #0																					N/A
LDP D9, D8, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineFunctor::evaluateV(int, int, int, double const, double) const–	0.03	0.05
○Loop 312 - BsplineFunctor.h:236-241 - exec	0.03	0.04
○Loop 311 - BsplineFunctor.h:246-260 - exec	0.00	0.01

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Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code