OV - exec - Function qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const*, double*, double*, double*, double*, int*) const

	Function: qmcplusplus::BsplineFunctor<double>::evaluateVGL(int, int, int, double const, double, do ...	Module: exec	Source: BsplineFunctor.h:284-339 [...]	Coverage (incl. loops): 0.51% \| (excl. loops): 0.04%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h: 1150 - 1150

--------------------------------------------------------------------------------

1150: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 284 - 339

--------------------------------------------------------------------------------

284:   int iLimit                 = iEnd - iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

299:     }

300:   }

301:

302:   #pragma omp simd

303:   for (int j = 0; j < iCount; j++)

304:   {

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

337:     // clang-format on

338:   }

339: }

0x416ec0 SUB	W11, W3, W2

0x416ec4 CMP	W11, #1

0x416ec8 B.LT	417588

0x416ecc STP	D15, D14, [SP, #944]!

0x416ed0 STP	D13, D12, [SP, #16]

0x416ed4 STP	D11, D10, [SP, #32]

0x416ed8 STP	D9, D8, [SP, #48]

0x416edc STP	X29, X19, [SP, #64]

0x416ee0 SUB	SP, SP, #784

0x416ee4 LDR	D0, [X0, #568]

0x416ee8 LDR	D1, [X0, #8]

0x416eec LDR	X16, [SP, #872]

0x416ef0 SBFM	X10, X2, #61, #31

0x416ef4 SUB	W14, W1, W2

0x416ef8 ORR	X12, XZR, XZR

0x416efc ORR	W18, WZR, WZR

0x416f00 ADD	X13, X4, X10

0x416f04 LDR	X15, [SP, #864]

0x416f08 ADD	X8, X5, X10

0x416f0c ADD	X9, X6, X10

0x416f10 ADD	X10, X7, X10

0x416f14 FMUL	D23, D0, D0

0x416f18 B	416f2c

0x416f1c HINT	#0

(308) 0x416f20 ADD	X12, X12, #1

(308) 0x416f24 CMP	X11, X12

(308) 0x416f28 B.EQ	416f4c

(308) 0x416f2c LDR	D2, [X13, X12,LSL #3]

(308) 0x416f30 FCMP	D2, D1

(308) 0x416f34 CCMP	W14, W12, #4, #11

(308) 0x416f38 B.EQ	416f20

(308) 0x416f3c STR	W12, [X16, X18,SXTW #2]

(308) 0x416f40 STR	D2, [X15, X18,SXTW #3]

(308) 0x416f44 ADD	W18, W18, #1

(308) 0x416f48 B	416f20

0x416f4c CMP	W18, #1

0x416f50 B.LT	417570

0x416f54 LDR	D19, [X0, #120]

0x416f58 STR	Q0, [SP, #480]

0x416f5c LDP	D24, D1, [X0, #296]

0x416f60 ORR	W17, WZR, W18

0x416f64 LDP	D12, D0, [X0, #328]

0x416f68 LDP	D4, D6, [X0, #160]

0x416f6c LDR	D31, [X0, #176]

0x416f70 LDR	D11, [X0, #208]

0x416f74 LDP	D28, D14, [X0, #224]

0x416f78 LDR	D15, [X0, #240]

0x416f7c LDR	D20, [X0, #272]

0x416f80 LDP	D7, D10, [X0, #256]

0x416f84 LDP	D3, D17, [X0, #24]

0x416f88 LDP	D27, D30, [X0, #40]

0x416f8c LDP	D2, D21, [X0, #56]

0x416f90 LDP	D5, D22, [X0, #72]

0x416f94 LDP	D26, D18, [X0, #88]

0x416f98 LDP	D16, D13, [X0, #104]

0x416f9c LDR	X11, [X0, #536]

0x416fa0 ADD	X12, X11, #8

0x416fa4 ADD	X13, X11, #16

0x416fa8 ADD	X14, X11, #24

0x416fac STP	Q0, Q1, [SP, #528]

0x416fb0 LDP	D29, D1, [X0, #360]

0x416fb4 LDP	D9, D0, [X0, #392]

0x416fb8 STR	Q19, [SP, #768]

0x416fbc LDR	D19, [X0, #128]

0x416fc0 STP	Q0, Q1, [SP, #496]

0x416fc4 LDP	D8, D1, [X0, #192]

0x416fc8 STP	Q3, Q17, [SP, #592]

0x416fcc STP	Q21, Q14, [SP, #624]

0x416fd0 STP	Q29, Q18, [SP, #656]

0x416fd4 STP	Q16, Q6, [SP, #688]

0x416fd8 STR	Q19, [SP, #752]

0x416fdc LDP	D19, D0, [X0, #136]

0x416fe0 STP	Q4, Q19, [SP, #720]

0x416fe4 CMP	W18, #3

0x416fe8 B.HI	41701c

0x416fec ORR	V25.16B, V0.16B, V0.16B

0x416ff0 LDR	Q0, [SP, #480]

0x416ff4 ORR	V3.16B, V10.16B, V10.16B

0x416ff8 ORR	V10.16B, V8.16B, V8.16B

0x416ffc ORR	V8.16B, V1.16B, V1.16B

0x417000 ORR	X18, XZR, XZR

0x417004 ORR	V17.16B, V9.16B, V9.16B

0x417008 ORR	V9.16B, V11.16B, V11.16B

0x41700c ORR	V29.16B, V15.16B, V15.16B

0x417010 ORR	V11.16B, V2.16B, V2.16B

0x417014 ORR	V15.16B, V5.16B, V5.16B

0x417018 B	417410

0x41701c LDP	Q19, Q4, [SP, #528]

0x417020 LDR	Q29, [SP, #480]

0x417024 STP	Q28, Q1, [SP, #336]

0x417028 AND	X18, X17, #5950

0x41702c ADD	X0, X16, #8

0x417030 ORR	X2, XZR, X15

0x417034 ORR	X1, XZR, X18

0x417038 STP	Q5, Q8, [SP, #416]

0x41703c LDR	Q25, [SP, #624]

0x417040 LDR	Q14, [SP, #416]

0x417044 DUP	V3.2D, V4.D[0]

0x417048 STP	Q0, Q13, [SP]

0x41704c DUP	V0.2D, V0.D[0]

0x417050 STP	Q22, Q30, [SP, #32]

0x417054 STP	Q20, Q15, [SP, #64]

0x417058 STP	Q11, Q31, [SP, #96]

0x41705c STP	Q12, Q9, [SP, #368]

0x417060 DUP	V19.2D, V19.D[0]

0x417064 STP	Q19, Q3, [SP, #304]

0x417068 LDP	Q19, Q1, [SP, #496]

0x41706c STP	Q26, Q27, [SP, #448]

0x417070 STR	Q2, [SP, #400]

0x417074 STR	Q23, [SP, #128]

0x417078 DUP	V3.2D, V1.D[0]

0x41707c DUP	V19.2D, V19.D[0]

0x417080 STP	Q19, Q3, [SP, #272]

0x417084 DUP	V3.2D, V31.D[0]

0x417088 DUP	V19.2D, V11.D[0]

0x41708c STP	Q19, Q3, [SP, #240]

0x417090 DUP	V3.2D, V15.D[0]

0x417094 DUP	V19.2D, V20.D[0]

0x417098 STP	Q19, Q3, [SP, #208]

0x41709c DUP	V3.2D, V30.D[0]

0x4170a0 DUP	V19.2D, V22.D[0]

0x4170a4 STP	Q19, Q3, [SP, #176]

0x4170a8 DUP	V19.2D, V13.D[0]

0x4170ac LDR	Q8, [SP, #176]

0x4170b0 STP	Q0, Q19, [SP, #144]

0x4170b4 HINT	#0

0x4170b8 HINT	#0

0x4170bc HINT	#0

(306) 0x4170c0 LDP	Q0, Q2, [X2], #32

(306) 0x4170c4 ORR	V27.16B, V24.16B, V24.16B

(306) 0x4170c8 SUBS	X1, X1, #4

(306) 0x4170cc FMUL	V1.2D, V0.2D, V29.D[0]

(306) 0x4170d0 STP	Q2, Q0, [SP, #560]

(306) 0x4170d4 FMUL	V2.2D, V2.2D, V29.D[0]

(306) 0x4170d8 LDR	Q31, [SP, #192]

(306) 0x4170dc LDP	Q11, Q15, [SP, #240]

(306) 0x4170e0 LDR	Q30, [SP, #432]

(306) 0x4170e4 LDP	Q0, Q17, [SP, #352]

(306) 0x4170e8 LDR	Q20, [SP, #400]

(306) 0x4170ec FCVTZS	V5.2D, V1.2D

(306) 0x4170f0 FCVTZS	V4.2D, V2.2D

(306) 0x4170f4 FRINTZ	V16.2D, V2.2D

(306) 0x4170f8 XTN	V6.2S, V5.2D

(306) 0x4170fc XTN	V4.2S, V4.2D

(306) 0x417100 FRINTZ	V5.2D, V1.2D

(306) 0x417104 FSUB	V9.2D, V2.2D, V16.2D

(306) 0x417108 MOV	W3, V6.S[1]

(306) 0x41710c FMOV	W5, S6

(306) 0x417110 MOV	W4, V4.S[1]

(306) 0x417114 FMUL	V13.2D, V9.2D, V9.2D

(306) 0x417118 FSUB	V23.2D, V1.2D, V5.2D

(306) 0x41711c LDP	Q2, Q1, [SP, #592]

(306) 0x417120 SBFM	X6, X3, #61, #31

(306) 0x417124 FMOV	W3, S4

(306) 0x417128 LDR	D18, [X11, X5,SXTW #3]

(306) 0x41712c LDR	D19, [X12, X5,SXTW #3]

(306) 0x417130 LDP	Q3, Q4, [SP, #304]

(306) 0x417134 SBFM	X4, X4, #61, #31

(306) 0x417138 ADD	X7, X11, X6

(306) 0x41713c ADD	X19, X11, X4

(306) 0x417140 FMUL	V28.2D, V13.2D, V9.2D

(306) 0x417144 FMUL	V5.2D, V23.2D, V23.2D

(306) 0x417148 LDR	D22, [X11, X3,SXTW #3]

(306) 0x41714c LDR	D21, [X12, X3,SXTW #3]

(306) 0x417150 ORR	V6.16B, V4.16B, V4.16B

(306) 0x417154 FMLA	V4.2D, V9.2D, V24.D[0]

(306) 0x417158 FMUL	V26.2D, V5.2D, V23.2D

(306) 0x41715c FMLA	V6.2D, V23.2D, V24.D[0]

(306) 0x417160 ORR	V24.16B, V3.16B, V3.16B

(306) 0x417164 ORR	V16.16B, V3.16B, V3.16B

(306) 0x417168 ORR	V3.16B, V7.16B, V7.16B

(306) 0x41716c ORR	V7.16B, V10.16B, V10.16B

(306) 0x417170 LDP	Q12, Q10, [SP, #704]

(306) 0x417174 LD1	{V18.D[1]}, [X7]

(306) 0x417178 ADD	X7, X12, X6

(306) 0x41717c LD1	{V19.D[1]}, [X7]

(306) 0x417180 ADD	X7, X12, X4

(306) 0x417184 FMLA	V24.2D, V9.2D, V17.D[0]

(306) 0x417188 FMLA	V16.2D, V23.2D, V17.D[0]

(306) 0x41718c LDR	Q17, [SP, #464]

(306) 0x417190 LD1	{V22.D[1]}, [X19]

(306) 0x417194 LD1	{V21.D[1]}, [X7]

(306) 0x417198 ADD	X19, X13, X6

(306) 0x41719c ADD	X7, X13, X4

(306) 0x4171a0 ADD	X6, X14, X6

(306) 0x4171a4 ADD	X4, X14, X4

(306) 0x4171a8 FMUL	V6.2D, V6.2D, V18.2D

(306) 0x4171ac FMLA	V6.2D, V16.2D, V19.2D

(306) 0x4171b0 FMUL	V16.2D, V13.2D, V10.D[0]

(306) 0x4171b4 FMUL	V4.2D, V4.2D, V22.2D

(306) 0x4171b8 FMLA	V16.2D, V9.2D, V12.D[0]

(306) 0x4171bc FMLA	V4.2D, V24.2D, V21.2D

(306) 0x4171c0 FMUL	V24.2D, V28.2D, V2.D[0]

(306) 0x4171c4 FMLA	V24.2D, V13.2D, V1.D[0]

(306) 0x4171c8 FMLA	V24.2D, V9.2D, V17.D[0]

(306) 0x4171cc FADD	V16.2D, V16.2D, V15.2D

(306) 0x4171d0 FMUL	V16.2D, V16.2D, V22.2D

(306) 0x4171d4 FADD	V24.2D, V24.2D, V31.2D

(306) 0x4171d8 FMUL	V22.2D, V24.2D, V22.2D

(306) 0x4171dc FMUL	V24.2D, V13.2D, V30.D[0]

(306) 0x4171e0 FMLA	V24.2D, V9.2D, V0.D[0]

(306) 0x4171e4 FADD	V24.2D, V24.2D, V11.2D

(306) 0x4171e8 FMLA	V16.2D, V24.2D, V21.2D

(306) 0x4171ec FMUL	V24.2D, V28.2D, V20.D[0]

(306) 0x4171f0 FMLA	V24.2D, V13.2D, V25.D[0]

(306) 0x4171f4 FMLA	V24.2D, V9.2D, V14.D[0]

(306) 0x4171f8 FADD	V24.2D, V24.2D, V8.2D

(306) 0x4171fc FMLA	V22.2D, V24.2D, V21.2D

(306) 0x417200 FMUL	V21.2D, V5.2D, V10.D[0]

(306) 0x417204 FMUL	V24.2D, V5.2D, V30.D[0]

(306) 0x417208 FMLA	V21.2D, V23.2D, V12.D[0]

(306) 0x41720c FMLA	V24.2D, V23.2D, V0.D[0]

(306) 0x417210 LDR	Q0, [SP, #336]

(306) 0x417214 FADD	V21.2D, V21.2D, V15.2D

(306) 0x417218 FADD	V24.2D, V24.2D, V11.2D

(306) 0x41721c LDR	Q15, [SP, #288]

(306) 0x417220 LDR	Q11, [SP, #224]

(306) 0x417224 LDP	Q12, Q10, [SP, #672]

(306) 0x417228 FMUL	V21.2D, V21.2D, V18.2D

(306) 0x41722c FMLA	V21.2D, V24.2D, V19.2D

(306) 0x417230 FMUL	V24.2D, V26.2D, V2.D[0]

(306) 0x417234 FMLA	V24.2D, V5.2D, V1.D[0]

(306) 0x417238 LDR	Q1, [SP, #736]

(306) 0x41723c FMLA	V24.2D, V23.2D, V17.D[0]

(306) 0x417240 LDR	Q17, [SP, #448]

(306) 0x417244 FADD	V24.2D, V24.2D, V31.2D

(306) 0x417248 FMUL	V18.2D, V24.2D, V18.2D

(306) 0x41724c FMUL	V24.2D, V26.2D, V20.D[0]

(306) 0x417250 LDP	Q31, Q30, [SP, #640]

(306) 0x417254 LDR	Q20, [SP, #160]

(306) 0x417258 FMLA	V24.2D, V5.2D, V25.D[0]

(306) 0x41725c FMLA	V24.2D, V23.2D, V14.D[0]

(306) 0x417260 FADD	V24.2D, V24.2D, V8.2D

(306) 0x417264 FMLA	V18.2D, V24.2D, V19.2D

(306) 0x417268 LDR	D19, [X13, X5,SXTW #3]

(306) 0x41726c ORR	V24.16B, V15.16B, V15.16B

(306) 0x417270 FMLA	V15.2D, V9.2D, V30.D[0]

(306) 0x417274 FMLA	V24.2D, V23.2D, V30.D[0]

(306) 0x417278 LD1	{V19.D[1]}, [X19]

(306) 0x41727c FMLA	V6.2D, V24.2D, V19.2D

(306) 0x417280 FMUL	V24.2D, V5.2D, V0.D[0]

(306) 0x417284 FMLA	V24.2D, V23.2D, V31.D[0]

(306) 0x417288 FADD	V24.2D, V24.2D, V11.2D

(306) 0x41728c FMLA	V21.2D, V24.2D, V19.2D

(306) 0x417290 FMUL	V24.2D, V26.2D, V17.D[0]

(306) 0x417294 FMLA	V24.2D, V5.2D, V12.D[0]

(306) 0x417298 FMLA	V24.2D, V23.2D, V10.D[0]

(306) 0x41729c FADD	V24.2D, V24.2D, V20.2D

(306) 0x4172a0 FMLA	V18.2D, V24.2D, V19.2D

(306) 0x4172a4 LDR	D19, [X13, X3,SXTW #3]

(306) 0x4172a8 FMUL	V24.2D, V13.2D, V0.D[0]

(306) 0x4172ac FMLA	V24.2D, V9.2D, V31.D[0]

(306) 0x4172b0 FADD	V24.2D, V24.2D, V11.2D

(306) 0x4172b4 LDR	Q11, [SP, #208]

(306) 0x4172b8 LD1	{V19.D[1]}, [X7]

(306) 0x4172bc FMLA	V16.2D, V24.2D, V19.2D

(306) 0x4172c0 FMUL	V24.2D, V28.2D, V17.D[0]

(306) 0x4172c4 FMLA	V4.2D, V15.2D, V19.2D

(306) 0x4172c8 LDR	Q17, [SP, #384]

(306) 0x4172cc FMLA	V24.2D, V13.2D, V12.D[0]

(306) 0x4172d0 FMLA	V24.2D, V9.2D, V10.D[0]

(306) 0x4172d4 ORR	V10.16B, V7.16B, V7.16B

(306) 0x4172d8 ORR	V7.16B, V3.16B, V3.16B

(306) 0x4172dc LDR	Q3, [SP, #272]

(306) 0x4172e0 FADD	V24.2D, V24.2D, V20.2D

(306) 0x4172e4 FMLA	V22.2D, V24.2D, V19.2D

(306) 0x4172e8 LDR	D19, [X14, X5,SXTW #3]

(306) 0x4172ec ORR	V24.16B, V3.16B, V3.16B

(306) 0x4172f0 FMLA	V24.2D, V23.2D, V17.D[0]

(306) 0x4172f4 LD1	{V19.D[1]}, [X6]

(306) 0x4172f8 FMLA	V6.2D, V24.2D, V19.2D

(306) 0x4172fc FMUL	V24.2D, V5.2D, V7.D[0]

(306) 0x417300 FMLA	V24.2D, V23.2D, V10.D[0]

(306) 0x417304 FADD	V24.2D, V24.2D, V11.2D

(306) 0x417308 FMLA	V21.2D, V24.2D, V19.2D

(306) 0x41730c ORR	V24.16B, V27.16B, V27.16B

(306) 0x417310 LDP	Q27, Q0, [SP, #752]

(306) 0x417314 FMUL	V2.2D, V26.2D, V0.D[0]

(306) 0x417318 FMLA	V2.2D, V5.2D, V27.D[0]

(306) 0x41731c FMLA	V2.2D, V23.2D, V1.D[0]

(306) 0x417320 LDP	Q23, Q0, [SP, #128]

(306) 0x417324 FADD	V1.2D, V2.2D, V0.2D

(306) 0x417328 ORR	V2.16B, V3.16B, V3.16B

(306) 0x41732c LDP	Q5, Q3, [SP, #560]

(306) 0x417330 FMLA	V18.2D, V1.2D, V19.2D

(306) 0x417334 LDR	D1, [X14, X3,SXTW #3]

(306) 0x417338 FMLA	V2.2D, V9.2D, V17.D[0]

(306) 0x41733c LD1	{V1.D[1]}, [X4]

(306) 0x417340 FMLA	V4.2D, V2.2D, V1.2D

(306) 0x417344 FMUL	V2.2D, V6.2D, V23.D[0]

(306) 0x417348 LDPSW	W3, W4, [X0, #504]

(306) 0x41734c ADD	X5, X10, X4,LSL #3

(306) 0x417350 STR	D18, [X8, X3,LSL #3]

(306) 0x417354 STR	D2, [X10, X3,LSL #3]

(306) 0x417358 ST1	{V2.D[1]}, [X5]

(306) 0x41735c FMUL	V2.2D, V4.2D, V23.D[0]

(306) 0x417360 FMUL	V4.2D, V21.2D, V29.D[0]

(306) 0x417364 FDIV	V4.2D, V4.2D, V3.2D

(306) 0x417368 LDPSW	W5, W6, [X0], #16

(306) 0x41736c ADD	X7, X10, X6,LSL #3

(306) 0x417370 STR	D2, [X10, X5,LSL #3]

(306) 0x417374 ST1	{V2.D[1]}, [X7]

(306) 0x417378 FMUL	V2.2D, V13.2D, V7.D[0]

(306) 0x41737c ADD	X7, X9, X4,LSL #3

(306) 0x417380 FMLA	V2.2D, V9.2D, V10.D[0]

(306) 0x417384 FADD	V2.2D, V2.2D, V11.2D

(306) 0x417388 FMLA	V16.2D, V2.2D, V1.2D

(306) 0x41738c FMUL	V2.2D, V16.2D, V29.D[0]

(306) 0x417390 FDIV	V2.2D, V2.2D, V5.2D

(306) 0x417394 STR	D4, [X9, X3,LSL #3]

(306) 0x417398 ST1	{V4.D[1]}, [X7]

(306) 0x41739c ADD	X7, X9, X6,LSL #3

(306) 0x4173a0 ADD	X3, X8, X4,LSL #3

(306) 0x4173a4 ST1	{V18.D[1]}, [X3]

(306) 0x4173a8 ADD	X3, X8, X6,LSL #3

(306) 0x4173ac STR	D2, [X9, X5,LSL #3]

(306) 0x4173b0 ST1	{V2.D[1]}, [X7]

(306) 0x4173b4 LDP	Q4, Q2, [SP, #752]

(306) 0x4173b8 FMUL	V2.2D, V28.2D, V2.D[0]

(306) 0x4173bc FMLA	V2.2D, V13.2D, V4.D[0]

(306) 0x4173c0 LDR	Q4, [SP, #736]

(306) 0x4173c4 FMLA	V2.2D, V9.2D, V4.D[0]

(306) 0x4173c8 FADD	V2.2D, V2.2D, V0.2D

(306) 0x4173cc FMLA	V22.2D, V2.2D, V1.2D

(306) 0x4173d0 STR	D22, [X8, X5,LSL #3]

(306) 0x4173d4 ST1	{V22.D[1]}, [X3]

(306) 0x4173d8 B.NE	4170c0

0x4173dc LDP	Q12, Q17, [SP, #368]

0x4173e0 LDP	Q28, Q8, [SP, #336]

0x4173e4 ORR	V3.16B, V10.16B, V10.16B

0x4173e8 LDR	Q11, [SP, #400]

0x4173ec LDR	Q0, [SP, #480]

0x4173f0 LDP	Q15, Q10, [SP, #416]

0x4173f4 LDP	Q9, Q31, [SP, #96]

0x4173f8 LDP	Q20, Q29, [SP, #64]

0x4173fc LDP	Q26, Q27, [SP, #448]

0x417400 LDP	Q22, Q30, [SP, #32]

0x417404 LDP	Q25, Q13, [SP]

0x417408 CMP	X18, X17

0x41740c B.EQ	417570

0x417410 ADD	X16, X16, X18,LSL #2

0x417414 ADD	X15, X15, X18,LSL #3

0x417418 SUB	X17, X17, X18

0x41741c HINT	#0

(307) 0x417420 LDR	D1, [X15], #8

(307) 0x417424 ORR	V14.16B, V3.16B, V3.16B

(307) 0x417428 ORR	V3.16B, V7.16B, V7.16B

(307) 0x41742c ORR	V7.16B, V17.16B, V17.16B

(307) 0x417430 LDP	Q17, Q19, [SP, #528]

(307) 0x417434 SUBS	X17, X17, #1

(307) 0x417438 FMUL	D2, D1, D0

(307) 0x41743c FCVTZS	W18, D2

(307) 0x417440 FRINTZ	D4, D2

(307) 0x417444 FSUB	D2, D2, S4

(307) 0x417448 LDR	D6, [X11, X18,SXTW #3]

(307) 0x41744c LDR	D16, [X12, X18,SXTW #3]

(307) 0x417450 FMADD	D18, D24, D2, D19

(307) 0x417454 FMADD	D19, D12, D2, D17

(307) 0x417458 FMUL	D4, D2, D2

(307) 0x41745c LDR	Q17, [SP, #592]

(307) 0x417460 FMUL	D5, D4, D2

(307) 0x417464 FMUL	D18, D18, D6

(307) 0x417468 FMADD	D18, D19, D16, D18

(307) 0x41746c LDP	Q21, Q19, [SP, #704]

(307) 0x417470 FMUL	D19, D19, D4

(307) 0x417474 FMADD	D19, D21, D2, D19

(307) 0x417478 FMUL	D21, D10, D4

(307) 0x41747c FMADD	D21, D8, D2, D21

(307) 0x417480 FADD	D19, D19, D31

(307) 0x417484 FADD	D21, D21, D9

(307) 0x417488 FMUL	D19, D19, D6

(307) 0x41748c FMADD	D19, D21, D16, D19

(307) 0x417490 FMUL	D21, D17, D5

(307) 0x417494 LDR	Q17, [SP, #608]

(307) 0x417498 FMADD	D21, D17, D4, D21

(307) 0x41749c LDR	Q17, [SP, #624]

(307) 0x4174a0 FMADD	D21, D27, D2, D21

(307) 0x4174a4 FADD	D21, D21, D30

(307) 0x4174a8 FMUL	D6, D21, D6

(307) 0x4174ac FMUL	D21, D11, D5

(307) 0x4174b0 FMADD	D21, D17, D4, D21

(307) 0x4174b4 LDR	Q17, [SP, #512]

(307) 0x4174b8 FMADD	D21, D15, D2, D21

(307) 0x4174bc FADD	D21, D21, D22

(307) 0x4174c0 FMADD	D6, D21, D16, D6

(307) 0x4174c4 LDR	Q21, [SP, #656]

(307) 0x4174c8 LDR	D16, [X13, X18,SXTW #3]

(307) 0x4174cc FMADD	D21, D21, D2, D17

(307) 0x4174d0 LDR	Q17, [SP, #640]

(307) 0x4174d4 FMADD	D18, D21, D16, D18

(307) 0x4174d8 FMUL	D21, D28, D4

(307) 0x4174dc FMADD	D21, D17, D2, D21

(307) 0x4174e0 LDR	Q17, [SP, #672]

(307) 0x4174e4 FADD	D21, D21, D29

(307) 0x4174e8 FMADD	D19, D21, D16, D19

(307) 0x4174ec FMUL	D21, D26, D5

(307) 0x4174f0 FMADD	D21, D17, D4, D21

(307) 0x4174f4 LDR	Q17, [SP, #688]

(307) 0x4174f8 FMADD	D21, D17, D2, D21

(307) 0x4174fc LDR	Q17, [SP, #496]

(307) 0x417500 FADD	D21, D21, D13

(307) 0x417504 FMADD	D6, D21, D16, D6

(307) 0x417508 LDR	D16, [X14, X18,SXTW #3]

(307) 0x41750c FMADD	D21, D7, D2, D17

(307) 0x417510 ORR	V17.16B, V7.16B, V7.16B

(307) 0x417514 ORR	V7.16B, V3.16B, V3.16B

(307) 0x417518 ORR	V3.16B, V14.16B, V14.16B

(307) 0x41751c LDRSW	X18, [X16], #4

(307) 0x417520 FMADD	D18, D21, D16, D18

(307) 0x417524 FMUL	D21, D7, D4

(307) 0x417528 FMADD	D21, D3, D2, D21

(307) 0x41752c FADD	D21, D21, D20

(307) 0x417530 FMADD	D19, D21, D16, D19

(307) 0x417534 LDR	Q21, [SP, #768]

(307) 0x417538 FMUL	D5, D21, D5

(307) 0x41753c LDR	Q21, [SP, #752]

(307) 0x417540 FMADD	D4, D21, D4, D5

(307) 0x417544 LDR	Q5, [SP, #736]

(307) 0x417548 FMADD	D2, D5, D2, D4

(307) 0x41754c FMUL	D4, D23, D18

(307) 0x417550 STR	D4, [X10, X18,LSL #3]

(307) 0x417554 FMUL	D4, D19, D0

(307) 0x417558 FADD	D2, D2, D25

(307) 0x41755c FDIV	D1, D4, D1

(307) 0x417560 FMADD	D2, D2, D16, D6

(307) 0x417564 STR	D2, [X8, X18,LSL #3]

(307) 0x417568 STR	D1, [X9, X18,LSL #3]

(307) 0x41756c B.NE	417420

0x417570 ADD	SP, SP, #784

0x417574 LDP	D9, D8, [SP, #48]

0x417578 LDP	D11, D10, [SP, #32]

0x41757c LDP	D13, D12, [SP, #16]

0x417580 LDP	X29, X19, [SP, #64]

0x417584 LDP	D15, D14, [SP], #80

0x417588 RET

0x41758c HINT	#0

Coverage (%)	Name	Source Location	Module
►58.22+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so
►34.32+	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main.omp_outlined.63	miniqmc.cpp:450	exec
○	__kmp_invoke_microtask		libomp.so
►5.17+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so
►2.22+	miniqmcreference::OneBodyJastr[...]	OneBodyJastrowRef.h:260	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main.omp_outlined.63	miniqmc.cpp:442	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run armclang_3

Source file and lines	BsplineFunctor.h:284-339
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1150
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:284,291-339

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 26.50 to 24.67 cycles (1.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is partially vectorized. 84% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 26.50 to 24.50 cycles (1.08x speedup).

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.
96% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
64% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 840 bytes. The binary function is storing 832 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.83	4.83	4.83	4.83	4.83	4.83	15.00	15.00	11.50	11.50	26.50	26.17	26.33	0.50	0.50
cycles	3.50	3.50	4.83	4.83	4.83	4.83	4.83	4.83	15.00	15.00	11.50	11.50	26.50	26.17	26.33	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Overall L1	26.50

Vectorization ratios

INT

all	70%
load	75%
store	96%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	64%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	69%
load	75%
store	96%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	64%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.50 cycles. At this rate:

33% of peak load performance is reached (31.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
65% of peak store performance is reached (31.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 416ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB W11, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417588 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB SP, SP, #784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D0, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X16, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X10, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W14, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W18, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X4, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X15, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X5, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X6, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X7, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMUL D23, D0, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 416f2c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
CMP W18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417570 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Q0, [SP, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP D24, D1, [X0, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ORR W17, WZR, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D12, D0, [X0, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D4, D6, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D31, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D11, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D28, D14, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D15, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D20, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D7, D10, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D3, D17, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D27, D30, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D2, D21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D5, D22, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D26, D18, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D16, D13, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X11, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP Q0, Q1, [SP, #528]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDP D29, D1, [X0, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D9, D0, [X0, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q19, [SP, #768]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D19, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STP Q0, Q1, [SP, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDP D8, D1, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q3, Q17, [SP, #592]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q21, Q14, [SP, #624]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q29, Q18, [SP, #656]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q16, Q6, [SP, #688]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STR Q19, [SP, #752]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP D19, D0, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q4, Q19, [SP, #720]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CMP W18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.HI 41701c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V25.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Q0, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ORR V3.16B, V10.16B, V10.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V10.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V8.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X18, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR V17.16B, V9.16B, V9.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V9.16B, V11.16B, V11.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V29.16B, V15.16B, V15.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V11.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V15.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
B 417410 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q19, Q4, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDR Q29, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q28, Q1, [SP, #336]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
AND X18, X17, #5950	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X1, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP Q5, Q8, [SP, #416]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Q25, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q14, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP V3.2D, V4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q0, Q13, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V0.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q22, Q30, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q20, Q15, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q11, Q31, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q12, Q9, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V19.2D, V19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDP Q19, Q1, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
STP Q26, Q27, [SP, #448]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STR Q2, [SP, #400]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q23, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP V3.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V3.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V11.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V3.2D, V15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V3.2D, V30.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V19.2D, V13.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Q8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q0, Q19, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP Q12, Q17, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q28, Q8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ORR V3.16B, V10.16B, V10.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Q11, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q0, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP Q15, Q10, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q9, Q31, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q20, Q29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q26, Q27, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q22, Q30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q25, Q13, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
CMP X18, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 417570 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X16, X18,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X15, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X17, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
ADD SP, SP, #784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X29, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP D15, D14, [SP], #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.04% of application time for run armclang_3

Source file and lines	BsplineFunctor.h:284-339
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1150
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:284,291-339

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

69% of VPU instructions are used in vector version (process two or more data elements in vector registers):

75% of VPU loads are used in vector version.
96% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
64% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function is composed of 1 FP arithmetical operations:

1: multiply

The binary function is loading 840 bytes. The binary function is storing 832 bytes.

Arithmetic intensity

Arithmetic intensity is 0.00 FP operations per loaded or stored byte.

General properties

nb instructions	142
loop length	568
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.50	3.50	4.83	4.83	4.83	4.83	4.83	4.83	15.00	15.00	11.50	11.50	26.50	26.17	26.33	0.50	0.50
cycles	3.50	3.50	4.83	4.83	4.83	4.83	4.83	4.83	15.00	15.00	11.50	11.50	26.50	26.17	26.33	0.50	0.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	17.00
Overall L1	26.50

Vectorization ratios

INT

all	70%
load	75%
store	96%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	64%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

INT+FP

all	69%
load	75%
store	96%
mul	0%
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	64%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 26.50 cycles. At this rate:

33% of peak load performance is reached (31.70 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
65% of peak store performance is reached (31.40 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 416ec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB W11, W3, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W11, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417588 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D15, D14, [SP, #944]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SUB SP, SP, #784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR D0, [X0, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D1, [X0, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X16, [SP, #872]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X10, X2, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SUB W14, W1, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X12, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W18, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X13, X4, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X15, [SP, #864]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X8, X5, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X9, X6, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X10, X7, X10	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMUL D23, D0, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
B 416f2c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
CMP W18, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 417570 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR D19, [X0, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR Q0, [SP, #480]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP D24, D1, [X0, #296]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ORR W17, WZR, W18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDP D12, D0, [X0, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D4, D6, [X0, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D31, [X0, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D11, [X0, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D28, D14, [X0, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D15, [X0, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D20, [X0, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP D7, D10, [X0, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D3, D17, [X0, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D27, D30, [X0, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D2, D21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D5, D22, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D26, D18, [X0, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D16, D13, [X0, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR X11, [X0, #536]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X12, X11, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X14, X11, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP Q0, Q1, [SP, #528]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDP D29, D1, [X0, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D9, D0, [X0, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STR Q19, [SP, #768]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR D19, [X0, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STP Q0, Q1, [SP, #496]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDP D8, D1, [X0, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q3, Q17, [SP, #592]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q21, Q14, [SP, #624]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q29, Q18, [SP, #656]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q16, Q6, [SP, #688]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STR Q19, [SP, #752]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDP D19, D0, [X0, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q4, Q19, [SP, #720]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
CMP W18, #3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.HI 41701c <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V25.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Q0, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
ORR V3.16B, V10.16B, V10.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V10.16B, V8.16B, V8.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V8.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR X18, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR V17.16B, V9.16B, V9.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V9.16B, V11.16B, V11.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V29.16B, V15.16B, V15.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V11.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
ORR V15.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
B 417410 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x550>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP Q19, Q4, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDR Q29, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q28, Q1, [SP, #336]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
AND X18, X17, #5950	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, X16, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X2, XZR, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X1, XZR, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP Q5, Q8, [SP, #416]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDR Q25, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q14, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
DUP V3.2D, V4.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q0, Q13, [SP]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V0.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q22, Q30, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q20, Q15, [SP, #64]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q11, Q31, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STP Q12, Q9, [SP, #368]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V19.2D, V19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
LDP Q19, Q1, [SP, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
STP Q26, Q27, [SP, #448]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
STR Q2, [SP, #400]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR Q23, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
DUP V3.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V19.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #272]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V3.2D, V31.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V11.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #240]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V3.2D, V15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V20.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #208]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V3.2D, V30.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V19.2D, V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
STP Q19, Q3, [SP, #176]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
DUP V19.2D, V13.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Q8, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
STP Q0, Q19, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDP Q12, Q17, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q28, Q8, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
ORR V3.16B, V10.16B, V10.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDR Q11, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR Q0, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP Q15, Q10, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q9, Q31, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q20, Q29, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q26, Q27, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q22, Q30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
LDP Q25, Q13, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.67	vect (100.0%)
CMP X18, X17	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 417570 <_ZNK11qmcplusplus14BsplineFunctorIdE11evaluateVGLEiiiPKdPdS4_S4_S4_Pi+0x6b0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X16, X16, X18,LSL #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X15, X15, X18,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X17, X17, X18	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
HINT #0																					N/A
ADD SP, SP, #784	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D9, D8, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D11, D10, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D13, D12, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP X29, X19, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP D15, D14, [SP], #80	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::BsplineFunctor::evaluateVGL(int, int, int, double const, double, double, double, double, int) const–	0.51	0.71
○Loop 308 - BsplineFunctor.h:291-298 - exec	0.42	0.58
○Loop 306 - BsplineFunctor.h:302-336 - exec	0.04	0.06
○Loop 307 - BsplineFunctor.h:302-336 - exec	0.00	0.01

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