OV - exec - Function qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSet&)

	Function: qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSe ...	Module: exec	Source: SoaDistanceTableABOMPTarget.h:184-233 [...]	Coverage (incl. loops): 5.17% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

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242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 248 - 248

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248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

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280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h: 1131 - 1131

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1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp: 38 - 38

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38:   return a < b ? a : b;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 267 - 267

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267:   inline const T* data() const { return myData; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

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193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 184 - 233

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184:   {

185:     resize();

186:

187:     ScopedTimer local_timer(evaluate_timer_);

188:     // be aware of the sign of Displacement

189:     const int num_targets_local = num_targets_;

190:     const int num_sources_local = num_sources_;

191:     const int num_padded        = getAlignedSize<T>(num_sources_);

192:

193:     target_pos.resize(num_targets_ * D);

194:     for (size_t iat = 0; iat < num_targets_; iat++)

195:       for (size_t idim = 0; idim < D; idim++)

196:         target_pos[iat * D + idim] = P.R[iat][idim];

197:

198:     auto* target_pos_ptr = target_pos.data();

199:     auto* source_pos_ptr = origin_.getCoordinates().getAllParticlePos().data();

[...]

205:     const size_t num_teams     = (num_sources_ + ChunkSizePerTeam - 1) / ChunkSizePerTeam;

206:     const size_t stride_size   = getPerTargetPctlStrideSize();

207:

208:     {

209:       ScopedTimer offload(offload_timer_);

210:       PRAGMA_OFFLOAD("omp target teams distribute collapse(2) num_teams(num_targets_*num_teams) \

211:                         map(to: source_pos_ptr[:num_padded*D]) \

212:                         map(always, to: target_pos_ptr[:num_targets_*D]) \

213:                         map(always, from: r_dr_ptr[:num_targets_*stride_size])")

214:       for (int iat = 0; iat < num_targets_local; ++iat)

215:         for (int team_id = 0; team_id < num_teams; team_id++)

216:         {

217:           const int first = ChunkSizePerTeam * team_id;

[...]

228:           for (int iel = first; iel < last; iel++)

229:             DTD_BConds<T, D, SC>::computeDistancesOffload(pos, source_pos_ptr, num_padded, r_iat_ptr, dr_iat_ptr,

230:                                                           num_padded, iel);

231:         }

232:     }

233:   }

0x49d4c0 STR	D12, [SP, #368]!

0x49d4c4 STP	D11, D10, [SP, #16]

0x49d4c8 STP	D9, D8, [SP, #32]

0x49d4cc STP	X29, X30, [SP, #48]

0x49d4d0 STP	X28, X27, [SP, #64]

0x49d4d4 STP	X26, X25, [SP, #80]

0x49d4d8 STP	X24, X23, [SP, #96]

0x49d4dc STP	X22, X21, [SP, #112]

0x49d4e0 STP	X20, X19, [SP, #128]

0x49d4e4 ADD	X29, SP, #48

0x49d4e8 SUB	SP, SP, #400

0x49d4ec ORR	X21, XZR, X1

0x49d4f0 ORR	X23, XZR, X0

0x49d4f4 BL	49f120

0x49d4f8 LDR	X20, [X23, #440]

0x49d4fc ORR	X0, XZR, X20

0x49d500 BL	469040

0x49d504 LDP	X8, X24, [X23, #16]

0x49d508 STUR	X8, [X29, #400]

0x49d50c MOVI	D0, #0

0x49d510 ADD	X0, X23, #384

0x49d514 ADD	X1, X24, X24,LSL #1

0x49d518 STR	X20, [SP, #8]

0x49d51c BL	43c4e0

0x49d520 LDR	X9, [X23, #24]

0x49d524 CBZ	X9, 49d584

0x49d528 LDR	X8, [X21, #64]

0x49d52c LDR	X15, [X23, #408]

0x49d530 ORR	X10, XZR, XZR

0x49d534 STR	X15, [SP, #160]

0x49d538 CMP	X9, #18

0x49d53c B.CS	49d62c

      (2231) 0x49d540 MOVZ	W11, #24

      (2231) 0x49d544 MOVZ	X12, #16

      (2231) 0x49d548 SUB	X9, X9, X10

      (2231) 0x49d54c MADD	X11, X10, X11, X12

      (2231) 0x49d550 ADD	X10, X15, X11

      (2231) 0x49d554 ADD	X8, X8, X11

      (2231) 0x49d558 HINT	#0

      (2231) 0x49d55c HINT	#0

        (2230) 0x49d560 LDUR	D0, [X8, #496]

        (2230) 0x49d564 SUBS	X9, X9, #1

        (2230) 0x49d568 STUR	D0, [X10, #496]

        (2230) 0x49d56c LDUR	D0, [X8, #504]

        (2230) 0x49d570 STUR	D0, [X10, #504]

        (2230) 0x49d574 LDR	D0, [X8], #24

        (2230) 0x49d578 STR	D0, [X10], #24

        (2230) 0x49d57c B.NE	49d560

      (2231) 0x49d580 B	49d58c

0x49d584 LDR	X8, [X23, #408]

0x49d588 STR	X8, [SP, #160]

      (2231) 0x49d58c LDR	X8, [X23, #8]

      (2231) 0x49d590 LDR	X0, [X8, #632]

      (2231) 0x49d594 LDR	X8, [X0]

      (2231) 0x49d598 LDR	X8, [X8, #72]

      (2231) 0x49d59c BLR	X8

      (2231) 0x49d5a0 LDR	X8, [X23, #72]

      (2231) 0x49d5a4 LDR	X26, [X0, #24]

      (2231) 0x49d5a8 LDR	X20, [X23, #16]

      (2231) 0x49d5ac LDR	X8, [X8, #24]

      (2231) 0x49d5b0 STR	X8, [SP, #96]

      (2231) 0x49d5b4 LDR	X8, [X23]

      (2231) 0x49d5b8 LDR	X8, [X8, #136]

      (2231) 0x49d5bc ORR	X0, XZR, X23

      (2231) 0x49d5c0 BLR	X8

      (2231) 0x49d5c4 ORR	X22, XZR, X0

      (2231) 0x49d5c8 LDR	X0, [X23, #432]

      (2231) 0x49d5cc STR	X23, [SP, #88]

      (2231) 0x49d5d0 STR	X0, [SP]

      (2231) 0x49d5d4 BL	469040

      (2231) 0x49d5d8 LDR	X3, [SP, #160]

      (2231) 0x49d5dc CMP	W24, #1

      (2231) 0x49d5e0 B.LT	49d5f0

      (2231) 0x49d5e4 ADD	X8, X20, #511

      (2231) 0x49d5e8 CMP	X8, #512

      (2231) 0x49d5ec B.CS	49d6a0

      (2231) 0x49d5f0 LDR	X0, [SP]

      (2231) 0x49d5f4 BL	469160

      (2231) 0x49d5f8 LDR	X0, [SP, #8]

      (2231) 0x49d5fc BL	469160

      (2231) 0x49d600 ADD	SP, SP, #400

      (2231) 0x49d604 LDP	D9, D8, [SP, #32]

      (2231) 0x49d608 LDP	D11, D10, [SP, #16]

      (2231) 0x49d60c LDP	X20, X19, [SP, #128]

      (2231) 0x49d610 LDP	X22, X21, [SP, #112]

      (2231) 0x49d614 LDP	X24, X23, [SP, #96]

      (2231) 0x49d618 LDP	X26, X25, [SP, #80]

      (2231) 0x49d61c LDP	X28, X27, [SP, #64]

      (2231) 0x49d620 LDP	X29, X30, [SP, #48]

      (2231) 0x49d624 LDR	D12, [SP], #144

      (2231) 0x49d628 RET

      (2231) 0x49d62c SUB	X12, X9, #1

      (2231) 0x49d630 MOVZ	W11, #24

      (2231) 0x49d634 ADD	X13, X15, #8

      (2231) 0x49d638 UMULH	X11, X12, X11

      (2231) 0x49d63c ADD	X12, X12, X12,LSL #1

      (2231) 0x49d640 ADD	X14, X13, X12,LSL #3

      (2231) 0x49d644 CMP	XZR, X11

      (2231) 0x49d648 CSINC	W11, WZR, WZR, #0

      (2231) 0x49d64c CMP	X14, X13

      (2231) 0x49d650 B.CC	49d540

      (2231) 0x49d654 TBNZ	W11, #0, 49d540

      (2231) 0x49d658 ADD	X13, X15, #16

      (2231) 0x49d65c ADD	X14, X13, X12,LSL #3

      (2231) 0x49d660 CMP	X14, X13

      (2231) 0x49d664 B.CC	49d540

      (2231) 0x49d668 TBNZ	W11, #0, 49d540

      (2231) 0x49d66c ADD	X12, X15, X12,LSL #3

      (2231) 0x49d670 CMP	X12, X15

      (2231) 0x49d674 B.CC	49d540

      (2231) 0x49d678 TBNZ	W11, #0, 49d540

      (2231) 0x49d67c ADD	X10, X9, X9,LSL #1

      (2231) 0x49d680 ADD	X11, X8, X10,LSL #3

      (2231) 0x49d684 CMP	X15, X11

      (2231) 0x49d688 B.CS	49dd70

      (2231) 0x49d68c ADD	X10, X15, X10,LSL #3

      (2231) 0x49d690 CMP	X8, X10

      (2231) 0x49d694 B.CS	49dd70

      (2231) 0x49d698 ORR	X10, XZR, XZR

      (2231) 0x49d69c B	49d540

    (2232) 0x49d6a0 LDUR	X16, [X29, #400]

    (2232) 0x49d6a4 UBFM	X17, X22, #61, #60

    (2232) 0x49d6a8 LDR	X22, [SP, #96]

    (2232) 0x49d6ac UBFM	X20, X8, #9, #63

    (2232) 0x49d6b0 ORR	X12, XZR, XZR

    (2232) 0x49d6b4 STR	X20, [SP, #152]

    (2232) 0x49d6b8 ADD	X9, X16, #3

    (2232) 0x49d6bc SBFM	X23, X16, #0, #31

    (2232) 0x49d6c0 AND	X9, X9, #8062

    (2232) 0x49d6c4 UBFM	X8, X9, #32, #31

    (2232) 0x49d6c8 SBFM	X13, X9, #61, #31

    (2232) 0x49d6cc SBFM	X14, X9, #0, #31

    (2232) 0x49d6d0 ADD	X10, X26, W9,SXTW #3

    (2232) 0x49d6d4 UBFM	W9, W9, #31, #30

    (2232) 0x49d6d8 SBFM	X15, X9, #0, #31

    (2232) 0x49d6dc ADD	X11, X26, W9,SXTW #3

    (2232) 0x49d6e0 AND	X9, X24, #6016

    (2232) 0x49d6e4 SBFM	X8, X8, #29, #63

    (2232) 0x49d6e8 ADD	X28, X22, X13

    (2232) 0x49d6ec STR	X9, [SP, #80]

    (2232) 0x49d6f0 ADD	X9, X8, X13

    (2232) 0x49d6f4 ADD	X16, X13, X15,LSL #3

    (2232) 0x49d6f8 ADD	X18, X28, #8

    (2232) 0x49d6fc ADD	X8, X26, X8

    (2232) 0x49d700 STP	X28, X17, [SP, #64]

    (2232) 0x49d704 ADD	X9, X22, X9

    (2232) 0x49d708 ADD	X27, X22, X16

    (2232) 0x49d70c STP	X8, X23, [SP, #136]

    (2232) 0x49d710 STP	X9, X18, [SP, #48]

    (2232) 0x49d714 ADD	X9, X9, #8

    (2232) 0x49d718 STR	X9, [SP, #40]

    (2232) 0x49d71c ADD	X9, X27, #8

    (2232) 0x49d720 STP	X9, X27, [SP, #24]

    (2232) 0x49d724 ADD	X9, X22, #8

    (2232) 0x49d728 STR	X9, [SP, #16]

    (2232) 0x49d72c ADD	X9, X8, #8

    (2232) 0x49d730 ADD	X8, X26, X15,LSL #3

    (2232) 0x49d734 STP	X8, X9, [SP, #120]

    (2232) 0x49d738 ADD	X8, X8, #8

    (2232) 0x49d73c STR	X8, [SP, #112]

    (2232) 0x49d740 ADD	X8, X13, X14,LSL #3

    (2232) 0x49d744 ADD	X7, X22, X8

    (2232) 0x49d748 B	49d770

    (2232) 0x49d74c LDR	X12, [SP, #104]

    (2232) 0x49d750 LDP	X17, X8, [SP, #72]

    (2232) 0x49d754 ADD	X12, X12, #1

    (2232) 0x49d758 ADD	X28, X28, X17

    (2232) 0x49d75c ADD	X7, X7, X17

    (2232) 0x49d760 ADD	X27, X27, X17

    (2232) 0x49d764 ADD	X22, X22, X17

    (2232) 0x49d768 CMP	X12, X8

    (2232) 0x49d76c B.EQ	49d5f0

    (2232) 0x49d770 ADD	W13, W12, W12,LSL #1

    (2232) 0x49d774 MADD	X8, X17, X12, XZR

    (2232) 0x49d778 STR	X12, [SP, #104]

    (2232) 0x49d77c LDR	X9, [SP, #88]

    (2232) 0x49d780 MOVZ	W18, #512

    (2232) 0x49d784 MOVZ	W0, #1

    (2232) 0x49d788 ORR	X16, XZR, XZR

    (2232) 0x49d78c ORR	X19, XZR, XZR

    (2232) 0x49d790 ORR	X14, XZR, XZR

    (2232) 0x49d794 ORR	X6, XZR, X22

    (2232) 0x49d798 ORR	X5, XZR, X27

    (2232) 0x49d79c ORR	X1, XZR, X28

    (2232) 0x49d7a0 ORR	X2, XZR, X11

    (2232) 0x49d7a4 ORR	X17, XZR, X10

    (2232) 0x49d7a8 ORR	X25, XZR, X26

    (2232) 0x49d7ac ADD	W12, W13, #1

    (2232) 0x49d7b0 STP	W12, W13, [X29, #416]

    (2232) 0x49d7b4 ADD	W12, W13, #2

    (2232) 0x49d7b8 STUR	W12, [X29, #412]

    (2232) 0x49d7bc LDR	X12, [SP, #64]

    (2232) 0x49d7c0 LDP	D0, D1, [X9, #280]

    (2232) 0x49d7c4 LDP	D2, D3, [X9, #296]

    (2232) 0x49d7c8 LDP	D4, D5, [X9, #312]

    (2232) 0x49d7cc LDP	D6, D7, [X9, #328]

    (2232) 0x49d7d0 ADD	X12, X12, X8

    (2232) 0x49d7d4 LDP	D16, D17, [X9, #200]

    (2232) 0x49d7d8 LDP	D18, D19, [X9, #216]

    (2232) 0x49d7dc LDP	D20, D21, [X9, #232]

    (2232) 0x49d7e0 LDP	D22, D23, [X9, #248]

    (2232) 0x49d7e4 LDP	D25, D24, [X9, #264]

    (2232) 0x49d7e8 STR	X12, [SP, #224]

    (2232) 0x49d7ec LDR	X12, [SP, #56]

    (2232) 0x49d7f0 ADD	X12, X12, X8

    (2232) 0x49d7f4 STR	X12, [SP, #216]

    (2232) 0x49d7f8 LDR	X12, [SP, #48]

    (2232) 0x49d7fc ADD	X12, X12, X8

    (2232) 0x49d800 STR	X12, [SP, #208]

    (2232) 0x49d804 LDR	X12, [SP, #40]

    (2232) 0x49d808 ADD	X12, X12, X8

    (2232) 0x49d80c STR	X12, [SP, #200]

    (2232) 0x49d810 LDR	X12, [SP, #32]

    (2232) 0x49d814 ADD	X12, X12, X8

    (2232) 0x49d818 STR	X12, [SP, #192]

    (2232) 0x49d81c LDR	X12, [SP, #24]

    (2232) 0x49d820 ADD	X12, X12, X8

    (2232) 0x49d824 STR	X12, [SP, #184]

    (2232) 0x49d828 LDR	X12, [SP, #96]

    (2232) 0x49d82c ADD	X12, X12, X8

    (2232) 0x49d830 STR	X12, [SP, #176]

    (2232) 0x49d834 LDR	X12, [SP, #16]

    (2232) 0x49d838 ADD	X8, X12, X8

    (2232) 0x49d83c STR	X8, [SP, #168]

    (2232) 0x49d840 ORR	X8, XZR, X7

    (2232) 0x49d844 B	49d884

    (2232) 0x49d848 ADD	X9, X19, #1

    (2232) 0x49d84c ADD	X14, X14, #512

    (2232) 0x49d850 ADD	W18, W18, #512

    (2232) 0x49d854 ADD	X0, X0, #512

    (2232) 0x49d858 SUB	X16, X16, #512

    (2232) 0x49d85c ADD	X25, X25, #1

    (2232) 0x49d860 ORR	X19, XZR, X9

    (2232) 0x49d864 ADD	X17, X17, #1

    (2232) 0x49d868 ADD	X2, X2, #1

    (2232) 0x49d86c ADD	X1, X1, #1

    (2232) 0x49d870 ADD	X8, X8, #1

    (2232) 0x49d874 ADD	X5, X5, #1

    (2232) 0x49d878 ADD	X6, X6, #1

    (2232) 0x49d87c CMP	X9, X20

    (2232) 0x49d880 B.EQ	49d74c

    (2232) 0x49d884 SBFM	X9, X18, #0, #31

    (2232) 0x49d888 ORR	X13, X14, #4096

    (2232) 0x49d88c CMP	X9, X23

    (2232) 0x49d890 CSEL	X9, X9, X23, #11

    (2232) 0x49d894 CMP	X9, X0

    (2232) 0x49d898 CSEL	X4, X9, X0, #12

    (2232) 0x49d89c ADD	W9, W14, #512

    (2232) 0x49d8a0 SBFM	X9, X9, #0, #31

    (2232) 0x49d8a4 CMP	X9, X23

    (2232) 0x49d8a8 CSEL	X9, X9, X23, #11

    (2232) 0x49d8ac CMP	X9, X13

    (2232) 0x49d8b0 CSINC	X9, X9, X14, #12

    (2232) 0x49d8b4 STUR	X9, [X29, #472]

    (2232) 0x49d8b8 UBFM	X9, X19, #55, #54

    (2232) 0x49d8bc CMP	X9, X23

    (2232) 0x49d8c0 B.GE	49d848

  (2234) 0x49d8c4 LDUR	X12, [X29, #472]

  (2234) 0x49d8c8 ORR	X21, XZR, X14

  (2234) 0x49d8cc SUB	X15, X12, X9

  (2234) 0x49d8d0 LDP	W12, W13, [X29, #416]

  (2234) 0x49d8d4 STUR	X15, [X29, #424]

  (2234) 0x49d8d8 LDR	D27, [X3, X12,UXTW #3]

  (2234) 0x49d8dc LDUR	W12, [X29, #412]

  (2234) 0x49d8e0 LDR	D26, [X3, X13,UXTW #3]

  (2234) 0x49d8e4 ADD	W13, W9, #512

  (2234) 0x49d8e8 LDR	D28, [X3, X12,UXTW #3]

  (2234) 0x49d8ec LDUR	X12, [X29, #400]

  (2234) 0x49d8f0 CMP	W13, W12

  (2234) 0x49d8f4 CSEL	W12, W13, W12, #11

  (2234) 0x49d8f8 CMP	X15, #5

  (2234) 0x49d8fc B.HI	49d9c0

  (2234) 0x49d900 SBFM	X9, X12, #0, #31

    (2229) 0x49d904 LDR	D29, [X26, X21,LSL #3]

    (2229) 0x49d908 LDR	D30, [X10, X21,LSL #3]

    (2229) 0x49d90c LDR	D31, [X11, X21,LSL #3]

    (2229) 0x49d910 FSUB	D29, D29, S26

    (2229) 0x49d914 FSUB	D30, D30, S27

    (2229) 0x49d918 FSUB	D31, D31, S28

    (2229) 0x49d91c FMUL	D8, D24, D29

    (2229) 0x49d920 FMUL	D9, D2, D29

    (2229) 0x49d924 FMUL	D29, D5, D29

    (2229) 0x49d928 FMADD	D8, D0, D30, D8

    (2229) 0x49d92c FMADD	D9, D3, D30, D9

    (2229) 0x49d930 FMADD	D29, D6, D30, D29

    (2229) 0x49d934 FMADD	D8, D1, D31, D8

    (2229) 0x49d938 FMADD	D9, D4, D31, D9

    (2229) 0x49d93c FMADD	D29, D7, D31, D29

    (2229) 0x49d940 FRINTA	D30, D8

    (2229) 0x49d944 FRINTA	D31, D9

    (2229) 0x49d948 FSUB	D30, D8, S30

    (2229) 0x49d94c FRINTA	D8, D29

    (2229) 0x49d950 FSUB	D31, D9, S31

    (2229) 0x49d954 FSUB	D29, D29, S8

    (2229) 0x49d958 FMUL	D8, D16, D30

    (2229) 0x49d95c FMADD	D8, D17, D31, D8

    (2229) 0x49d960 FMADD	D8, D29, D18, D8

    (2229) 0x49d964 STR	D8, [X28, X21,LSL #3]

    (2229) 0x49d968 FMUL	D8, D19, D30

    (2229) 0x49d96c FMUL	D30, D22, D30

    (2229) 0x49d970 FMADD	D8, D20, D31, D8

    (2229) 0x49d974 FMADD	D30, D23, D31, D30

    (2229) 0x49d978 FMADD	D8, D21, D29, D8

    (2229) 0x49d97c FMADD	D29, D25, D29, D30

    (2229) 0x49d980 STR	D8, [X7, X21,LSL #3]

    (2229) 0x49d984 STR	D29, [X27, X21,LSL #3]

    (2229) 0x49d988 LDR	D30, [X28, X21,LSL #3]

    (2229) 0x49d98c LDR	D31, [X7, X21,LSL #3]

    (2229) 0x49d990 FMUL	D30, D30, D30

    (2229) 0x49d994 FMADD	D29, D29, D29, D30

    (2229) 0x49d998 FMADD	D29, D31, D31, D29

    (2229) 0x49d99c FSQRT	D29, D29

    (2229) 0x49d9a0 STR	D29, [X22, X21,LSL #3]

    (2229) 0x49d9a4 ADD	X21, X21, #1

    (2229) 0x49d9a8 CMP	X21, X9

    (2229) 0x49d9ac B.LT	49d904

  (2234) 0x49d9b0 B	49d848

0x49d9b4 HINT	#0

0x49d9b8 HINT	#0

0x49d9bc HINT	#0

(2233) 0x49d9c0 STUR	X12, [X29, #432]

(2233) 0x49d9c4 LDR	X12, [SP, #224]

(2233) 0x49d9c8 UBFM	X15, X19, #52, #51

(2233) 0x49d9cc STUR	X19, [X29, #376]

(2233) 0x49d9d0 ORN	X9, XZR, X9

(2233) 0x49d9d4 LDR	X3, [SP, #136]

(2233) 0x49d9d8 ADD	X20, X26, X15

(2233) 0x49d9dc STUR	X16, [X29, #392]

(2233) 0x49d9e0 STUR	X18, [X29, #440]

(2233) 0x49d9e4 ADD	X19, X12, X15

(2233) 0x49d9e8 LDR	X12, [SP, #216]

(2233) 0x49d9ec ADD	X24, X3, X15

(2233) 0x49d9f0 LDR	X3, [SP, #128]

(2233) 0x49d9f4 STUR	X4, [X29, #384]

(2233) 0x49d9f8 ADD	X16, X12, X15

(2233) 0x49d9fc LDUR	X12, [X29, #472]

(2233) 0x49da00 ADD	X3, X3, X15

(2233) 0x49da04 ADD	X9, X12, X9

(2233) 0x49da08 LDR	X12, [SP, #208]

(2233) 0x49da0c ADD	X21, X16, X9,LSL #3

(2233) 0x49da10 ADD	X3, X3, X9,LSL #3

(2233) 0x49da14 ADD	X30, X20, X9,LSL #3

(2233) 0x49da18 STUR	X3, [X29, #448]

(2233) 0x49da1c LDR	X3, [SP, #120]

(2233) 0x49da20 ADD	X30, X30, #8

(2233) 0x49da24 ADD	X13, X12, X15

(2233) 0x49da28 LDR	X12, [SP, #200]

(2233) 0x49da2c ADD	X3, X3, X15

(2233) 0x49da30 STUR	X3, [X29, #360]

(2233) 0x49da34 LDR	X3, [SP, #112]

(2233) 0x49da38 ADD	X16, X12, X15

(2233) 0x49da3c LDR	X12, [SP, #192]

(2233) 0x49da40 ADD	X18, X16, X9,LSL #3

(2233) 0x49da44 ADD	X16, X12, X15

(2233) 0x49da48 LDR	X12, [SP, #184]

(2233) 0x49da4c ADD	X23, X12, X15

(2233) 0x49da50 LDR	X12, [SP, #176]

(2233) 0x49da54 ADD	X23, X23, X9,LSL #3

(2233) 0x49da58 CMP	X19, X23

(2233) 0x49da5c CCMP	X16, X21, #2, #3

(2233) 0x49da60 ADD	X4, X12, X15

(2233) 0x49da64 LDR	X12, [SP, #168]

(2233) 0x49da68 ADD	X12, X12, X15

(2233) 0x49da6c ADD	X15, X3, X15

(2233) 0x49da70 ADD	X12, X12, X9,LSL #3

(2233) 0x49da74 ADD	X9, X15, X9,LSL #3

(2233) 0x49da78 CSINC	W15, WZR, WZR, #2

(2233) 0x49da7c CMP	X19, X12

(2233) 0x49da80 STUR	W15, [X29, #356]

(2233) 0x49da84 ORR	X15, XZR, X19

(2233) 0x49da88 STUR	X19, [X29, #368]

(2233) 0x49da8c CCMP	X4, X21, #2, #3

(2233) 0x49da90 CSINC	W3, WZR, WZR, #2

(2233) 0x49da94 CMP	X19, X30

(2233) 0x49da98 LDUR	X19, [X29, #448]

(2233) 0x49da9c CCMP	X20, X21, #2, #3

(2233) 0x49daa0 STUR	W3, [X29, #352]

(2233) 0x49daa4 CSINC	W3, WZR, WZR, #2

(2233) 0x49daa8 STUR	W3, [X29, #348]

(2233) 0x49daac CMP	X15, X19

(2233) 0x49dab0 CCMP	X24, X21, #2, #3

(2233) 0x49dab4 CSINC	W3, WZR, WZR, #2

(2233) 0x49dab8 CMP	X15, X9

(2233) 0x49dabc LDUR	X15, [X29, #360]

(2233) 0x49dac0 STUR	W3, [X29, #344]

(2233) 0x49dac4 CCMP	X15, X21, #2, #3

(2233) 0x49dac8 CSINC	W3, WZR, WZR, #2

(2233) 0x49dacc CMP	X13, X23

(2233) 0x49dad0 CCMP	X16, X18, #2, #3

(2233) 0x49dad4 STUR	W3, [X29, #340]

(2233) 0x49dad8 CSINC	W3, WZR, WZR, #2

(2233) 0x49dadc CMP	X13, X12

(2233) 0x49dae0 CCMP	X4, X18, #2, #3

(2233) 0x49dae4 STUR	W3, [X29, #336]

(2233) 0x49dae8 CSINC	W3, WZR, WZR, #2

(2233) 0x49daec CMP	X13, X30

(2233) 0x49daf0 CCMP	X20, X18, #2, #3

(2233) 0x49daf4 STUR	W3, [X29, #332]

(2233) 0x49daf8 CSINC	W3, WZR, WZR, #2

(2233) 0x49dafc CMP	X13, X19

(2233) 0x49db00 ORR	X19, XZR, X15

(2233) 0x49db04 CCMP	X24, X18, #2, #3

(2233) 0x49db08 STUR	W3, [X29, #328]

(2233) 0x49db0c CSINC	W3, WZR, WZR, #2

(2233) 0x49db10 CMP	X13, X9

(2233) 0x49db14 CCMP	X15, X18, #2, #3

(2233) 0x49db18 STUR	W3, [X29, #324]

(2233) 0x49db1c LDUR	X15, [X29, #448]

(2233) 0x49db20 CSINC	W3, WZR, WZR, #2

(2233) 0x49db24 CMP	X16, X12

(2233) 0x49db28 CCMP	X4, X23, #2, #3

(2233) 0x49db2c STUR	W3, [X29, #320]

(2233) 0x49db30 CSINC	W3, WZR, WZR, #2

(2233) 0x49db34 CMP	X16, X30

(2233) 0x49db38 CCMP	X20, X23, #2, #3

(2233) 0x49db3c STUR	W3, [X29, #316]

(2233) 0x49db40 CSINC	W3, WZR, WZR, #2

(2233) 0x49db44 CMP	X16, X15

(2233) 0x49db48 CCMP	X24, X23, #2, #3

(2233) 0x49db4c STUR	W3, [X29, #312]

(2233) 0x49db50 CSINC	W3, WZR, WZR, #2

(2233) 0x49db54 CMP	X16, X9

(2233) 0x49db58 CCMP	X19, X23, #2, #3

(2233) 0x49db5c STUR	W3, [X29, #308]

(2233) 0x49db60 LDR	X23, [SP, #144]

(2233) 0x49db64 CSINC	W3, WZR, WZR, #2

(2233) 0x49db68 CMP	X4, X30

(2233) 0x49db6c CCMP	X20, X12, #2, #3

(2233) 0x49db70 STUR	W3, [X29, #304]

(2233) 0x49db74 LDR	X20, [SP, #152]

(2233) 0x49db78 CSINC	W3, WZR, WZR, #2

(2233) 0x49db7c CMP	X4, X15

(2233) 0x49db80 CCMP	X24, X12, #2, #3

(2233) 0x49db84 STUR	W3, [X29, #300]

(2233) 0x49db88 LDR	X3, [SP, #160]

(2233) 0x49db8c CSINC	W30, WZR, WZR, #2

(2233) 0x49db90 CMP	X4, X9

(2233) 0x49db94 LDP	X4, X16, [X29, #896]

(2233) 0x49db98 CCMP	X19, X12, #2, #3

(2233) 0x49db9c CSINC	W9, WZR, WZR, #2

(2233) 0x49dba0 CMP	X13, X21

(2233) 0x49dba4 LDP	X13, X19, [X29, #880]

(2233) 0x49dba8 STUR	W30, [X29, #448]

(2233) 0x49dbac ORR	X21, XZR, X14

(2233) 0x49dbb0 CCMP	X13, X18, #2, #3

(2233) 0x49dbb4 LDP	X12, X18, [X29, #944]

(2233) 0x49dbb8 B.CC	49d900

(2233) 0x49dbbc LDUR	W13, [X29, #356]

(2233) 0x49dbc0 ORR	X21, XZR, X14

(2233) 0x49dbc4 TBNZ	W13, #0, 49d900

(2233) 0x49dbc8 LDUR	W13, [X29, #352]

(2233) 0x49dbcc ORR	X21, XZR, X14

(2233) 0x49dbd0 TBNZ	W13, #0, 49d900

(2233) 0x49dbd4 LDUR	W13, [X29, #348]

(2233) 0x49dbd8 ORR	X21, XZR, X14

(2233) 0x49dbdc TBNZ	W13, #0, 49d900

(2233) 0x49dbe0 LDUR	W13, [X29, #344]

(2233) 0x49dbe4 ORR	X21, XZR, X14

(2233) 0x49dbe8 TBNZ	W13, #0, 49d900

(2233) 0x49dbec LDUR	W13, [X29, #340]

(2233) 0x49dbf0 ORR	X21, XZR, X14

(2233) 0x49dbf4 TBNZ	W13, #0, 49d900

(2233) 0x49dbf8 LDUR	W13, [X29, #336]

(2233) 0x49dbfc ORR	X21, XZR, X14

(2233) 0x49dc00 TBNZ	W13, #0, 49d900

(2233) 0x49dc04 LDUR	W13, [X29, #332]

(2233) 0x49dc08 ORR	X21, XZR, X14

(2233) 0x49dc0c TBNZ	W13, #0, 49d900

(2233) 0x49dc10 LDUR	W13, [X29, #328]

(2233) 0x49dc14 ORR	X21, XZR, X14

(2233) 0x49dc18 TBNZ	W13, #0, 49d900

(2233) 0x49dc1c LDUR	W13, [X29, #324]

(2233) 0x49dc20 ORR	X21, XZR, X14

(2233) 0x49dc24 TBNZ	W13, #0, 49d900

(2233) 0x49dc28 LDUR	W13, [X29, #320]

(2233) 0x49dc2c ORR	X21, XZR, X14

(2233) 0x49dc30 TBNZ	W13, #0, 49d900

(2233) 0x49dc34 LDUR	W13, [X29, #316]

(2233) 0x49dc38 ORR	X21, XZR, X14

(2233) 0x49dc3c TBNZ	W13, #0, 49d900

(2233) 0x49dc40 LDUR	W13, [X29, #312]

(2233) 0x49dc44 ORR	X21, XZR, X14

(2233) 0x49dc48 TBNZ	W13, #0, 49d900

(2233) 0x49dc4c LDUR	W13, [X29, #308]

(2233) 0x49dc50 ORR	X21, XZR, X14

(2233) 0x49dc54 TBNZ	W13, #0, 49d900

(2233) 0x49dc58 LDUR	W13, [X29, #304]

(2233) 0x49dc5c ORR	X21, XZR, X14

(2233) 0x49dc60 TBNZ	W13, #0, 49d900

(2233) 0x49dc64 LDUR	W13, [X29, #300]

(2233) 0x49dc68 ORR	X21, XZR, X14

(2233) 0x49dc6c TBNZ	W13, #0, 49d900

(2233) 0x49dc70 LDUR	W13, [X29, #448]

(2233) 0x49dc74 ORR	X21, XZR, X14

(2233) 0x49dc78 TBNZ	W13, #0, 49d900

(2233) 0x49dc7c ORR	X21, XZR, X14

(2233) 0x49dc80 TBNZ	W9, #0, 49d900

(2233) 0x49dc84 ADD	X9, X4, X16

(2233) 0x49dc88 AND	X12, X4, #4096

(2233) 0x49dc8c DUP	V29.2D, V26.D[0]

(2233) 0x49dc90 DUP	V30.2D, V27.D[0]

(2233) 0x49dc94 DUP	V31.2D, V28.D[0]

(2233) 0x49dc98 ORR	X18, XZR, XZR

(2233) 0x49dc9c SUB	X13, X9, X12

(2233) 0x49dca0 LDUR	X9, [X29, #472]

(2233) 0x49dca4 AND	X4, X9, #4096

(2233) 0x49dca8 LDUR	X9, [X29, #424]

(2233) 0x49dcac SUB	X9, X9, X4

(2233) 0x49dcb0 ADD	X21, X14, X9

(2233) 0x49dcb4 HINT	#0

(2233) 0x49dcb8 HINT	#0

(2233) 0x49dcbc HINT	#0

  (2236) 0x49dcc0 LDR	Q8, [X25, X18]

  (2236) 0x49dcc4 LDR	Q9, [X17, X18]

  (2236) 0x49dcc8 LDR	Q10, [X2, X18]

  (2236) 0x49dccc SUBS	X13, X13, #2

  (2236) 0x49dcd0 FSUB	V8.2D, V8.2D, V29.2D

  (2236) 0x49dcd4 FSUB	V9.2D, V9.2D, V30.2D

  (2236) 0x49dcd8 FSUB	V10.2D, V10.2D, V31.2D

  (2236) 0x49dcdc FMUL	V11.2D, V8.2D, V24.D[0]

  (2236) 0x49dce0 FMUL	V12.2D, V8.2D, V2.D[0]

  (2236) 0x49dce4 FMUL	V8.2D, V8.2D, V5.D[0]

  (2236) 0x49dce8 FMLA	V11.2D, V9.2D, V0.D[0]

  (2236) 0x49dcec FMLA	V12.2D, V9.2D, V3.D[0]

  (2236) 0x49dcf0 FMLA	V8.2D, V9.2D, V6.D[0]

  (2236) 0x49dcf4 FMLA	V11.2D, V10.2D, V1.D[0]

  (2236) 0x49dcf8 FMLA	V12.2D, V10.2D, V4.D[0]

  (2236) 0x49dcfc FMLA	V8.2D, V10.2D, V7.D[0]

  (2236) 0x49dd00 FRINTA	V9.2D, V11.2D

  (2236) 0x49dd04 FRINTA	V10.2D, V12.2D

  (2236) 0x49dd08 FSUB	V9.2D, V11.2D, V9.2D

  (2236) 0x49dd0c FRINTA	V11.2D, V8.2D

  (2236) 0x49dd10 FSUB	V10.2D, V12.2D, V10.2D

  (2236) 0x49dd14 FMUL	V12.2D, V9.2D, V19.D[0]

  (2236) 0x49dd18 FSUB	V8.2D, V8.2D, V11.2D

  (2236) 0x49dd1c FMUL	V11.2D, V9.2D, V16.D[0]

  (2236) 0x49dd20 FMUL	V9.2D, V9.2D, V22.D[0]

  (2236) 0x49dd24 FMLA	V12.2D, V10.2D, V20.D[0]

  (2236) 0x49dd28 FMLA	V11.2D, V10.2D, V17.D[0]

  (2236) 0x49dd2c FMLA	V9.2D, V10.2D, V23.D[0]

  (2236) 0x49dd30 FMLA	V12.2D, V8.2D, V21.D[0]

  (2236) 0x49dd34 FMLA	V11.2D, V8.2D, V18.D[0]

  (2236) 0x49dd38 FMLA	V9.2D, V8.2D, V25.D[0]

  (2236) 0x49dd3c FMUL	V8.2D, V11.2D, V11.2D

  (2236) 0x49dd40 STR	Q11, [X1, X18]

  (2236) 0x49dd44 STR	Q12, [X8, X18]

  (2236) 0x49dd48 STR	Q9, [X5, X18]

  (2236) 0x49dd4c FMLA	V8.2D, V9.2D, V9.2D

  (2236) 0x49dd50 FMLA	V8.2D, V12.2D, V12.2D

  (2236) 0x49dd54 FSQRT	V8.2D, V8.2D

  (2236) 0x49dd58 STR	Q8, [X6, X18]

  (2236) 0x49dd5c ADD	X18, X18, #16

  (2236) 0x49dd60 B.NE	49dcc0

(2233) 0x49dd64 LDP	X12, X18, [X29, #944]

(2233) 0x49dd68 CBZ	X4, 49d848

(2233) 0x49dd6c B	49d900

      (2231) 0x49dd70 AND	X10, X9, #8062

      (2231) 0x49dd74 ORR	X12, XZR, X15

      (2231) 0x49dd78 ORR	X13, XZR, X8

      (2231) 0x49dd7c ORR	X11, XZR, X10

        (2235) 0x49dd80 LDP	Q1, Q0, [X13]

        (2235) 0x49dd84 LDP	Q3, Q2, [X13, #64]

        (2235) 0x49dd88 SUBS	X11, X11, #4

        (2235) 0x49dd8c LDP	Q4, Q5, [X13, #32]

        (2235) 0x49dd90 ADD	X13, X13, #96

        (2235) 0x49dd94 STP	Q1, Q0, [X12]

        (2235) 0x49dd98 STP	Q4, Q5, [X12, #32]

        (2235) 0x49dd9c STP	Q3, Q2, [X12, #64]

        (2235) 0x49dda0 ADD	X12, X12, #96

        (2235) 0x49dda4 B.NE	49dd80

      (2231) 0x49dda8 CMP	X9, X10

      (2231) 0x49ddac B.NE	49d540

      (2231) 0x49ddb0 B	49d58c

0x49ddb4 BL	409d00

0x49ddb8 BL	409d00

0x49ddbc B	49ddc8

0x49ddc0 B	49ddc8

0x49ddc4 B	49ddc8

0x49ddc8 ORR	X20, XZR, X0

0x49ddcc LDR	X0, [SP, #8]

0x49ddd0 BL	469160

0x49ddd4 ORR	X0, XZR, X20

0x49ddd8 BL	404970

0x49dddc BL	409d00

Coverage (%)	Name	Source Location	Module
►99.75+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	qmcplusplus::NonLocalPP<double[...]	NonLocalPP.hpp:135	exec
○	main.omp_outlined.63	NewTimer.h:249	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	SoaDistanceTableABOMPTarget.h:184-233
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:267
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:184-199,205-217,228-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.83 to 1.50 cycles (4.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 67% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.83 to 6.50 cycles (1.05x speedup).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.83 to 4.00 cycles (1.71x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	4.00	4.00	3.00	3.00	3.00	3.00	1.50	1.50	0.50	0.50	6.83	6.50	6.67	5.00	5.00
cycles	6.50	6.50	4.00	4.00	3.00	3.00	3.00	3.00	1.50	1.50	0.50	0.50	6.83	6.50	6.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	6.83

Vectorization ratios

all	7%
load	0%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.83 cycles. At this rate:

9% of peak load performance is reached (9.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
51% of peak store performance is reached (24.59 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 49d4c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR D12, [SP, #368]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 49f120 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6resizeEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X23, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 469040 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X24, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X23, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X24, X24,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 43c4e0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 49d584 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X23, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, #18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CS 49d62c <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
BL 409d00 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409d00 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49ddc8 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x908>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49ddc8 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x908>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49ddc8 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x908>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 469160 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 404970 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409d00 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run armclang_3

Source file and lines	SoaDistanceTableABOMPTarget.h:184-233
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:267
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:184-199,205-217,228-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.83 to 1.50 cycles (4.56x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.83 to 4.00 cycles (1.71x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	48
loop length	192
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

5.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	6.50	6.50	4.00	4.00	3.00	3.00	3.00	3.00	1.50	1.50	0.50	0.50	6.83	6.50	6.67	5.00	5.00
cycles	6.50	6.50	4.00	4.00	3.00	3.00	3.00	3.00	1.50	1.50	0.50	0.50	6.83	6.50	6.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	5.63
Overall L1	6.83

Vectorization ratios

all	7%
load	0%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.83 cycles. At this rate:

9% of peak load performance is reached (9.37 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
51% of peak store performance is reached (24.59 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 49d4c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STR D12, [SP, #368]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D11, D10, [SP, #16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D9, D8, [SP, #32]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB SP, SP, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X21, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X23, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 49f120 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE6resizeEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X20, [X23, #440]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 469040 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP X8, X24, [X23, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
STUR X8, [X29, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
MOVI D0, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X0, X23, #384	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, X24, X24,LSL #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X20, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 43c4e0 <_ZN11qmcplusplus6VectorIdNS_12OMPallocatorIdNS_10MallocatorIdLm32EEEEEE6resizeEmd>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CBZ X9, 49d584 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0xc4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X15, [X23, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X10, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X15, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CMP X9, #18	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.CS 49d62c <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x16c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X23, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X8, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
BL 409d00 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409d00 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49ddc8 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x908>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49ddc8 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x908>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 49ddc8 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x908>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BL 469160 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 404970 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409d00 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)–	5.17	7.15
▼Loop 2233 - SoaDistanceTableABOMPTarget.h:194-233 - exec–	0.07	0.10
○Loop 2236 - ParticleBConds3DSoa.h:280-298 - exec	5.07	6.95
▼Loop 2234 - SoaDistanceTableABOMPTarget.h:194-233 - exec–	0.01	0.01
▼Loop 2232 - SoaDistanceTableABOMPTarget.h:194-233 - exec–	0.02	0.02
▼Loop 2231 - SoaDistanceTableABOMPTarget.h:194-233 - exec–	0.00	0.01
○Loop 2230 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0.00	0.01
○Loop 2235 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0.00	0.00
○Loop 2229 - SoaDistanceTableABOMPTarget.h:228-228 - exec	0.00	0.00

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ASM code

Code clean check

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Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code