OV - exec - Loop 321

	Loop Id: 321	Module: exec	Source: BsplineFunctor.h:305-336	Coverage: 0.03%

0x41b9c4 LDP	Q19, Q16, [X13], #32    [7]

0x41b9c8 MOVI	V24.4S, #3

0x41b9cc MOVI	V26.4S, #2

0x41b9d0 MOVI	V28.4S, #1

0x41b9d4 LDP	W16, W24, [X4, #4]    [14]

0x41b9d8 ADD	X4, X4, #16

0x41b9dc LDR	Q5, [SP, #512]    [3]

0x41b9e0 SBFM	X25, X16, #61, #31

0x41b9e4 SBFM	X5, X24, #61, #31

0x41b9e8 ADD	X23, X12, X25

0x41b9ec ADD	X21, X25, X11

0x41b9f0 FMUL	V30.2D, V19.2D, V7.2D

0x41b9f4 ADD	X3, X25, X7

0x41b9f8 FMUL	V31.2D, V16.2D, V7.2D

0x41b9fc FDIV	V29.2D, V7.2D, V16.2D

0x41ba00 LDR	Q16, [SP, #304]    [3]

0x41ba04 FDIV	V8.2D, V7.2D, V19.2D

0x41ba08 LDR	Q19, [SP, #192]    [3]

0x41ba0c FCVTZS	V17.2D, V30.2D

0x41ba10 FCVTZS	V22.2D, V31.2D

0x41ba14 STR	Q29, [SP, #464]    [3]

0x41ba18 FRINTZ	V20.2D, V30.2D

0x41ba1c FRINTZ	V29.2D, V31.2D

0x41ba20 UZP1	V27.4S, V17.4S, V22.4S

0x41ba24 FSUB	V30.2D, V30.2D, V20.2D

0x41ba28 FSUB	V31.2D, V31.2D, V29.2D

0x41ba2c ADD	V23.4S, V27.4S, V24.4S

0x41ba30 ADD	V25.4S, V27.4S, V26.4S

0x41ba34 SSHLL2	V9.2D, V27.4S, #32

0x41ba38 ADD	V15.4S, V27.4S, V28.4S

0x41ba3c SSHLL	V14.2D, V27.2S, #32

0x41ba40 ORR	V24.16B, V5.16B, V5.16B

0x41ba44 FMUL	V29.2D, V30.2D, V30.2D

0x41ba48 SSHLL	V12.2D, V23.2S, #32

0x41ba4c SSHLL	V10.2D, V25.2S, #32

0x41ba50 FMOV	X30, D9

0x41ba54 SSHLL2	V18.2D, V25.4S, #32

0x41ba58 FMOV	X6, D14

0x41ba5c SSHLL2	V2.2D, V23.4S, #32

0x41ba60 MOV	X1, V12.D[1]

0x41ba64 SSHLL	V22.2D, V15.2S, #32

0x41ba68 FMOV	X16, D12

0x41ba6c SSHLL2	V28.2D, V15.4S, #32

0x41ba70 MOV	X18, V10.D[1]

0x41ba74 FMOV	X22, D10

0x41ba78 LDR	D20, [X0, X30,LSL #3]    [9]

0x41ba7c MOV	X30, V18.D[1]

0x41ba80 MOV	X24, V2.D[1]

0x41ba84 LDR	D3, [X0, X1,LSL #3]    [9]

0x41ba88 MOV	X25, V22.D[1]

0x41ba8c LDR	D13, [X0, X16,LSL #3]    [9]

0x41ba90 MOV	X16, V9.D[1]

0x41ba94 LDR	Q9, [SP, #608]    [3]

0x41ba98 FMOV	X1, D2

0x41ba9c LDR	D21, [X0, X18,LSL #3]    [9]

0x41baa0 MOV	X18, V14.D[1]

0x41baa4 MOV	V13.D[1], V3.D[0]

0x41baa8 LDP	Q10, Q3, [SP, #576]    [3]

0x41baac LDR	D11, [X0, X22,LSL #3]    [9]

0x41bab0 ORR	V26.16B, V9.16B, V9.16B

0x41bab4 LDP	Q2, Q4, [SP, #544]    [3]

0x41bab8 LDR	D17, [X0, X6,LSL #3]    [9]

0x41babc FMOV	X6, D18

0x41bac0 MOV	V11.D[1], V21.D[0]

0x41bac4 LDR	D21, [X0, X30,LSL #3]    [9]

0x41bac8 FMOV	X30, D22

0x41bacc FMLA	V26.2D, V30.2D, V3.2D

0x41bad0 LDP	Q6, Q18, [SP, #480]    [3]

0x41bad4 ORR	V27.16B, V10.16B, V10.16B

0x41bad8 LDR	D15, [X0, X25,LSL #3]    [9]

0x41badc MOV	X25, V28.D[1]

0x41bae0 FMLA	V10.2D, V31.2D, V4.2D

0x41bae4 LDR	D22, [X0, X24,LSL #3]    [9]

0x41bae8 FMOV	X24, D28

0x41baec ORR	V28.16B, V9.16B, V9.16B

0x41baf0 LDR	D23, [X0, X1,LSL #3]    [9]

0x41baf4 FMLA	V26.2D, V29.2D, V16.2D

0x41baf8 LDR	D16, [X0, X30,LSL #3]    [9]

0x41bafc FMLA	V27.2D, V30.2D, V4.2D

0x41bb00 ORR	V12.16B, V6.16B, V6.16B

0x41bb04 LDR	D9, [X0, X18,LSL #3]    [9]

0x41bb08 ORR	V25.16B, V6.16B, V6.16B

0x41bb0c MOV	V23.D[1], V22.D[0]

0x41bb10 LDR	D14, [X0, X6,LSL #3]    [9]

0x41bb14 FMUL	V22.2D, V31.2D, V31.2D

0x41bb18 MOV	V16.D[1], V15.D[0]

0x41bb1c LDR	Q15, [SP, #304]    [3]

0x41bb20 FMLA	V28.2D, V31.2D, V3.2D

0x41bb24 LDURSW	X22, [X4, #496]    [10]

0x41bb28 MOV	V17.D[1], V9.D[0]

0x41bb2c FMLA	V10.2D, V22.2D, V2.2D

0x41bb30 LDUR	W1, [X4, #508]    [10]

0x41bb34 MOV	V14.D[1], V21.D[0]

0x41bb38 FMLA	V12.2D, V30.2D, V19.2D

0x41bb3c LDR	D19, [X0, X24,LSL #3]    [9]

0x41bb40 UBFM	X6, X22, #61, #60

0x41bb44 SBFM	X1, X1, #61, #31

0x41bb48 FMLA	V27.2D, V29.2D, V2.2D

0x41bb4c ADD	X22, X12, X1

0x41bb50 ADD	X18, X1, X11

0x41bb54 LDP	Q6, Q2, [SP, #272]    [3]

0x41bb58 FMLA	V28.2D, V22.2D, V15.2D

0x41bb5c LDR	D15, [X0, X16,LSL #3]    [9]

0x41bb60 ADD	X16, X1, X7

0x41bb64 LDR	Q4, [SP, #384]    [3]

0x41bb68 FMLA	V24.2D, V30.2D, V18.2D

0x41bb6c LDR	Q3, [SP, #432]    [3]

0x41bb70 MOV	V20.D[1], V15.D[0]

0x41bb74 ORR	V15.16B, V5.16B, V5.16B

0x41bb78 FMLA	V2.2D, V30.2D, V6.2D

0x41bb7c LDR	Q6, [SP, #256]    [3]

0x41bb80 FMLA	V15.2D, V31.2D, V18.2D

0x41bb84 LDP	Q5, Q18, [SP, #688]    [3]

0x41bb88 FMLA	V2.2D, V29.2D, V6.2D

0x41bb8c FMUL	V27.2D, V11.2D, V27.2D

0x41bb90 FMUL	V9.2D, V30.2D, V29.2D

0x41bb94 FMUL	V26.2D, V13.2D, V26.2D

0x41bb98 FMUL	V21.2D, V14.2D, V10.2D

0x41bb9c LDR	D10, [X0, X25,LSL #3]    [9]

0x41bba0 FMUL	V3.2D, V29.2D, V3.2D

0x41bba4 FMLA	V27.2D, V16.2D, V2.2D

0x41bba8 FMUL	V2.2D, V29.2D, V5.2D

0x41bbac MOV	V19.D[1], V10.D[0]

0x41bbb0 LDR	Q10, [SP, #192]    [3]

0x41bbb4 FMLA	V3.2D, V9.2D, V18.2D

0x41bbb8 FMLA	V2.2D, V9.2D, V4.2D

0x41bbbc LDP	Q4, Q6, [SP, #224]    [3]

0x41bbc0 FMLA	V25.2D, V31.2D, V10.2D

0x41bbc4 FMUL	V10.2D, V31.2D, V22.2D

0x41bbc8 FMUL	V12.2D, V11.2D, V12.2D

0x41bbcc FMUL	V24.2D, V13.2D, V24.2D

0x41bbd0 FMUL	V15.2D, V23.2D, V15.2D

0x41bbd4 FMLA	V6.2D, V30.2D, V4.2D

0x41bbd8 LDR	Q4, [SP, #208]    [3]

0x41bbdc FMUL	V25.2D, V14.2D, V25.2D

0x41bbe0 FMUL	V28.2D, V23.2D, V28.2D

0x41bbe4 FMLA	V6.2D, V29.2D, V4.2D

0x41bbe8 FMUL	V4.2D, V22.2D, V5.2D

0x41bbec FMLA	V26.2D, V17.2D, V6.2D

0x41bbf0 LDR	Q6, [SP, #432]    [3]

0x41bbf4 FADD	V27.2D, V27.2D, V26.2D

0x41bbf8 ORR	V26.16B, V18.16B, V18.16B

0x41bbfc LDP	Q18, Q5, [SP, #368]    [3]

0x41bc00 FMUL	V27.2D, V27.2D, V8.2D

0x41bc04 ORR	V8.16B, V1.16B, V1.16B

0x41bc08 FMLA	V4.2D, V10.2D, V5.2D

0x41bc0c FMUL	V5.2D, V22.2D, V6.2D

0x41bc10 FMLA	V5.2D, V10.2D, V26.2D

0x41bc14 LDP	Q6, Q26, [SP, #400]    [3]

0x41bc18 FMLA	V26.2D, V30.2D, V6.2D

0x41bc1c FMUL	V6.2D, V29.2D, V18.2D

0x41bc20 FADD	V2.2D, V26.2D, V2.2D

0x41bc24 FMUL	V26.2D, V2.2D, V11.2D

0x41bc28 LDR	Q2, [SP, #720]    [3]

0x41bc2c LDP	Q18, Q11, [SP, #336]    [3]

0x41bc30 FMUL	V29.2D, V29.2D, V18.2D

0x41bc34 LDR	Q18, [SP, #176]    [3]

0x41bc38 FMLA	V8.2D, V30.2D, V18.2D

0x41bc3c LDR	Q18, [SP, #352]    [3]

0x41bc40 FMLA	V12.2D, V16.2D, V8.2D

0x41bc44 ORR	V8.16B, V0.16B, V0.16B

0x41bc48 FMLA	V6.2D, V9.2D, V18.2D

0x41bc4c LDR	Q18, [SP, #320]    [3]

0x41bc50 FMLA	V29.2D, V9.2D, V18.2D

0x41bc54 LDR	Q9, [SP, #160]    [3]

0x41bc58 LDR	Q18, [SP, #448]    [3]

0x41bc5c FMLA	V8.2D, V30.2D, V9.2D

0x41bc60 ORR	V9.16B, V2.16B, V2.16B

0x41bc64 FMLA	V24.2D, V17.2D, V8.2D

0x41bc68 FMLA	V9.2D, V30.2D, V18.2D

0x41bc6c FADD	V12.2D, V12.2D, V24.2D

0x41bc70 FADD	V24.2D, V9.2D, V3.2D

0x41bc74 LDR	Q3, [SP, #528]    [3]

0x41bc78 FMUL	V8.2D, V24.2D, V13.2D

0x41bc7c LDP	Q13, Q18, [SP, #400]    [3]

0x41bc80 FMUL	V24.2D, V12.2D, V3.2D

0x41bc84 STR	D24, [X12, X6]    [5]

0x41bc88 FMLA	V18.2D, V31.2D, V13.2D

0x41bc8c ORR	V13.16B, V1.16B, V1.16B

0x41bc90 FADD	V4.2D, V18.2D, V4.2D

0x41bc94 FMUL	V9.2D, V14.2D, V4.2D

0x41bc98 LDR	Q14, [SP, #368]    [3]

0x41bc9c FMUL	V12.2D, V22.2D, V14.2D

0x41bca0 ORR	V14.16B, V0.16B, V0.16B

0x41bca4 FMLA	V12.2D, V10.2D, V11.2D

0x41bca8 LDR	Q11, [SP, #336]    [3]

0x41bcac ST1	{V24.D[1]}, [X23]    [8]

0x41bcb0 LDR	Q4, [SP, #160]    [3]

0x41bcb4 FMUL	V11.2D, V22.2D, V11.2D

0x41bcb8 LDR	Q18, [SP, #176]    [3]

0x41bcbc LDR	Q24, [SP, #320]    [3]

0x41bcc0 FMLA	V14.2D, V31.2D, V4.2D

0x41bcc4 FMLA	V13.2D, V31.2D, V18.2D

0x41bcc8 FMLA	V15.2D, V20.2D, V14.2D

0x41bccc FMLA	V25.2D, V19.2D, V13.2D

0x41bcd0 LDR	Q13, [SP, #288]    [3]

0x41bcd4 FMLA	V11.2D, V10.2D, V24.2D

0x41bcd8 FADD	V25.2D, V25.2D, V15.2D

0x41bcdc FMUL	V15.2D, V25.2D, V3.2D

0x41bce0 LDR	Q3, [SP, #448]    [3]

0x41bce4 STR	D15, [X12, X5]    [5]

0x41bce8 ST1	{V15.D[1]}, [X22]    [6]

0x41bcec STR	D27, [X6, X11]    [2]

0x41bcf0 FMLA	V2.2D, V31.2D, V3.2D

0x41bcf4 ST1	{V27.D[1]}, [X21]    [4]

0x41bcf8 LDP	Q18, Q14, [SP, #656]    [3]

0x41bcfc LDP	Q10, Q27, [SP, #256]    [3]

0x41bd00 FADD	V5.2D, V2.2D, V5.2D

0x41bd04 LDP	Q4, Q24, [SP, #224]    [3]

0x41bd08 LDP	Q25, Q15, [SP, #624]    [3]

0x41bd0c ORR	V2.16B, V14.16B, V14.16B

0x41bd10 FMLA	V14.2D, V31.2D, V18.2D

0x41bd14 FMLA	V2.2D, V30.2D, V18.2D

0x41bd18 FMLA	V13.2D, V31.2D, V27.2D

0x41bd1c FMLA	V24.2D, V31.2D, V4.2D

0x41bd20 FADD	V6.2D, V2.2D, V6.2D

0x41bd24 FMLA	V13.2D, V22.2D, V10.2D

0x41bd28 FADD	V12.2D, V14.2D, V12.2D

0x41bd2c FMUL	V23.2D, V23.2D, V5.2D

0x41bd30 FMLA	V26.2D, V16.2D, V6.2D

0x41bd34 LDR	Q16, [SP, #208]    [3]

0x41bd38 FMLA	V21.2D, V19.2D, V13.2D

0x41bd3c FMLA	V24.2D, V22.2D, V16.2D

0x41bd40 ORR	V22.16B, V15.16B, V15.16B

0x41bd44 FMLA	V9.2D, V19.2D, V12.2D

0x41bd48 FMLA	V22.2D, V30.2D, V25.2D

0x41bd4c ORR	V30.16B, V15.16B, V15.16B

0x41bd50 FMLA	V28.2D, V20.2D, V24.2D

0x41bd54 FMLA	V30.2D, V31.2D, V25.2D

0x41bd58 FADD	V19.2D, V22.2D, V29.2D

0x41bd5c FADD	V21.2D, V21.2D, V28.2D

0x41bd60 LDR	Q28, [SP, #464]    [3]

0x41bd64 FADD	V31.2D, V30.2D, V11.2D

0x41bd68 FMLA	V8.2D, V17.2D, V19.2D

0x41bd6c FMLA	V23.2D, V20.2D, V31.2D

0x41bd70 FADD	V17.2D, V26.2D, V8.2D

0x41bd74 FMUL	V26.2D, V21.2D, V28.2D

0x41bd78 FADD	V20.2D, V9.2D, V23.2D

0x41bd7c STR	D26, [X5, X11]    [1]

0x41bd80 ST1	{V26.D[1]}, [X18]    [12]

0x41bd84 STR	D17, [X6, X7]    [2]

0x41bd88 ST1	{V17.D[1]}, [X3]    [13]

0x41bd8c STR	D20, [X5, X7]    [1]

0x41bd90 ST1	{V20.D[1]}, [X16]    [11]

0x41bd94 CMP	X28, X4

0x41bd98 B.NE	41b9c4

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 305 - 336

--------------------------------------------------------------------------------

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

Coverage (%)	Name	Source Location	Module
►98.70+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:201	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P8, P9, P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	BsplineFunctor.h:305-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.00
CQA cycles if no scalar integer	41.00
CQA cycles if FP arith vectorized	43.00
CQA cycles if fully vectorized	40.50
Front-end cycles	30.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	43.00
P9 cycles	43.00
P10 cycles	43.00
P11 cycles	43.00
P12 cycles	24.83
P13 cycles	24.50
P14 cycles	24.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	246.00
Nb uops	246.00
Nb loads	NA
Nb stores	13.00
Nb stack references	0.00
FLOP/cycle	7.07
Nb FLOP add-sub	32.00
Nb FLOP mul	60.00
Nb FLOP fma	104.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.28
Bytes prefetched	0.00
Bytes loaded	1056.00
Bytes stored	160.00
Stride 0	2.00
Stride 1	1.00
Stride n	1.00
Stride unknown	8.00
Stride indirect	2.00
Vectorization ratio all	76.09
Vectorization ratio load	72.41
Vectorization ratio store	7.69
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	51.79
Vector-efficiency ratio all	85.98
Vector-efficiency ratio load	86.21
Vector-efficiency ratio store	53.85
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	67.41

Metric	Value
CQA speedup if no scalar integer	1.05
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	1.06
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.40
Bottlenecks	P8, P9, P10, P11,
Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source	BsplineFunctor.h:305-336
Source loop unroll info	not unrolled or unrolled with no peel/tail loop
Source loop unroll confidence level	max
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	43.00
CQA cycles if no scalar integer	41.00
CQA cycles if FP arith vectorized	43.00
CQA cycles if fully vectorized	40.50
Front-end cycles	30.75
P0 cycles	0.50
P1 cycles	0.50
P2 cycles	2.25
P3 cycles	2.25
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.08
P7 cycles	2.08
P8 cycles	43.00
P9 cycles	43.00
P10 cycles	43.00
P11 cycles	43.00
P12 cycles	24.83
P13 cycles	24.50
P14 cycles	24.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	6.99 - 13.99
Inter-iter dependencies cycles	1
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	246.00
Nb uops	246.00
Nb loads	NA
Nb stores	13.00
Nb stack references	0.00
FLOP/cycle	7.07
Nb FLOP add-sub	32.00
Nb FLOP mul	60.00
Nb FLOP fma	104.00
Nb FLOP div	4.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	28.28
Bytes prefetched	0.00
Bytes loaded	1056.00
Bytes stored	160.00
Stride 0	2.00
Stride 1	1.00
Stride n	1.00
Stride unknown	8.00
Stride indirect	2.00
Vectorization ratio all	76.09
Vectorization ratio load	72.41
Vectorization ratio store	7.69
Vectorization ratio mul	100.00
Vectorization ratio add_sub	100.00
Vectorization ratio fma	100.00
Vectorization ratio div_sqrt	100.00
Vectorization ratio other	51.79
Vector-efficiency ratio all	85.98
Vector-efficiency ratio load	86.21
Vector-efficiency ratio store	53.85
Vector-efficiency ratio mul	100.00
Vector-efficiency ratio add_sub	100.00
Vector-efficiency ratio fma	100.00
Vector-efficiency ratio div_sqrt	100.00
Vector-efficiency ratio other	67.41

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

The loop is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:305-336.

The related source loop is not unrolled or unrolled with no peel/tail loop.

gain
potential
hint
expert

Vectorization

Your loop is partially vectorized. 85% of vector register length is used (average across all VPU instructions). By fully vectorizing your loop, you can lower the cost of an iteration from 43.00 to 40.50 cycles (1.06x speedup).

Details

76% of VPU instructions are used in vector version (process two or more data elements in vector registers):

72% of VPU loads are used in vector version.
7% of VPU stores are used in vector version.
51% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 104 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (104 inside FMA instructions)
164: multiply (104 inside FMA instructions)
4: divide

The binary loop is loading 1056 bytes. The binary loop is storing 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	246
loop length	984
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	43.00	43.00	43.00	43.00	24.83	24.50	24.67	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	43.00	43.00	43.00	43.00	24.83	24.50	24.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-13.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	30.75
Data deps.	1.00
Overall L1	43.00

Vectorization ratios

INT

all	60%
load	72%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	33%

INT+FP

all	76%
load	72%
store	7%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	51%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.00 cycles. At this rate:

25% of peak load performance is reached (24.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b9c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q19, Q16, [X13], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVI V24.4S, #3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V26.4S, #2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V28.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDP W16, W24, [X4, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SBFM X25, X16, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X24, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X23, X12, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X25, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V30.2D, V19.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ADD X3, X25, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V31.2D, V16.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV V29.2D, V7.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR Q16, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV V8.2D, V7.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR Q19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCVTZS V17.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCVTZS V22.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
STR Q29, [SP, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FRINTZ V20.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FRINTZ V29.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
UZP1 V27.4S, V17.4S, V22.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V30.2D, V30.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V31.2D, V31.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V23.4S, V27.4S, V24.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V25.4S, V27.4S, V26.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SSHLL2 V9.2D, V27.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
ADD V15.4S, V27.4S, V28.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SSHLL V14.2D, V27.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
ORR V24.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V29.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
SSHLL V12.2D, V23.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL V10.2D, V25.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X30, D9	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V18.2D, V25.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X6, D14	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V2.2D, V23.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X1, V12.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
SSHLL V22.2D, V15.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X16, D12	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V28.2D, V15.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X18, V10.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X22, D10	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D20, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X30, V18.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV X24, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D3, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X25, V22.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D13, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X16, V9.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR Q9, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMOV X1, D2	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D21, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X18, V14.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV V13.D[1], V3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDP Q10, Q3, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR D11, [X0, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ORR V26.16B, V9.16B, V9.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q2, Q4, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR D17, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X6, D18	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
MOV V11.D[1], V21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D21, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X30, D22	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
FMLA V26.2D, V30.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q6, Q18, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V27.16B, V10.16B, V10.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D15, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X25, V28.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMLA V10.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D22, [X0, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X24, D28	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ORR V28.16B, V9.16B, V9.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D23, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V26.2D, V29.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D16, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V27.2D, V30.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V12.16B, V6.16B, V6.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D9, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ORR V25.16B, V6.16B, V6.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOV V23.D[1], V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D14, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V22.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOV V16.D[1], V15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V28.2D, V31.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDURSW X22, [X4, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOV V17.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V10.2D, V22.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDUR W1, [X4, #508]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOV V14.D[1], V21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V12.2D, V30.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D19, [X0, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
UBFM X6, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X1, X1, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA V27.2D, V29.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ADD X22, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X1, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q6, Q2, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V28.2D, V22.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D15, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X16, X1, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q4, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V24.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q3, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOV V20.D[1], V15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ORR V15.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V2.2D, V30.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q6, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V15.2D, V31.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q5, Q18, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V2.2D, V29.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V27.2D, V11.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V9.2D, V30.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V26.2D, V13.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V14.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR D10, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V3.2D, V29.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V27.2D, V16.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V2.2D, V29.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOV V19.D[1], V10.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V3.2D, V9.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V2.2D, V9.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q4, Q6, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V25.2D, V31.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V10.2D, V31.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V12.2D, V11.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V24.2D, V13.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V15.2D, V23.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V6.2D, V30.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V25.2D, V14.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V28.2D, V23.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V6.2D, V29.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V4.2D, V22.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V26.2D, V17.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q6, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V27.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V26.16B, V18.16B, V18.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q18, Q5, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V27.2D, V27.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ORR V8.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V4.2D, V10.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V5.2D, V22.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V5.2D, V10.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q6, Q26, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V26.2D, V30.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V6.2D, V29.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V2.2D, V26.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V26.2D, V2.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q2, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q18, Q11, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V29.2D, V29.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V8.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V12.2D, V16.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V8.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V6.2D, V9.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q18, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V29.2D, V9.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V8.2D, V30.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V9.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V24.2D, V17.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V9.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V12.2D, V12.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V24.2D, V9.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q3, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V8.2D, V24.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q13, Q18, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V24.2D, V12.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D24, [X12, X6]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FMLA V18.2D, V31.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V13.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V4.2D, V18.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V9.2D, V14.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q14, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V12.2D, V22.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ORR V14.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V12.2D, V10.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q11, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ST1 {V24.D[1]}, [X23]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDR Q4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V11.2D, V22.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q24, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V14.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V15.2D, V20.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V19.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V11.2D, V10.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V25.2D, V25.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V15.2D, V25.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q3, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR D15, [X12, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V15.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D27, [X6, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FMLA V2.2D, V31.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ST1 {V27.D[1]}, [X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDP Q18, Q14, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q10, Q27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V5.2D, V2.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q4, Q24, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q25, Q15, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V2.16B, V14.16B, V14.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V14.2D, V31.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V2.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V24.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V6.2D, V2.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V13.2D, V22.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V12.2D, V14.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V23.2D, V23.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V26.2D, V16.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V21.2D, V19.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V24.2D, V22.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V22.16B, V15.16B, V15.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V9.2D, V19.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V22.2D, V30.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V30.16B, V15.16B, V15.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V28.2D, V20.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V30.2D, V31.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V19.2D, V22.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V21.2D, V21.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q28, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V31.2D, V30.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V8.2D, V17.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V23.2D, V20.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V17.2D, V26.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V26.2D, V21.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V20.2D, V9.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D26, [X5, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V26.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D17, [X6, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V17.D[1]}, [X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D20, [X5, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V20.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
CMP X28, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41b9c4 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::TwoBodyJastrowRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)
Source file and lines	BsplineFunctor.h:305-336
Module	exec

gain
potential
hint
expert

Vectorization

Details

76% of VPU instructions are used in vector version (process two or more data elements in vector registers):

72% of VPU loads are used in vector version.
7% of VPU stores are used in vector version.
51% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

FMA

Detected 104 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Conversion instructions

Detected expensive conversion instructions.

Details

FCVTZS: 2 occurrences►
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309
- /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:309

Workaround

Avoid mixing data with different types. In particular, check if the type of constants is the same as array elements.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 304 FP arithmetical operations:

136: addition or subtraction (104 inside FMA instructions)
164: multiply (104 inside FMA instructions)
4: divide

The binary loop is loading 1056 bytes. The binary loop is storing 160 bytes.

Arithmetic intensity

Arithmetic intensity is 0.25 FP operations per loaded or stored byte.

General properties

nb instructions	246
loop length	984
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

30.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	43.00	43.00	43.00	43.00	24.83	24.50	24.67	0.00	0.00
cycles	0.50	0.50	2.25	2.25	2.17	2.17	2.08	2.08	43.00	43.00	43.00	43.00	24.83	24.50	24.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions	6.99-13.99
Longest recurrence chain latency (RecMII)	1.00

Cycles summary

Front-end	30.75
Data deps.	1.00
Overall L1	43.00

Vectorization ratios

INT

all	60%
load	72%
store	7%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	100%
fma	NA (no fma vectorizable/vectorized instructions)
other	56%

all	92%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	33%

INT+FP

all	76%
load	72%
store	7%
mul	100%
add-sub	100%
fma	100%
div/sqrt	100%
other	51%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 43.00 cycles. At this rate:

25% of peak load performance is reached (24.56 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
7% of peak store performance is reached (3.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 41b9c4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	Latency	Recip. throughput	Vectorization
LDP Q19, Q16, [X13], #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOVI V24.4S, #3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V26.4S, #2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
MOVI V28.4S, #1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (25.0%)
LDP W16, W24, [X4, #4]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
ADD X4, X4, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q5, [SP, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
SBFM X25, X16, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X5, X24, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X23, X12, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X21, X25, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V30.2D, V19.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ADD X3, X25, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMUL V31.2D, V16.2D, V7.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FDIV V29.2D, V7.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR Q16, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FDIV V8.2D, V7.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	7-15	3.50-6.99	vect (100.0%)
LDR Q19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FCVTZS V17.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FCVTZS V22.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
STR Q29, [SP, #464]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	vect (100.0%)
FRINTZ V20.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
FRINTZ V29.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	3	0.50	vect (100.0%)
UZP1 V27.4S, V17.4S, V22.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V30.2D, V30.2D, V20.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FSUB V31.2D, V31.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V23.4S, V27.4S, V24.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ADD V25.4S, V27.4S, V26.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SSHLL2 V9.2D, V27.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
ADD V15.4S, V27.4S, V28.4S	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
SSHLL V14.2D, V27.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
ORR V24.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V29.2D, V30.2D, V30.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
SSHLL V12.2D, V23.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
SSHLL V10.2D, V25.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X30, D9	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V18.2D, V25.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X6, D14	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V2.2D, V23.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X1, V12.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
SSHLL V22.2D, V15.2S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
FMOV X16, D12	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
SSHLL2 V28.2D, V15.4S, #32	1	0	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	2	0.50	vect (50.0%)
MOV X18, V10.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMOV X22, D10	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D20, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X30, V18.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV X24, V2.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D3, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X25, V22.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR D13, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X16, V9.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
LDR Q9, [SP, #608]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMOV X1, D2	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
LDR D21, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X18, V14.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
MOV V13.D[1], V3.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDP Q10, Q3, [SP, #576]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR D11, [X0, X22,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ORR V26.16B, V9.16B, V9.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q2, Q4, [SP, #544]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDR D17, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X6, D18	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
MOV V11.D[1], V21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D21, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X30, D22	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
FMLA V26.2D, V30.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q6, Q18, [SP, #480]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V27.16B, V10.16B, V10.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D15, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
MOV X25, V28.D[1]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	1	scal (50.0%)
FMLA V10.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D22, [X0, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMOV X24, D28	1	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	2	1	scal (50.0%)
ORR V28.16B, V9.16B, V9.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D23, [X0, X1,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V26.2D, V29.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D16, [X0, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMLA V27.2D, V30.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V12.16B, V6.16B, V6.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR D9, [X0, X18,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ORR V25.16B, V6.16B, V6.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
MOV V23.D[1], V22.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR D14, [X0, X6,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V22.2D, V31.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOV V16.D[1], V15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q15, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V28.2D, V31.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDURSW X22, [X4, #496]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOV V17.D[1], V9.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V10.2D, V22.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDUR W1, [X4, #508]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	4	0.33	N/A
MOV V14.D[1], V21.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
FMLA V12.2D, V30.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D19, [X0, X24,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
UBFM X6, X22, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X1, X1, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
FMLA V27.2D, V29.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ADD X22, X12, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
ADD X18, X1, X11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDP Q6, Q2, [SP, #272]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V28.2D, V22.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR D15, [X0, X16,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
ADD X16, X1, X7	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	1	0.17	N/A
LDR Q4, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V24.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q3, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
MOV V20.D[1], V15.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
ORR V15.16B, V5.16B, V5.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V2.2D, V30.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q6, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V15.2D, V31.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q5, Q18, [SP, #688]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V2.2D, V29.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V27.2D, V11.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V9.2D, V30.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V26.2D, V13.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V21.2D, V14.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR D10, [X0, X25,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	scal (50.0%)
FMUL V3.2D, V29.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V27.2D, V16.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V2.2D, V29.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
MOV V19.D[1], V10.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	scal (50.0%)
LDR Q10, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V3.2D, V9.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V2.2D, V9.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q4, Q6, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V25.2D, V31.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V10.2D, V31.2D, V22.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V12.2D, V11.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V24.2D, V13.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V15.2D, V23.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V6.2D, V30.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q4, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V25.2D, V14.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMUL V28.2D, V23.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V6.2D, V29.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V4.2D, V22.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V26.2D, V17.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q6, [SP, #432]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V27.2D, V27.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
ORR V26.16B, V18.16B, V18.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q18, Q5, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V27.2D, V27.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ORR V8.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V4.2D, V10.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V5.2D, V22.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V5.2D, V10.2D, V26.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDP Q6, Q26, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMLA V26.2D, V30.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMUL V6.2D, V29.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V2.2D, V26.2D, V2.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V26.2D, V2.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q2, [SP, #720]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDP Q18, Q11, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V29.2D, V29.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V8.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q18, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V12.2D, V16.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V8.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V6.2D, V9.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q18, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V29.2D, V9.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q9, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q18, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V8.2D, V30.2D, V9.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V9.16B, V2.16B, V2.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V24.2D, V17.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V9.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V12.2D, V12.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V24.2D, V9.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q3, [SP, #528]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V8.2D, V24.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDP Q13, Q18, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FMUL V24.2D, V12.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
STR D24, [X12, X6]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FMLA V18.2D, V31.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V13.16B, V1.16B, V1.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V4.2D, V18.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V9.2D, V14.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q14, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V12.2D, V22.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
ORR V14.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V12.2D, V10.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q11, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
ST1 {V24.D[1]}, [X23]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDR Q4, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMUL V11.2D, V22.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q18, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
LDR Q24, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V14.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V15.2D, V20.2D, V14.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V25.2D, V19.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q13, [SP, #288]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V11.2D, V10.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V25.2D, V25.2D, V15.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V15.2D, V25.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
LDR Q3, [SP, #448]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
STR D15, [X12, X5]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V15.D[1]}, [X22]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D27, [X6, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
FMLA V2.2D, V31.2D, V3.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ST1 {V27.D[1]}, [X21]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
LDP Q18, Q14, [SP, #656]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q10, Q27, [SP, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
FADD V5.2D, V2.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDP Q4, Q24, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
LDP Q25, Q15, [SP, #624]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.67	vect (100.0%)
ORR V2.16B, V14.16B, V14.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V14.2D, V31.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V2.2D, V30.2D, V18.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V13.2D, V31.2D, V27.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V24.2D, V31.2D, V4.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V6.2D, V2.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V13.2D, V22.2D, V10.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V12.2D, V14.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V23.2D, V23.2D, V5.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FMLA V26.2D, V16.2D, V6.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
LDR Q16, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FMLA V21.2D, V19.2D, V13.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V24.2D, V22.2D, V16.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V22.16B, V15.16B, V15.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V9.2D, V19.2D, V12.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V22.2D, V30.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
ORR V30.16B, V15.16B, V15.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V28.2D, V20.2D, V24.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V30.2D, V31.2D, V25.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V19.2D, V22.2D, V29.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FADD V21.2D, V21.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
LDR Q28, [SP, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33	vect (100.0%)
FADD V31.2D, V30.2D, V11.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMLA V8.2D, V17.2D, V19.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FMLA V23.2D, V20.2D, V31.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25	vect (100.0%)
FADD V17.2D, V26.2D, V8.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
FMUL V26.2D, V21.2D, V28.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	3	0.25	vect (100.0%)
FADD V20.2D, V9.2D, V23.2D	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	2	0.25	vect (100.0%)
STR D26, [X5, X11]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V26.D[1]}, [X18]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D17, [X6, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V17.D[1]}, [X3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
STR D20, [X5, X7]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50	scal (50.0%)
ST1 {V20.D[1]}, [X16]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	4	1	scal (50.0%)
CMP X28, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 41b9c4 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x644>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

FMA

Workaround

Conversion instructions

Details

Workaround

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code