OV - exec - Loop 278

	Loop Id: 278	Module: exec	Source: OneBodyJastrowRef.h:134-146 [...]	Coverage: 0.01%

0x417a50 LDR	X2, [X23, #24]

0x417a54 ORR	X0, XZR, X22

0x417a58 LDRSW	X3, [X22, #672]

0x417a5c LDR	W1, [X26, #168]

0x417a60 LDR	D15, [X2, X3,LSL #3]

0x417a64 BL	49180c

0x417a68 LDR	X4, [X0, #72]

0x417a6c LDR	W10, [X26, #152]

0x417a70 ADD	X5, X4, X20

0x417a74 LDR	X27, [X5, #24]

0x417a78 CMP	W10, #0

0x417a7c B.LE	417f8c

0x417a80 LDR	X11, [X26, #456]

0x417a84 MOVI	D1, #0

0x417a88 MOVZ	X7, #0

0x417a8c UBFM	X10, X10, #62, #31

0x417a90 PTRUE	P7.B, ALL

0x417a94 CNTW	X9, ALL

0x417a98 HINT	#0

0x417a9c HINT	#0

  (277) 0x417aa0 UBFM	X17, X7, #63, #62

  (277) 0x417aa4 LDR	X30, [X11, X17]

  (277) 0x417aa8 CBZ	X30, 417f28

  (277) 0x417aac LDR	X21, [X26, #160]

  (277) 0x417ab0 LDR	X6, [X26, #328]

  (277) 0x417ab4 LDR	X28, [X21, #616]

  (277) 0x417ab8 LDR	X8, [X28, #24]

  (277) 0x417abc ADD	X12, X8, X7

  (277) 0x417ac0 LDR	W13, [X8, X7]

  (277) 0x417ac4 LDR	W14, [X12, #4]

  (277) 0x417ac8 CMP	W14, W13

  (277) 0x417acc B.LE	417f28

  (277) 0x417ad0 SUB	W15, W14, W13

  (277) 0x417ad4 SBFM	X18, X13, #61, #31

  (277) 0x417ad8 LDR	D6, [X30, #8]

  (277) 0x417adc ANDS	W0, W15, #128

  (277) 0x417ae0 MOVZ	W5, #0

  (277) 0x417ae4 ADD	X28, X27, X18

  (277) 0x417ae8 ORR	W21, WZR, W13

  (277) 0x417aec B.EQ	417c24

  (277) 0x417af0 CMP	W0, #1

  (277) 0x417af4 B.EQ	417bf8

  (277) 0x417af8 CMP	W0, #2

  (277) 0x417afc B.EQ	417bd4

  (277) 0x417b00 CMP	W0, #3

  (277) 0x417b04 B.EQ	417bb0

  (277) 0x417b08 CMP	W0, #4

  (277) 0x417b0c B.EQ	417b8c

  (277) 0x417b10 CMP	W0, #5

  (277) 0x417b14 B.EQ	417b68

  (277) 0x417b18 CMP	W0, #6

  (277) 0x417b1c B.EQ	417b44

  (277) 0x417b20 LDR	D7, [X27, X18]

  (277) 0x417b24 FCMPE	D6, D7

  (277) 0x417b28 B.LS	417b3c

  (277) 0x417b2c CMN	W13, #1

  (277) 0x417b30 B.EQ	417b3c

  (277) 0x417b34 MOVZ	W5, #1

  (277) 0x417b38 STR	D7, [X6]

  (277) 0x417b3c ADD	X28, X28, #8

  (277) 0x417b40 ADD	W21, W13, #1

  (277) 0x417b44 LDR	D8, [X28]

  (277) 0x417b48 FCMPE	D6, D8

  (277) 0x417b4c B.LS	417b60

  (277) 0x417b50 CMN	W21, #1

  (277) 0x417b54 B.EQ	417b60

  (277) 0x417b58 STR	D8, [X6, X5,UXTW #3]

  (277) 0x417b5c ADD	W5, W5, #1

  (277) 0x417b60 ADD	X28, X28, #8

  (277) 0x417b64 ADD	W21, W21, #1

  (277) 0x417b68 LDR	D26, [X28]

  (277) 0x417b6c FCMPE	D6, D26

  (277) 0x417b70 B.LS	417b84

  (277) 0x417b74 CMN	W21, #1

  (277) 0x417b78 B.EQ	417b84

  (277) 0x417b7c STR	D26, [X6, X5,UXTW #3]

  (277) 0x417b80 ADD	W5, W5, #1

  (277) 0x417b84 ADD	X28, X28, #8

  (277) 0x417b88 ADD	W21, W21, #1

  (277) 0x417b8c LDR	D9, [X28]

  (277) 0x417b90 FCMPE	D6, D9

  (277) 0x417b94 B.LS	417ba8

  (277) 0x417b98 CMN	W21, #1

  (277) 0x417b9c B.EQ	417ba8

  (277) 0x417ba0 STR	D9, [X6, X5,UXTW #3]

  (277) 0x417ba4 ADD	W5, W5, #1

  (277) 0x417ba8 ADD	X28, X28, #8

  (277) 0x417bac ADD	W21, W21, #1

  (277) 0x417bb0 LDR	D10, [X28]

  (277) 0x417bb4 FCMPE	D6, D10

  (277) 0x417bb8 B.LS	417bcc

  (277) 0x417bbc CMN	W21, #1

  (277) 0x417bc0 B.EQ	417bcc

  (277) 0x417bc4 STR	D10, [X6, X5,UXTW #3]

  (277) 0x417bc8 ADD	W5, W5, #1

  (277) 0x417bcc ADD	X28, X28, #8

  (277) 0x417bd0 ADD	W21, W21, #1

  (277) 0x417bd4 LDR	D20, [X28]

  (277) 0x417bd8 FCMPE	D6, D20

  (277) 0x417bdc B.LS	417bf0

  (277) 0x417be0 CMN	W21, #1

  (277) 0x417be4 B.EQ	417bf0

  (277) 0x417be8 STR	D20, [X6, X5,UXTW #3]

  (277) 0x417bec ADD	W5, W5, #1

  (277) 0x417bf0 ADD	X28, X28, #8

  (277) 0x417bf4 ADD	W21, W21, #1

  (277) 0x417bf8 LDR	D11, [X28]

  (277) 0x417bfc FCMPE	D6, D11

  (277) 0x417c00 B.LS	417c14

  (277) 0x417c04 CMN	W21, #1

  (277) 0x417c08 B.EQ	417c14

  (277) 0x417c0c STR	D11, [X6, X5,UXTW #3]

  (277) 0x417c10 ADD	W5, W5, #1

  (277) 0x417c14 ADD	W21, W21, #1

  (277) 0x417c18 ADD	X28, X28, #8

  (277) 0x417c1c CMP	W14, W21

  (277) 0x417c20 B.EQ	417d34

    (279) 0x417c24 LDR	D12, [X28]

    (279) 0x417c28 FCMPE	D6, D12

    (279) 0x417c2c B.LS	417c40

    (279) 0x417c30 CMN	W21, #1

    (279) 0x417c34 B.EQ	417c40

    (279) 0x417c38 STR	D12, [X6, X5,UXTW #3]

    (279) 0x417c3c ADD	W5, W5, #1

    (279) 0x417c40 LDR	D13, [X28, #8]

    (279) 0x417c44 ADD	W16, W21, #1

    (279) 0x417c48 ADD	X3, X28, #8

    (279) 0x417c4c FCMPE	D6, D13

    (279) 0x417c50 B.LS	417c64

    (279) 0x417c54 CMN	W16, #1

    (279) 0x417c58 B.EQ	417c64

    (279) 0x417c5c STR	D13, [X6, X5,UXTW #3]

    (279) 0x417c60 ADD	W5, W5, #1

    (279) 0x417c64 LDR	D16, [X3, #8]

    (279) 0x417c68 ADD	W25, W16, #1

    (279) 0x417c6c FCMPE	D6, D16

    (279) 0x417c70 B.LS	417c84

    (279) 0x417c74 CMN	W25, #1

    (279) 0x417c78 B.EQ	417c84

    (279) 0x417c7c STR	D16, [X6, X5,UXTW #3]

    (279) 0x417c80 ADD	W5, W5, #1

    (279) 0x417c84 LDR	D17, [X3, #16]

    (279) 0x417c88 ADD	W2, W16, #2

    (279) 0x417c8c FCMPE	D6, D17

    (279) 0x417c90 B.LS	417ca4

    (279) 0x417c94 CMN	W2, #1

    (279) 0x417c98 B.EQ	417ca4

    (279) 0x417c9c STR	D17, [X6, X5,UXTW #3]

    (279) 0x417ca0 ADD	W5, W5, #1

    (279) 0x417ca4 LDR	D18, [X3, #24]

    (279) 0x417ca8 ADD	W1, W16, #3

    (279) 0x417cac FCMPE	D6, D18

    (279) 0x417cb0 B.LS	417cc4

    (279) 0x417cb4 CMN	W1, #1

    (279) 0x417cb8 B.EQ	417cc4

    (279) 0x417cbc STR	D18, [X6, X5,UXTW #3]

    (279) 0x417cc0 ADD	W5, W5, #1

    (279) 0x417cc4 LDR	D22, [X3, #32]

    (279) 0x417cc8 ADD	W4, W16, #4

    (279) 0x417ccc FCMPE	D6, D22

    (279) 0x417cd0 B.LS	417ce4

    (279) 0x417cd4 CMN	W4, #1

    (279) 0x417cd8 B.EQ	417ce4

    (279) 0x417cdc STR	D22, [X6, X5,UXTW #3]

    (279) 0x417ce0 ADD	W5, W5, #1

    (279) 0x417ce4 LDR	D30, [X3, #40]

    (279) 0x417ce8 ADD	W24, W16, #5

    (279) 0x417cec FCMPE	D6, D30

    (279) 0x417cf0 B.LS	417d04

    (279) 0x417cf4 CMN	W24, #1

    (279) 0x417cf8 B.EQ	417d04

    (279) 0x417cfc STR	D30, [X6, X5,UXTW #3]

    (279) 0x417d00 ADD	W5, W5, #1

    (279) 0x417d04 LDR	D31, [X3, #48]

    (279) 0x417d08 ADD	W17, W16, #6

    (279) 0x417d0c FCMPE	D6, D31

    (279) 0x417d10 B.LS	417d24

    (279) 0x417d14 CMN	W17, #1

    (279) 0x417d18 B.EQ	417d24

    (279) 0x417d1c STR	D31, [X6, X5,UXTW #3]

    (279) 0x417d20 ADD	W5, W5, #1

    (279) 0x417d24 ADD	W21, W16, #7

    (279) 0x417d28 ADD	X28, X3, #56

    (279) 0x417d2c CMP	W14, W21

    (279) 0x417d30 B.NE	417c24

  (277) 0x417d34 CBZ	W5, 417f28

  (277) 0x417d38 ADD	X12, X30, #568

  (277) 0x417d3c LD1RD	{Z3.D}, P7/Z, [X30, #3]

  (277) 0x417d40 LD1RD	{Z4.D}, P7/Z, [X30, #4]

  (277) 0x417d44 LD1RD	{Z5.D}, P7/Z, [X30, #5]

  (277) 0x417d48 LD1RD	{Z6.D}, P7/Z, [X30, #6]

  (277) 0x417d4c LD1RD	{Z7.D}, P7/Z, [X30, #7]

  (277) 0x417d50 LD1RD	{Z16.D}, P7/Z, [X30, #8]

  (277) 0x417d54 LD1RD	{Z17.D}, P7/Z, [X30, #9]

  (277) 0x417d58 LD1RD	{Z18.D}, P7/Z, [X30, #10]

  (277) 0x417d5c LD1RD	{Z19.D}, P7/Z, [X30, #11]

  (277) 0x417d60 LD1RD	{Z20.D}, P7/Z, [X30, #12]

  (277) 0x417d64 LD1RD	{Z21.D}, P7/Z, [X30, #13]

  (277) 0x417d68 LD1RD	{Z22.D}, P7/Z, [X30, #14]

  (277) 0x417d6c LD1RD	{Z23.D}, P7/Z, [X30, #15]

  (277) 0x417d70 LD1RD	{Z24.D}, P7/Z, [X30, #16]

  (277) 0x417d74 LD1RD	{Z25.D}, P7/Z, [X30, #17]

  (277) 0x417d78 LD1RD	{Z26.D}, P7/Z, [X30, #18]

  (277) 0x417d7c LDR	X30, [X30, #536]

  (277) 0x417d80 MOVZ	X14, #0

  (277) 0x417d84 ADDVL	X8, X6, #1

  (277) 0x417d88 ORR	W13, WZR, W5

  (277) 0x417d8c DUP	Z28.D, #0

  (277) 0x417d90 UQDECD	W13, ALL

  (277) 0x417d94 LD1RD	{Z2.D}, P7/Z, [X12]

  (277) 0x417d98 WHILELO	P5.D, WZR, W13

  (277) 0x417d9c ORR	Z29.D, Z28.D, Z28.D

  (277) 0x417da0 WHILELO	P6.D, WZR, W5

    (280) 0x417da4 LD1D	{Z0.D}, P5/Z, [X8, X14,LSL #3]

    (280) 0x417da8 LD1D	{Z27.D}, P6/Z, [X6, X14,LSL #3]

    (280) 0x417dac FMUL	Z8.D, Z2.D, Z0.D

    (280) 0x417db0 FMUL	Z14.D, Z2.D, Z27.D

    (280) 0x417db4 MOVPRFX	Z9, Z8

    (280) 0x417db8 FRINTZ	Z9.D, P7/M, Z8.D

    (280) 0x417dbc MOVPRFX	Z10, Z8

    (280) 0x417dc0 FCVTZS	Z10.S, P7/M, Z8.D

    (280) 0x417dc4 FSUB	Z31.D, Z8.D, Z9.D

    (280) 0x417dc8 MOVPRFX	Z11, Z14

    (280) 0x417dcc FCVTZS	Z11.S, P7/M, Z14.D

    (280) 0x417dd0 FMUL	Z27.D, Z31.D, Z31.D

    (280) 0x417dd4 MOVPRFX	Z8, Z18

    (280) 0x417dd8 FMLA	Z8.D, P7/M, Z17.D, Z31.D

    (280) 0x417ddc FMUL	Z0.D, Z27.D, Z31.D

    (280) 0x417de0 FMUL	Z12.D, Z16.D, Z27.D

    (280) 0x417de4 FMLA	Z12.D, P7/M, Z7.D, Z0.D

    (280) 0x417de8 UZP1	Z30.S, Z11.S, Z10.S

    (280) 0x417dec FADD	Z11.D, Z8.D, Z12.D

    (280) 0x417df0 MOVPRFX	Z13, Z30

    (280) 0x417df4 ADD	Z13.S, Z13.S, #1

    (280) 0x417df8 MOVPRFX	Z8, Z6

    (280) 0x417dfc FMLA	Z8.D, P7/M, Z5.D, Z31.D

    (280) 0x417e00 SUNPKHI	Z9.D, Z13

    (280) 0x417e04 LD1D	{Z12.D}, P5/Z, [X30, Z9.D,LSL #3]

    (280) 0x417e08 FMUL	Z10.D, Z4.D, Z27.D

    (280) 0x417e0c FMUL	Z11.D, Z11.D, Z12.D

    (280) 0x417e10 FMLA	Z10.D, P7/M, Z3.D, Z0.D

    (280) 0x417e14 SUNPKHI	Z9.D, Z30

    (280) 0x417e18 FADD	Z12.D, Z8.D, Z10.D

    (280) 0x417e1c LD1D	{Z8.D}, P5/Z, [X30, Z9.D,LSL #3]

    (280) 0x417e20 FMUL	Z10.D, Z20.D, Z27.D

    (280) 0x417e24 FMAD	Z12.D, P7/M, Z8.D, Z11.D

    (280) 0x417e28 FMLA	Z10.D, P7/M, Z19.D, Z0.D

    (280) 0x417e2c MOVPRFX	Z11, Z22

    (280) 0x417e30 FMLA	Z11.D, P7/M, Z21.D, Z31.D

    (280) 0x417e34 FMUL	Z27.D, Z27.D, Z24.D

    (280) 0x417e38 FADD	Z8.D, Z11.D, Z10.D

    (280) 0x417e3c FMAD	Z0.D, P7/M, Z23.D, Z27.D

    (280) 0x417e40 FADD	Z28.D, P5/M, Z28.D, Z12.D

    (280) 0x417e44 MOVPRFX	Z27, Z30

    (280) 0x417e48 ADD	Z27.S, Z27.S, #3

    (280) 0x417e4c MOVPRFX	Z12, Z30

    (280) 0x417e50 ADD	Z12.S, Z12.S, #2

    (280) 0x417e54 SUNPKHI	Z10.D, Z27

    (280) 0x417e58 SUNPKLO	Z30.D, Z30

    (280) 0x417e5c LD1D	{Z11.D}, P5/Z, [X30, Z10.D,LSL #3]

    (280) 0x417e60 FMAD	Z31.D, P7/M, Z25.D, Z26.D

    (280) 0x417e64 FADD	Z31.D, Z31.D, Z0.D

    (280) 0x417e68 SUNPKHI	Z0.D, Z12

    (280) 0x417e6c LD1D	{Z9.D}, P5/Z, [X30, Z0.D,LSL #3]

    (280) 0x417e70 FMLA	Z28.D, P5/M, Z8.D, Z9.D

    (280) 0x417e74 SUNPKLO	Z8.D, Z12

    (280) 0x417e78 FMLA	Z28.D, P5/M, Z11.D, Z31.D

    (280) 0x417e7c LD1D	{Z0.D}, P6/Z, [X30, Z8.D,LSL #3]

    (280) 0x417e80 LD1D	{Z11.D}, P6/Z, [X30, Z30.D,LSL #3]

    (280) 0x417e84 SUNPKLO	Z12.D, Z27

    (280) 0x417e88 MOVPRFX	Z31, Z14

    (280) 0x417e8c FRINTZ	Z31.D, P7/M, Z14.D

    (280) 0x417e90 SUNPKLO	Z13.D, Z13

    (280) 0x417e94 FSUB	Z8.D, Z14.D, Z31.D

    (280) 0x417e98 FMUL	Z30.D, Z8.D, Z8.D

    (280) 0x417e9c FMUL	Z27.D, Z30.D, Z8.D

    (280) 0x417ea0 FMUL	Z14.D, Z16.D, Z30.D

    (280) 0x417ea4 FMLA	Z14.D, P7/M, Z7.D, Z27.D

    (280) 0x417ea8 LD1D	{Z10.D}, P6/Z, [X30, Z13.D,LSL #3]

    (280) 0x417eac ADD	X14, X14, X9

    (280) 0x417eb0 LD1D	{Z13.D}, P6/Z, [X30, Z12.D,LSL #3]

    (280) 0x417eb4 WHILELO	P5.D, W14, W13

    (280) 0x417eb8 MOVPRFX	Z12, Z18

    (280) 0x417ebc FMLA	Z12.D, P7/M, Z17.D, Z8.D

    (280) 0x417ec0 FADD	Z31.D, Z12.D, Z14.D

    (280) 0x417ec4 MOVPRFX	Z14, Z6

    (280) 0x417ec8 FMLA	Z14.D, P7/M, Z5.D, Z8.D

    (280) 0x417ecc FMUL	Z12.D, Z31.D, Z10.D

    (280) 0x417ed0 FMUL	Z9.D, Z4.D, Z30.D

    (280) 0x417ed4 FMUL	Z10.D, Z20.D, Z30.D

    (280) 0x417ed8 FMLA	Z9.D, P7/M, Z3.D, Z27.D

    (280) 0x417edc MOVPRFX	Z31, Z22

    (280) 0x417ee0 FMLA	Z31.D, P7/M, Z21.D, Z8.D

    (280) 0x417ee4 FADD	Z9.D, Z14.D, Z9.D

    (280) 0x417ee8 FMUL	Z30.D, Z30.D, Z24.D

    (280) 0x417eec FMAD	Z9.D, P7/M, Z11.D, Z12.D

    (280) 0x417ef0 FMAD	Z8.D, P7/M, Z25.D, Z26.D

    (280) 0x417ef4 MOVPRFX	Z11, Z10

    (280) 0x417ef8 FMLA	Z11.D, P7/M, Z19.D, Z27.D

    (280) 0x417efc FADD	Z29.D, P6/M, Z29.D, Z9.D

    (280) 0x417f00 FMAD	Z27.D, P7/M, Z23.D, Z30.D

    (280) 0x417f04 FADD	Z14.D, Z31.D, Z11.D

    (280) 0x417f08 FMLA	Z29.D, P6/M, Z14.D, Z0.D

    (280) 0x417f0c FADD	Z0.D, Z8.D, Z27.D

    (280) 0x417f10 FMLA	Z29.D, P6/M, Z13.D, Z0.D

    (280) 0x417f14 WHILELO	P6.D, W14, W5

    (280) 0x417f18 B.NE	417da4

  (277) 0x417f1c FADD	Z2.D, Z29.D, Z28.D

  (277) 0x417f20 FADDV	D28, P7, Z2.D

  (277) 0x417f24 FADD	D1, D1, D28

  (277) 0x417f28 ADD	X7, X7, #4

  (277) 0x417f2c CMP	X10, X7

  (277) 0x417f30 B.NE	417aa0

0x417f34 FSUB	D15, D15, S1

0x417f38 FMOV	D0, D15

0x417f3c ADD	X20, X20, #40

0x417f40 BL	403db0

0x417f44 LDR	X6, [SP, #160]

0x417f48 LDP	X15, X18, [X6]

0x417f4c SUB	X0, X18, X15

0x417f50 STR	D0, [X15, X19,UXTW #3]

0x417f54 ADD	X19, X19, #1

0x417f58 CMP	X19, X0,ASR #3

0x417f5c B.CC	417a50

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 993 - 1131

--------------------------------------------------------------------------------

993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h: 134 - 146

--------------------------------------------------------------------------------

134:     for (int k = 0; k < ratios.size(); ++k)

135:       ratios[k] = std::exp(Vat[VP.refPtcl] - computeU(VP.getDistTableAB(myTableID).getDistRow(k).data()));

136:   }

137:

138:   inline valT computeU(const valT* dist)

139:   {

140:     valT curVat(0);

141:     if (NumGroups > 0)

142:     {

143:       for (int jg = 0; jg < NumGroups; ++jg)

144:       {

145:         if (F[jg] != nullptr)

146:           curVat += F[jg]->evaluateV(-1, Ions.first(jg), Ions.last(jg), dist, DistCompressed.data());

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 231 - 260

--------------------------------------------------------------------------------

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

Coverage (%)	Name	Source Location	Module
►97.71+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Metric	Value
CQA speedup if no scalar integer	3.83
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	1.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12,
Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	stl_vector.h:993-993,stl_vector.h:1131-1131,OneBodyJastrowRef.h:134-135,OneBodyJastrowRef.h:140-141,OhmmsVector.h:223-223,OhmmsVector.h:249-249,BsplineFunctor.h:246-246
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	2.84
Front-end cycles	3.63
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.17
P7 cycles	2.17
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	3.83
P13 cycles	3.50
P14 cycles	3.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.26
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.91
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	48.44
Vector-efficiency ratio load	41.67
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.57

Metric	Value
CQA speedup if no scalar integer	3.83
CQA speedup if FP arith vectorized	1.28
CQA speedup if fully vectorized	1.35
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.05
Bottlenecks	P12,
Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source	stl_vector.h:993-993,stl_vector.h:1131-1131,OneBodyJastrowRef.h:134-135,OneBodyJastrowRef.h:140-141,OhmmsVector.h:223-223,OhmmsVector.h:249-249,BsplineFunctor.h:246-246
Source loop unroll info	NA
Source loop unroll confidence level	NA
Unroll/vectorization loop type	NA
Unroll factor	NA
CQA cycles	3.83
CQA cycles if no scalar integer	1.00
CQA cycles if FP arith vectorized	3.00
CQA cycles if fully vectorized	2.84
Front-end cycles	3.63
P0 cycles	2.00
P1 cycles	2.00
P2 cycles	2.17
P3 cycles	2.17
P4 cycles	2.17
P5 cycles	2.17
P6 cycles	2.17
P7 cycles	2.17
P8 cycles	1.00
P9 cycles	1.00
P10 cycles	1.00
P11 cycles	1.00
P12 cycles	3.83
P13 cycles	3.50
P14 cycles	3.67
P15 cycles	0.00
P16 cycles	0.00
DIV/SQRT cycles	0.00
Inter-iter dependencies cycles	NA
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	31.00
Nb uops	29.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	0.26
Nb FLOP add-sub	1.00
Nb FLOP mul	0.00
Nb FLOP fma	0.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	21.91
Bytes prefetched	0.00
Bytes loaded	76.00
Bytes stored	8.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	0.00
Vectorization ratio load	0.00
Vectorization ratio store	0.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	0.00
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	0.00
Vector-efficiency ratio all	48.44
Vector-efficiency ratio load	41.67
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	50.00
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	53.57

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	OneBodyJastrowRef.h:134-146
Module	exec

The loop is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:134-146
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your loop is not vectorized. Only 48% of vector register length is used (average across all VPU instructions). By vectorizing your loop, you can lower the cost of an iteration from 3.83 to 2.84 cycles (1.35x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 76 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00
cycles	2.00	2.00	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.63
Overall L1	3.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

20% of peak load performance is reached (19.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 417f38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X2, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X3, [X22, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X26, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D15, [X2, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
BL 49180c <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W10, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X4, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X27, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 417f8c <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X26, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ X7, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X10, X10, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
CNTW X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
FSUB D15, D15, S1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X20, X20, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 403db0 <@plt_start@+0xc0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X18, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X0, X18, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X15, X19,UXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X19, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X19, X0,ASR #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
B.CC 417a50 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Function	miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)
Source file and lines	OneBodyJastrowRef.h:134-146
Module	exec

The loop is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:134-146
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:231-260

Warnings:

Non-innermost loop: analyzing only self part (ignoring child loops).
Ignoring paths for analysis
Failed to get the number of paths
RecMII not computed since number of paths is unknown or > max_paths
Streams not analyzed since number of paths is unknown or > max_paths

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized loop can use their full power.

Workaround

Try another compiler or update/tune your current one
Remove inter-iterations dependences from your loop and make it unit-stride:
- If your arrays have 2 or more dimensions, check whether elements are accessed contiguously and, otherwise, try to permute loops accordingly: C storage order is row-major: for(i) for(j) a[j][i] = b[j][i]; (slow, non stride 1) => for(i) for(j) a[i][j] = b[i][j]; (fast, stride 1)
- If your loop streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 3.83 to 1.00 cycles (3.83x speedup).

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 1 FP arithmetical operations:

1: addition or subtraction

The binary loop is loading 76 bytes. The binary loop is storing 8 bytes.

Arithmetic intensity

Arithmetic intensity is 0.01 FP operations per loaded or stored byte.

General properties

nb instructions	31
loop length	124
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00
cycles	2.00	2.00	2.17	2.17	2.17	2.17	2.17	2.17	1.00	1.00	1.00	1.00	3.83	3.50	3.67	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.63
Overall L1	3.83

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 3.83 cycles. At this rate:

20% of peak load performance is reached (19.83 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.09 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 417f38

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
LDR X2, [X23, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDRSW X3, [X22, #672]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W1, [X26, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR D15, [X2, X3,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
BL 49180c <_ZNK11qmcplusplus11ParticleSet14getDistTableABEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W10, [X26, #152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X5, X4, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X27, [X5, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CMP W10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 417f8c <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x58c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X11, [X26, #456]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVI D1, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ X7, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X10, X10, #62, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
CNTW X9, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
FSUB D15, D15, S1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D0, D15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X20, X20, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
BL 403db0 <@plt_start@+0xc0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X15, X18, [X6]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
SUB X0, X18, X15	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D0, [X15, X19,UXTW #3]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X19, X19, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP X19, X0,ASR #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
B.CC 417a50 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code