OV - exec - Function qmcplusplus::TimerType<std::chrono::_V2::system

	Function: qmcplusplus::TimerType<std::chrono::_V2::system_clock>::stop()	Module: exec	Source: NewTimer.cpp:84-120 [...]	Coverage (incl. loops): 0.02% \| (excl. loops): 0.02%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h: 151 - 172

--------------------------------------------------------------------------------

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 119 - 124

--------------------------------------------------------------------------------

119:       if (!(this->long_buckets[j] == rhs.long_buckets[j]))

120:       {

121:         return this->long_buckets[j] < rhs.long_buckets[j];

122:       }

123:     }

124:     return this->long_buckets[N - 1] < rhs.long_buckets[N - 1];

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/tuple: 2887 - 2888

--------------------------------------------------------------------------------

2887:       : first(std::forward<_Args1>(std::get<_Indexes1>(__tuple1))...),

2888: 	second(std::forward<_Args2>(std::get<_Indexes2>(__tuple2))...)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp: 84 - 120

--------------------------------------------------------------------------------

84: void TimerType<CLOCK>::stop()

85: {

86:   if (active)

[...]

98:     bool is_true_master(true);

99:     for (int level = omp_get_level(); level > 0; level--)

100:       if (omp_get_ancestor_thread_num(level) != 0)

101:         is_true_master = false;

102:     if (is_true_master)

103:     {

104:       std::chrono::duration<double> elapsed = CLOCK::now() - start_time;

105:       total_time += elapsed.count();

106:       num_calls++;

107:

108:       per_stack_total_time[current_stack_key] += elapsed.count();

109:       per_stack_num_calls[current_stack_key] += 1;

110:

111:       if (manager)

112:         manager->pop_timer(this);

[...]

120: }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_tree.h: 269 - 2459

--------------------------------------------------------------------------------

269:       _Rb_tree_iterator(_Base_ptr __x) _GLIBCXX_NOEXCEPT

[...]

283: 	_M_node = _Rb_tree_increment(_M_node);

[...]

298: 	_M_node = _Rb_tree_decrement(_M_node);

299: 	return *this;

[...]

631:       }

[...]

733:       { return static_cast<_Link_type>(this->_M_impl._M_header._M_parent); }

[...]

748:       { return &this->_M_impl._M_header; }

[...]

778:       { return static_cast<_Link_type>(__x->_M_left); }

[...]

786:       { return static_cast<_Link_type>(__x->_M_right); }

[...]

1636: 	~_Auto_node()

[...]

1947:       while (__x != 0)

1948: 	if (!_M_impl._M_key_compare(_S_key(__x), __k))

1949: 	  __y = __x, __x = _S_left(__x);

[...]

2109:       _Base_ptr __y = _M_end();

2110:       bool __comp = true;

2111:       while (__x != 0)

2112: 	{

2113: 	  __y = __x;

2114: 	  __comp = _M_impl._M_key_compare(__k, _S_key(__x));

2115: 	  __x = __comp ? _S_left(__x) : _S_right(__x);

2116: 	}

2117:       iterator __j = iterator(__y);

2118:       if (__comp)

2119: 	{

2120: 	  if (__j == begin())

2121: 	    return _Res(__x, __y);

2122: 	  else

2123: 	    --__j;

2124: 	}

2125:       if (_M_impl._M_key_compare(_S_key(__j._M_node), __k))

[...]

2217: 	      && _M_impl._M_key_compare(_S_key(_M_rightmost()), __k))

2218: 	    return _Res(0, _M_rightmost());

2219: 	  else

2220: 	    return _M_get_insert_unique_pos(__k);

2221: 	}

2222:       else if (_M_impl._M_key_compare(__k, _S_key(__pos._M_node)))

2223: 	{

2224: 	  // First, try before...

2225: 	  iterator __before = __pos;

2226: 	  if (__pos._M_node == _M_leftmost()) // begin()

2227: 	    return _Res(_M_leftmost(), _M_leftmost());

2228: 	  else if (_M_impl._M_key_compare(_S_key((--__before)._M_node), __k))

2229: 	    {

2230: 	      if (_S_right(__before._M_node) == 0)

[...]

2242: 	  if (__pos._M_node == _M_rightmost())

2243: 	    return _Res(0, _M_rightmost());

2244: 	  else if (_M_impl._M_key_compare(__k, _S_key((++__after)._M_node)))

2245: 	    {

2246: 	      if (_S_right(__pos._M_node) == 0)

[...]

2373:     _Rb_tree<_Key, _Val, _KeyOfValue, _Compare, _Alloc>::

2374:     _M_insert_node(_Base_ptr __x, _Base_ptr __p, _Link_type __z)

2375:     -> iterator

2376:     {

2377:       bool __insert_left = (__x != 0 || __p == _M_end()

2378: 			    || _M_impl._M_key_compare(_S_key(__z),

2379: 						      _S_key(__p)));

2380:

2381:       _Rb_tree_insert_and_rebalance(__insert_left, __z, __p,

2382: 				    this->_M_impl._M_header);

2383:       ++_M_impl._M_node_count;

[...]

2459: 	auto __res = _M_get_insert_hint_unique_pos(__pos, __z._M_key());

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_map.h: 511 - 511

--------------------------------------------------------------------------------

511: 	if (__i == end() || key_comp()(__k, (*__i).first))

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/chrono.h: 214 - 716

--------------------------------------------------------------------------------

214: 	      static_cast<_CR>(__d.count()) / static_cast<_CR>(_CF::den)));

[...]

716: 	return __cd(__cd(__lhs).count() - __cd(__rhs).count());

0x4d57e0 STP	X29, X30, [SP, #928]!

0x4d57e4 ADD	X29, SP, #0

0x4d57e8 STP	X21, X22, [SP, #32]

0x4d57ec LDRB	W21, [X0, #56]

0x4d57f0 TBNZ	W21, #0, 4d5800

(2622) 0x4d57f4 LDP	X21, X22, [SP, #32]

(2622) 0x4d57f8 LDP	X29, X30, [SP], #96

(2622) 0x4d57fc RET

(2622) 0x4d5800 STP	X19, X20, [SP, #16]

(2622) 0x4d5804 ORR	W20, WZR, W21

(2622) 0x4d5808 STP	X23, X24, [SP, #48]

(2622) 0x4d580c ORR	X23, XZR, X0

(2622) 0x4d5810 BL	404400

(2622) 0x4d5814 ORR	W19, WZR, W0

(2622) 0x4d5818 CMP	W0, #0

(2622) 0x4d581c B.LE	4d59cc

(2622) 0x4d5820 ANDS	W1, W0, #128

(2622) 0x4d5824 SUB	W22, W0, #1

(2622) 0x4d5828 B.EQ	4d58f0

(2622) 0x4d582c CMP	W1, #1

(2622) 0x4d5830 B.EQ	4d58d4

(2622) 0x4d5834 CMP	W1, #2

(2622) 0x4d5838 B.EQ	4d58bc

(2622) 0x4d583c CMP	W1, #3

(2622) 0x4d5840 B.EQ	4d58a4

(2622) 0x4d5844 CMP	W1, #4

(2622) 0x4d5848 B.EQ	4d588c

(2622) 0x4d584c CMP	W1, #5

(2622) 0x4d5850 B.EQ	4d5874

(2622) 0x4d5854 CMP	W1, #6

(2622) 0x4d5858 B.NE	4d5b6c

(2622) 0x4d585c ORR	W0, WZR, W19

(2622) 0x4d5860 SUB	W19, W19, #1

(2622) 0x4d5864 BL	404140

(2622) 0x4d5868 CMP	W0, #0

(2622) 0x4d586c CCMP	W20, #0, #4, #0

(2622) 0x4d5870 CSINC	W20, WZR, WZR, #0

(2622) 0x4d5874 ORR	W0, WZR, W19

(2622) 0x4d5878 SUB	W19, W19, #1

(2622) 0x4d587c BL	404140

(2622) 0x4d5880 CMP	W0, #0

(2622) 0x4d5884 CCMP	W20, #0, #4, #0

(2622) 0x4d5888 CSINC	W20, WZR, WZR, #0

(2622) 0x4d588c ORR	W0, WZR, W19

(2622) 0x4d5890 SUB	W19, W19, #1

(2622) 0x4d5894 BL	404140

(2622) 0x4d5898 CMP	W0, #0

(2622) 0x4d589c CCMP	W20, #0, #4, #0

(2622) 0x4d58a0 CSINC	W20, WZR, WZR, #0

(2622) 0x4d58a4 ORR	W0, WZR, W19

(2622) 0x4d58a8 SUB	W19, W19, #1

(2622) 0x4d58ac BL	404140

(2622) 0x4d58b0 CMP	W0, #0

(2622) 0x4d58b4 CCMP	W20, #0, #4, #0

(2622) 0x4d58b8 CSINC	W20, WZR, WZR, #0

(2622) 0x4d58bc ORR	W0, WZR, W19

(2622) 0x4d58c0 SUB	W19, W19, #1

(2622) 0x4d58c4 BL	404140

(2622) 0x4d58c8 CMP	W0, #0

(2622) 0x4d58cc CCMP	W20, #0, #4, #0

(2622) 0x4d58d0 CSINC	W20, WZR, WZR, #0

(2622) 0x4d58d4 ORR	W0, WZR, W19

(2622) 0x4d58d8 BL	404140

(2622) 0x4d58dc CMP	W0, #0

(2622) 0x4d58e0 CCMP	W20, #0, #4, #0

(2622) 0x4d58e4 CSINC	W20, WZR, WZR, #0

(2622) 0x4d58e8 SUBS	W19, W19, #1

(2622) 0x4d58ec B.EQ	4d59b4

  (2631) 0x4d58f0 ORR	W0, WZR, W19

  (2631) 0x4d58f4 SUB	W24, W19, #1

  (2631) 0x4d58f8 BL	404140

  (2631) 0x4d58fc CMP	W0, #0

  (2631) 0x4d5900 ORR	W0, WZR, W24

  (2631) 0x4d5904 CCMP	W20, #0, #4, #0

  (2631) 0x4d5908 CSINC	W22, WZR, WZR, #0

  (2631) 0x4d590c BL	404140

  (2631) 0x4d5910 ORR	W2, WZR, W0

  (2631) 0x4d5914 SUB	W0, W24, #1

  (2631) 0x4d5918 CMP	W2, #0

  (2631) 0x4d591c CCMP	W22, #0, #4, #0

  (2631) 0x4d5920 CSINC	W20, WZR, WZR, #0

  (2631) 0x4d5924 BL	404140

  (2631) 0x4d5928 ORR	W3, WZR, W0

  (2631) 0x4d592c SUB	W0, W19, #3

  (2631) 0x4d5930 CMP	W3, #0

  (2631) 0x4d5934 CCMP	W20, #0, #4, #0

  (2631) 0x4d5938 CSINC	W24, WZR, WZR, #0

  (2631) 0x4d593c BL	404140

  (2631) 0x4d5940 ORR	W4, WZR, W0

  (2631) 0x4d5944 SUB	W0, W19, #4

  (2631) 0x4d5948 CMP	W4, #0

  (2631) 0x4d594c CCMP	W24, #0, #4, #0

  (2631) 0x4d5950 CSINC	W22, WZR, WZR, #0

  (2631) 0x4d5954 BL	404140

  (2631) 0x4d5958 ORR	W5, WZR, W0

  (2631) 0x4d595c SUB	W0, W19, #5

  (2631) 0x4d5960 CMP	W5, #0

  (2631) 0x4d5964 CCMP	W22, #0, #4, #0

  (2631) 0x4d5968 CSINC	W20, WZR, WZR, #0

  (2631) 0x4d596c BL	404140

  (2631) 0x4d5970 ORR	W6, WZR, W0

  (2631) 0x4d5974 SUB	W0, W19, #6

  (2631) 0x4d5978 CMP	W6, #0

  (2631) 0x4d597c CCMP	W20, #0, #4, #0

  (2631) 0x4d5980 CSINC	W24, WZR, WZR, #0

  (2631) 0x4d5984 BL	404140

  (2631) 0x4d5988 ORR	W7, WZR, W0

  (2631) 0x4d598c SUB	W0, W19, #7

  (2631) 0x4d5990 CMP	W7, #0

  (2631) 0x4d5994 CCMP	W24, #0, #4, #0

  (2631) 0x4d5998 CSINC	W22, WZR, WZR, #0

  (2631) 0x4d599c BL	404140

  (2631) 0x4d59a0 CMP	W0, #0

  (2631) 0x4d59a4 CCMP	W22, #0, #4, #0

  (2631) 0x4d59a8 CSINC	W20, WZR, WZR, #0

  (2631) 0x4d59ac SUBS	W19, W19, #8

  (2631) 0x4d59b0 B.NE	4d58f0

(2622) 0x4d59b4 TBNZ	W20, #0, 4d59cc

(2622) 0x4d59b8 LDP	X19, X20, [SP, #16]

(2622) 0x4d59bc LDP	X23, X24, [SP, #48]

(2622) 0x4d59c0 LDP	X21, X22, [SP, #32]

(2622) 0x4d59c4 LDP	X29, X30, [SP], #96

(2622) 0x4d59c8 RET

(2622) 0x4d59cc STP	X25, X26, [SP, #64]

(2622) 0x4d59d0 ADD	X24, X23, #104

(2622) 0x4d59d4 ADD	X20, X23, #112

(2622) 0x4d59d8 STR	X27, [SP, #80]

(2622) 0x4d59dc STR	D15, [SP, #88]

(2622) 0x4d59e0 BL	4041b0

(2622) 0x4d59e4 LDR	X9, [X23]

(2622) 0x4d59e8 ADRP	X8,

(2622) 0x4d59ec LDR	D15, [X8, #2920]

(2622) 0x4d59f0 LDR	D0, [X23, #8]

(2622) 0x4d59f4 SUB	X0, X0, X9

(2622) 0x4d59f8 LDR	X10, [X23, #16]

(2622) 0x4d59fc SCVTF	D1, X0

(2622) 0x4d5a00 LDR	X15, [X24, #16]

(2622) 0x4d5a04 ADD	X11, X10, #1

(2622) 0x4d5a08 FMUL	D15, D1, D15

(2622) 0x4d5a0c STR	X11, [X23, #16]

(2622) 0x4d5a10 FADD	D2, D0, D15

(2622) 0x4d5a14 STR	D2, [X23, #8]

(2622) 0x4d5a18 CBZ	X15, 4d5b84

(2622) 0x4d5a1c LDR	X16, [X23, #80]

(2622) 0x4d5a20 ORR	X19, XZR, X20

  (2628) 0x4d5a24 ADD	X12, X15, #32

  (2628) 0x4d5a28 LDR	X13, [X15, #32]

  (2628) 0x4d5a2c CMP	X13, X16

  (2628) 0x4d5a30 B.NE	4d5b40

  (2628) 0x4d5a34 LDR	X13, [X12, #8]

  (2628) 0x4d5a38 LDR	X14, [X23, #88]

  (2628) 0x4d5a3c CMP	X14, X13

  (2628) 0x4d5a40 B.NE	4d5b44

  (2628) 0x4d5a44 ORR	X19, XZR, X15

  (2628) 0x4d5a48 LDR	X15, [X15, #16]

  (2628) 0x4d5a4c CBNZ	X15, 4d5a24

(2622) 0x4d5a50 CMP	X20, X19

(2622) 0x4d5a54 B.EQ	4d5b84

(2622) 0x4d5a58 LDR	X17, [X19, #32]

(2622) 0x4d5a5c ADD	X25, X19, #32

(2622) 0x4d5a60 CMP	X17, X16

(2622) 0x4d5a64 B.NE	4d5d4c

(2622) 0x4d5a68 LDR	X17, [X25, #8]

(2622) 0x4d5a6c LDR	X16, [X23, #88]

(2622) 0x4d5a70 CMP	X16, X17

(2622) 0x4d5a74 B.NE	4d5d4c

(2622) 0x4d5a78 LDR	D31, [X19, #56]

(2622) 0x4d5a7c ADD	X24, X23, #152

(2622) 0x4d5a80 ADD	X20, X23, #160

(2622) 0x4d5a84 LDR	X26, [X24, #16]

(2622) 0x4d5a88 FADD	D3, D31, D15

(2622) 0x4d5a8c STR	D3, [X19, #56]

(2622) 0x4d5a90 CBZ	X26, 4d5c1c

(2622) 0x4d5a94 LDR	X5, [X23, #80]

(2622) 0x4d5a98 ORR	X19, XZR, X20

(2622) 0x4d5a9c HINT	#0

  (2624) 0x4d5aa0 ADD	X30, X26, #32

  (2624) 0x4d5aa4 LDR	X3, [X26, #32]

  (2624) 0x4d5aa8 CMP	X3, X5

  (2624) 0x4d5aac B.NE	4d5b2c

  (2624) 0x4d5ab0 LDR	X3, [X30, #8]

  (2624) 0x4d5ab4 LDR	X6, [X23, #88]

  (2624) 0x4d5ab8 CMP	X6, X3

  (2624) 0x4d5abc B.NE	4d5b30

  (2624) 0x4d5ac0 ORR	X19, XZR, X26

  (2624) 0x4d5ac4 LDR	X26, [X26, #16]

  (2624) 0x4d5ac8 CBNZ	X26, 4d5aa0

(2622) 0x4d5acc CMP	X20, X19

(2622) 0x4d5ad0 B.EQ	4d5c1c

(2622) 0x4d5ad4 LDR	X7, [X19, #32]

(2622) 0x4d5ad8 ADD	X25, X19, #32

(2622) 0x4d5adc CMP	X7, X5

(2622) 0x4d5ae0 B.NE	4d5eb4

(2622) 0x4d5ae4 LDR	X7, [X25, #8]

(2622) 0x4d5ae8 LDR	X5, [X23, #88]

(2622) 0x4d5aec CMP	X5, X7

(2622) 0x4d5af0 B.NE	4d5eb4

(2622) 0x4d5af4 LDR	X24, [X19, #56]

(2622) 0x4d5af8 LDR	X0, [X23, #72]

(2622) 0x4d5afc ADD	X12, X24, #1

(2622) 0x4d5b00 STR	X12, [X19, #56]

(2622) 0x4d5b04 CBZ	X0, 4d5b54

0x4d5b08 LDR	X27, [SP, #80]

0x4d5b0c ORR	X1, XZR, X23

0x4d5b10 LDP	X19, X20, [SP, #16]

0x4d5b14 LDP	X23, X24, [SP, #48]

0x4d5b18 LDP	X25, X26, [SP, #64]

0x4d5b1c LDP	X21, X22, [SP, #32]

0x4d5b20 LDR	D15, [SP, #88]

0x4d5b24 LDP	X29, X30, [SP], #96

0x4d5b28 B	4db520

  (2624) 0x4d5b2c ORR	X6, XZR, X5

  (2624) 0x4d5b30 CMP	X6, X3

  (2624) 0x4d5b34 B.LE	4d5ac0

  (2624) 0x4d5b38 LDR	X26, [X26, #24]

  (2624) 0x4d5b3c B	4d5ac8

  (2628) 0x4d5b40 ORR	X14, XZR, X16

  (2628) 0x4d5b44 CMP	X14, X13

  (2628) 0x4d5b48 B.LE	4d5a44

  (2628) 0x4d5b4c LDR	X15, [X15, #24]

  (2628) 0x4d5b50 B	4d5a4c

(2622) 0x4d5b54 LDR	X27, [SP, #80]

(2622) 0x4d5b58 LDP	X19, X20, [SP, #16]

(2622) 0x4d5b5c LDP	X23, X24, [SP, #48]

(2622) 0x4d5b60 LDP	X25, X26, [SP, #64]

(2622) 0x4d5b64 LDR	D15, [SP, #88]

(2622) 0x4d5b68 B	4d57f4

(2622) 0x4d5b6c BL	404140

(2622) 0x4d5b70 CMP	W0, #0

(2622) 0x4d5b74 ORR	W19, WZR, W22

(2622) 0x4d5b78 CCMP	W21, #0, #4, #0

(2622) 0x4d5b7c CSINC	W20, WZR, WZR, #0

(2622) 0x4d5b80 B	4d585c

(2622) 0x4d5b84 MOVZ	X0, #64

(2622) 0x4d5b88 BL	403dc0

(2622) 0x4d5b8c LDP	X6, X7, [X23, #80]

(2622) 0x4d5b90 ADD	X25, X0, #32

(2622) 0x4d5b94 ORR	X26, XZR, X0

(2622) 0x4d5b98 ORR	X27, XZR, X0

(2622) 0x4d5b9c LDR	X5, [X23, #96]

(2622) 0x4d5ba0 STP	X6, X7, [X0, #32]

(2622) 0x4d5ba4 LDR	X7, [X24, #40]

(2622) 0x4d5ba8 STP	X5, XZR, [X25, #16]

(2622) 0x4d5bac CBZ	X7, 4d5bd8

(2622) 0x4d5bb0 LDR	X2, [X23, #136]

(2622) 0x4d5bb4 LDR	X19, [X26, #32]

(2622) 0x4d5bb8 LDR	X9, [X2, #32]

(2622) 0x4d5bbc ADD	X8, X2, #32

(2622) 0x4d5bc0 CMP	X9, X19

(2622) 0x4d5bc4 B.NE	4d63ac

(2622) 0x4d5bc8 LDR	X10, [X8, #8]

(2622) 0x4d5bcc LDR	X0, [X25, #8]

(2622) 0x4d5bd0 CMP	X10, X0

(2622) 0x4d5bd4 B.NE	4d638c

(2622) 0x4d5bd8 LDR	X19, [X24, #16]

(2622) 0x4d5bdc CBZ	X19, 4d62b4

(2622) 0x4d5be0 LDR	X22, [X26, #32]

(2622) 0x4d5be4 ORR	X4, XZR, X22

  (2627) 0x4d5be8 LDR	X1, [X19, #32]

  (2627) 0x4d5bec ADD	X12, X19, #32

  (2627) 0x4d5bf0 CMP	X1, X22

  (2627) 0x4d5bf4 B.NE	4d5d30

  (2627) 0x4d5bf8 LDR	X13, [X12, #8]

  (2627) 0x4d5bfc LDR	X14, [X25, #8]

  (2627) 0x4d5c00 CMP	X13, X14

  (2627) 0x4d5c04 B.NE	4d5d38

  (2627) 0x4d5c08 LDR	X18, [X19, #24]

  (2627) 0x4d5c0c MOVZ	W15, #0

  (2627) 0x4d5c10 CBZ	X18, 4d5cb4

  (2627) 0x4d5c14 ORR	X19, XZR, X18

  (2627) 0x4d5c18 B	4d5be8

(2622) 0x4d5c1c MOVZ	X0, #64

(2622) 0x4d5c20 BL	403dc0

(2622) 0x4d5c24 LDP	X12, X13, [X23, #80]

(2622) 0x4d5c28 ADD	X25, X0, #32

(2622) 0x4d5c2c ORR	X26, XZR, X0

(2622) 0x4d5c30 ORR	X27, XZR, X0

(2622) 0x4d5c34 LDR	X14, [X24, #40]

(2622) 0x4d5c38 STP	X12, X13, [X0, #32]

(2622) 0x4d5c3c LDR	X13, [X23, #96]

(2622) 0x4d5c40 STP	X13, XZR, [X25, #16]

(2622) 0x4d5c44 CBZ	X14, 4d5c70

(2622) 0x4d5c48 LDR	X2, [X23, #184]

(2622) 0x4d5c4c LDR	X18, [X26, #32]

(2622) 0x4d5c50 LDR	X15, [X2, #32]

(2622) 0x4d5c54 ADD	X4, X2, #32

(2622) 0x4d5c58 CMP	X15, X18

(2622) 0x4d5c5c B.NE	4d6364

(2622) 0x4d5c60 LDR	X19, [X4, #8]

(2622) 0x4d5c64 LDR	X16, [X25, #8]

(2622) 0x4d5c68 CMP	X19, X16

(2622) 0x4d5c6c B.NE	4d6344

(2622) 0x4d5c70 LDR	X19, [X24, #16]

(2622) 0x4d5c74 CBZ	X19, 4d62cc

(2622) 0x4d5c78 LDR	X22, [X26, #32]

(2622) 0x4d5c7c ORR	X9, XZR, X22

  (2623) 0x4d5c80 LDR	X8, [X19, #32]

  (2623) 0x4d5c84 ADD	X2, X19, #32

  (2623) 0x4d5c88 CMP	X22, X8

  (2623) 0x4d5c8c B.NE	4d5d14

  (2623) 0x4d5c90 LDR	X1, [X2, #8]

  (2623) 0x4d5c94 LDR	X6, [X25, #8]

  (2623) 0x4d5c98 CMP	X1, X6

  (2623) 0x4d5c9c B.NE	4d5d1c

  (2623) 0x4d5ca0 LDR	X7, [X19, #24]

  (2623) 0x4d5ca4 MOVZ	W5, #0

  (2623) 0x4d5ca8 CBZ	X7, 4d5ce4

  (2623) 0x4d5cac ORR	X19, XZR, X7

  (2623) 0x4d5cb0 B	4d5c80

(2622) 0x4d5cb4 ORR	X2, XZR, X19

(2622) 0x4d5cb8 TBNZ	W15, #0, 4d6160

(2622) 0x4d5cbc CMP	X22, X1

(2622) 0x4d5cc0 B.NE	4d6280

(2622) 0x4d5cc4 LDR	X4, [X25, #8]

(2622) 0x4d5cc8 LDR	X1, [X19, #40]

(2622) 0x4d5ccc CMP	X1, X4

(2622) 0x4d5cd0 B.NE	4d6280

(2622) 0x4d5cd4 ORR	X0, XZR, X27

(2622) 0x4d5cd8 MOVZ	X1, #64

(2622) 0x4d5cdc BL	403da0

(2622) 0x4d5ce0 B	4d5a78

(2622) 0x4d5ce4 ORR	X2, XZR, X19

(2622) 0x4d5ce8 TBNZ	W5, #0, 4d6138

(2622) 0x4d5cec CMP	X22, X8

(2622) 0x4d5cf0 B.NE	4d6270

(2622) 0x4d5cf4 LDR	X9, [X25, #8]

(2622) 0x4d5cf8 LDR	X8, [X19, #40]

(2622) 0x4d5cfc CMP	X8, X9

(2622) 0x4d5d00 B.NE	4d6270

(2622) 0x4d5d04 ORR	X0, XZR, X27

(2622) 0x4d5d08 MOVZ	X1, #64

(2622) 0x4d5d0c BL	403da0

(2622) 0x4d5d10 B	4d5af4

  (2623) 0x4d5d14 ORR	X1, XZR, X8

  (2623) 0x4d5d18 ORR	X6, XZR, X22

  (2623) 0x4d5d1c CMP	X1, X6

  (2623) 0x4d5d20 B.LE	4d5ca0

  (2623) 0x4d5d24 LDR	X7, [X19, #16]

  (2623) 0x4d5d28 ORR	W5, WZR, W21

  (2623) 0x4d5d2c B	4d5ca8

  (2627) 0x4d5d30 ORR	X13, XZR, X1

  (2627) 0x4d5d34 ORR	X14, XZR, X22

  (2627) 0x4d5d38 CMP	X13, X14

  (2627) 0x4d5d3c B.LE	4d5c08

  (2627) 0x4d5d40 LDR	X18, [X19, #16]

  (2627) 0x4d5d44 ORR	W15, WZR, W21

  (2627) 0x4d5d48 B	4d5c10

(2622) 0x4d5d4c CMP	X16, X17

(2622) 0x4d5d50 B.GE	4d5a78

(2622) 0x4d5d54 MOVZ	X0, #64

(2622) 0x4d5d58 BL	403dc0

(2622) 0x4d5d5c LDP	X22, X18, [X23, #80]

(2622) 0x4d5d60 ADD	X26, X0, #32

(2622) 0x4d5d64 ORR	X27, XZR, X0

(2622) 0x4d5d68 LDR	X1, [X23, #96]

(2622) 0x4d5d6c STP	X22, X18, [X0, #32]

(2622) 0x4d5d70 STP	X1, XZR, [X26, #16]

(2622) 0x4d5d74 LDR	X2, [X19, #32]

(2622) 0x4d5d78 CMP	X22, X2

(2622) 0x4d5d7c B.NE	4d5e04

(2622) 0x4d5d80 LDR	X30, [X25, #8]

(2622) 0x4d5d84 LDR	X3, [X26, #8]

(2622) 0x4d5d88 CMP	X3, X30

(2622) 0x4d5d8c B.LT	4d5e08

(2622) 0x4d5d90 B.EQ	4d5cd4

(2622) 0x4d5d94 LDR	X4, [X23, #136]

(2622) 0x4d5d98 CMP	X19, X4

(2622) 0x4d5d9c B.EQ	4d6194

(2622) 0x4d5da0 ORR	X0, XZR, X19

(2622) 0x4d5da4 BL	404390

(2622) 0x4d5da8 LDR	X6, [X0, #32]

(2622) 0x4d5dac ADD	X5, X0, #32

(2622) 0x4d5db0 CMP	X6, X22

(2622) 0x4d5db4 B.NE	4d643c

(2622) 0x4d5db8 LDR	X7, [X5, #8]

(2622) 0x4d5dbc LDR	X8, [X26, #8]

(2622) 0x4d5dc0 CMP	X8, X7

(2622) 0x4d5dc4 B.NE	4d6424

(2622) 0x4d5dc8 LDR	X19, [X24, #16]

(2622) 0x4d5dcc CBZ	X19, 4d6454

  (2629) 0x4d5dd0 LDR	X15, [X19, #32]

  (2629) 0x4d5dd4 ADD	X10, X19, #32

  (2629) 0x4d5dd8 CMP	X15, X22

  (2629) 0x4d5ddc B.NE	4d6214

  (2629) 0x4d5de0 LDR	X0, [X10, #8]

  (2629) 0x4d5de4 LDR	X11, [X26, #8]

  (2629) 0x4d5de8 CMP	X0, X11

  (2629) 0x4d5dec B.NE	4d621c

  (2629) 0x4d5df0 LDR	X13, [X19, #24]

  (2629) 0x4d5df4 MOVZ	W12, #0

  (2629) 0x4d5df8 CBZ	X13, 4d61a0

  (2629) 0x4d5dfc ORR	X19, XZR, X13

  (2629) 0x4d5e00 B	4d5dd0

(2622) 0x4d5e04 B.GE	4d5d94

(2622) 0x4d5e08 LDR	X25, [X23, #128]

(2622) 0x4d5e0c CMP	X19, X25

(2622) 0x4d5e10 B.EQ	4d5e8c

(2622) 0x4d5e14 ORR	X0, XZR, X19

(2622) 0x4d5e18 BL	404000

(2622) 0x4d5e1c LDR	X18, [X0, #32]

(2622) 0x4d5e20 ORR	X2, XZR, X0

(2622) 0x4d5e24 CMP	X18, X22

(2622) 0x4d5e28 B.NE	4d5e78

(2622) 0x4d5e2c LDR	X16, [X26, #8]

(2622) 0x4d5e30 LDR	X18, [X0, #40]

(2622) 0x4d5e34 CMP	X18, X16

(2622) 0x4d5e38 B.NE	4d5e7c

(2622) 0x4d5e3c LDR	X19, [X24, #16]

(2622) 0x4d5e40 CBZ	X19, 4d6318

  (2630) 0x4d5e44 LDR	X3, [X19, #32]

  (2630) 0x4d5e48 ADD	X17, X19, #32

  (2630) 0x4d5e4c CMP	X3, X22

  (2630) 0x4d5e50 B.NE	4d60b4

  (2630) 0x4d5e54 LDR	X1, [X17, #8]

  (2630) 0x4d5e58 LDR	X2, [X26, #8]

  (2630) 0x4d5e5c CMP	X1, X2

  (2630) 0x4d5e60 B.NE	4d60bc

  (2630) 0x4d5e64 LDR	X4, [X19, #24]

  (2630) 0x4d5e68 MOVZ	W30, #0

  (2630) 0x4d5e6c CBZ	X4, 4d60d0

  (2630) 0x4d5e70 ORR	X19, XZR, X4

  (2630) 0x4d5e74 B	4d5e44

(2622) 0x4d5e78 ORR	X16, XZR, X22

(2622) 0x4d5e7c CMP	X18, X16

(2622) 0x4d5e80 B.GE	4d5e3c

(2622) 0x4d5e84 LDR	X22, [X2, #24]

(2622) 0x4d5e88 CBZ	X22, 4d60f8

(2622) 0x4d5e8c ORR	X2, XZR, X19

(2622) 0x4d5e90 ORR	W0, WZR, W21

(2622) 0x4d5e94 ORR	X19, XZR, X27

(2622) 0x4d5e98 ORR	X3, XZR, X20

(2622) 0x4d5e9c ORR	X1, XZR, X19

(2622) 0x4d5ea0 BL	404420

(2622) 0x4d5ea4 LDR	X20, [X24, #40]

(2622) 0x4d5ea8 ADD	X2, X20, #1

(2622) 0x4d5eac STR	X2, [X24, #40]

(2622) 0x4d5eb0 B	4d5a78

(2622) 0x4d5eb4 CMP	X5, X7

(2622) 0x4d5eb8 B.GE	4d5af4

(2622) 0x4d5ebc MOVZ	X0, #64

(2622) 0x4d5ec0 BL	403dc0

(2622) 0x4d5ec4 LDP	X22, X8, [X23, #80]

(2622) 0x4d5ec8 ADD	X26, X0, #32

(2622) 0x4d5ecc ORR	X27, XZR, X0

(2622) 0x4d5ed0 LDR	X9, [X23, #96]

(2622) 0x4d5ed4 STP	X22, X8, [X0, #32]

(2622) 0x4d5ed8 STP	X9, XZR, [X26, #16]

(2622) 0x4d5edc LDR	X10, [X19, #32]

(2622) 0x4d5ee0 CMP	X22, X10

(2622) 0x4d5ee4 B.NE	4d5f74

(2622) 0x4d5ee8 LDR	X0, [X25, #8]

(2622) 0x4d5eec LDR	X11, [X26, #8]

(2622) 0x4d5ef0 CMP	X11, X0

(2622) 0x4d5ef4 B.LT	4d5f78

(2622) 0x4d5ef8 B.EQ	4d5d04

(2622) 0x4d5efc LDR	X12, [X23, #184]

(2622) 0x4d5f00 CMP	X12, X19

(2622) 0x4d5f04 B.EQ	4d6188

(2622) 0x4d5f08 ORR	X0, XZR, X19

(2622) 0x4d5f0c BL	404390

(2622) 0x4d5f10 LDR	X13, [X0, #32]

(2622) 0x4d5f14 ORR	X2, XZR, X0

(2622) 0x4d5f18 ADD	X4, X0, #32

(2622) 0x4d5f1c CMP	X13, X22

(2622) 0x4d5f20 B.NE	4d6400

(2622) 0x4d5f24 LDR	X14, [X4, #8]

(2622) 0x4d5f28 LDR	X15, [X26, #8]

(2622) 0x4d5f2c CMP	X15, X14

(2622) 0x4d5f30 B.NE	4d63e8

(2622) 0x4d5f34 LDR	X19, [X24, #16]

(2622) 0x4d5f38 CBZ	X19, 4d63d4

(2622) 0x4d5f3c HINT	#0

  (2625) 0x4d5f40 LDR	X3, [X19, #32]

  (2625) 0x4d5f44 ADD	X16, X19, #32

  (2625) 0x4d5f48 CMP	X3, X22

  (2625) 0x4d5f4c B.NE	4d61f8

  (2625) 0x4d5f50 LDR	X4, [X16, #8]

  (2625) 0x4d5f54 LDR	X17, [X26, #8]

  (2625) 0x4d5f58 CMP	X4, X17

  (2625) 0x4d5f5c B.NE	4d6200

  (2625) 0x4d5f60 LDR	X2, [X19, #24]

  (2625) 0x4d5f64 MOVZ	W30, #0

  (2625) 0x4d5f68 CBZ	X2, 4d61cc

  (2625) 0x4d5f6c ORR	X19, XZR, X2

  (2625) 0x4d5f70 B	4d5f40

(2622) 0x4d5f74 B.GE	4d5efc

(2622) 0x4d5f78 LDR	X25, [X23, #176]

(2622) 0x4d5f7c CMP	X25, X19

(2622) 0x4d5f80 B.EQ	4d6008

(2622) 0x4d5f84 ORR	X0, XZR, X19

(2622) 0x4d5f88 BL	404000

(2622) 0x4d5f8c LDR	X6, [X0, #32]

(2622) 0x4d5f90 ORR	X2, XZR, X0

(2622) 0x4d5f94 CMP	X6, X22

(2622) 0x4d5f98 B.NE	4d5ff4

(2622) 0x4d5f9c LDR	X5, [X26, #8]

(2622) 0x4d5fa0 LDR	X6, [X0, #40]

(2622) 0x4d5fa4 CMP	X6, X5

(2622) 0x4d5fa8 B.NE	4d5ff8

(2622) 0x4d5fac LDR	X19, [X24, #16]

(2622) 0x4d5fb0 CBZ	X19, 4d6308

(2622) 0x4d5fb4 HINT	#0

(2622) 0x4d5fb8 HINT	#0

(2622) 0x4d5fbc HINT	#0

  (2626) 0x4d5fc0 LDR	X11, [X19, #32]

  (2626) 0x4d5fc4 ADD	X7, X19, #32

  (2626) 0x4d5fc8 CMP	X11, X22

  (2626) 0x4d5fcc B.NE	4d6030

  (2626) 0x4d5fd0 LDR	X8, [X7, #8]

  (2626) 0x4d5fd4 LDR	X9, [X26, #8]

  (2626) 0x4d5fd8 CMP	X8, X9

  (2626) 0x4d5fdc B.NE	4d6038

  (2626) 0x4d5fe0 LDR	X0, [X19, #24]

  (2626) 0x4d5fe4 MOVZ	W10, #0

  (2626) 0x4d5fe8 CBZ	X0, 4d604c

  (2626) 0x4d5fec ORR	X19, XZR, X0

  (2626) 0x4d5ff0 B	4d5fc0

(2622) 0x4d5ff4 ORR	X5, XZR, X22

(2622) 0x4d5ff8 CMP	X6, X5

(2622) 0x4d5ffc B.GE	4d5fac

(2622) 0x4d6000 LDR	X22, [X2, #24]

(2622) 0x4d6004 CBZ	X22, 4d6074

(2622) 0x4d6008 ORR	X2, XZR, X19

(2622) 0x4d600c ORR	X19, XZR, X27

(2622) 0x4d6010 ORR	X3, XZR, X20

(2622) 0x4d6014 ORR	W0, WZR, W21

(2622) 0x4d6018 ORR	X1, XZR, X19

(2622) 0x4d601c BL	404420

(2622) 0x4d6020 LDR	X20, [X24, #40]

(2622) 0x4d6024 ADD	X11, X20, #1

(2622) 0x4d6028 STR	X11, [X24, #40]

(2622) 0x4d602c B	4d5af4

  (2626) 0x4d6030 ORR	X8, XZR, X11

  (2626) 0x4d6034 ORR	X9, XZR, X22

  (2626) 0x4d6038 CMP	X8, X9

  (2626) 0x4d603c B.LE	4d5fe0

  (2626) 0x4d6040 LDR	X0, [X19, #16]

  (2626) 0x4d6044 ORR	W10, WZR, W21

  (2626) 0x4d6048 B	4d5fe8

(2622) 0x4d604c ORR	X2, XZR, X19

(2622) 0x4d6050 TBNZ	W10, #0, 4d6250

(2622) 0x4d6054 CMP	X22, X11

(2622) 0x4d6058 B.NE	4d606c

(2622) 0x4d605c LDR	X22, [X26, #8]

(2622) 0x4d6060 LDR	X11, [X19, #40]

(2622) 0x4d6064 CMP	X11, X22

(2622) 0x4d6068 B.EQ	4d5d04

(2622) 0x4d606c CMP	X11, X22

(2622) 0x4d6070 B.GE	4d5d04

(2622) 0x4d6074 ORR	X19, XZR, X27

(2622) 0x4d6078 CMP	X20, X2

(2622) 0x4d607c B.EQ	4d6010

(2622) 0x4d6080 LDR	X10, [X2, #32]

(2622) 0x4d6084 LDR	X0, [X19, #32]

(2622) 0x4d6088 CMP	X10, X0

(2622) 0x4d608c B.NE	4d60a8

(2622) 0x4d6090 ADD	X4, X2, #32

(2622) 0x4d6094 LDR	X10, [X4, #8]

(2622) 0x4d6098 MOVZ	W21, #0

(2622) 0x4d609c LDR	X0, [X19, #40]

(2622) 0x4d60a0 CMP	X10, X0

(2622) 0x4d60a4 B.EQ	4d6010

(2622) 0x4d60a8 CMP	X0, X10

(2622) 0x4d60ac CSINC	W21, WZR, WZR, #10

(2622) 0x4d60b0 B	4d6010

  (2630) 0x4d60b4 ORR	X1, XZR, X3

  (2630) 0x4d60b8 ORR	X2, XZR, X22

  (2630) 0x4d60bc CMP	X1, X2

  (2630) 0x4d60c0 B.LE	4d5e64

  (2630) 0x4d60c4 LDR	X4, [X19, #16]

  (2630) 0x4d60c8 ORR	W30, WZR, W21

  (2630) 0x4d60cc B	4d5e6c

(2622) 0x4d60d0 ORR	X2, XZR, X19

(2622) 0x4d60d4 TBNZ	W30, #0, 4d6230

(2622) 0x4d60d8 CMP	X22, X3

(2622) 0x4d60dc B.NE	4d60f0

(2622) 0x4d60e0 LDR	X22, [X26, #8]

(2622) 0x4d60e4 LDR	X3, [X19, #40]

(2622) 0x4d60e8 CMP	X3, X22

(2622) 0x4d60ec B.EQ	4d5cd4

(2622) 0x4d60f0 CMP	X3, X22

(2622) 0x4d60f4 B.GE	4d5cd4

(2622) 0x4d60f8 ORR	X19, XZR, X27

(2622) 0x4d60fc ORR	W0, WZR, W21

(2622) 0x4d6100 CMP	X20, X2

(2622) 0x4d6104 B.EQ	4d5e98

(2622) 0x4d6108 LDR	X27, [X2, #32]

(2622) 0x4d610c LDR	X17, [X19, #32]

(2622) 0x4d6110 CMP	X17, X27

(2622) 0x4d6114 B.NE	4d612c

(2622) 0x4d6118 LDR	X27, [X2, #40]

(2622) 0x4d611c MOVZ	W0, #0

(2622) 0x4d6120 LDR	X17, [X19, #40]

(2622) 0x4d6124 CMP	X17, X27

(2622) 0x4d6128 B.EQ	4d5e98

(2622) 0x4d612c CMP	X17, X27

(2622) 0x4d6130 CSINC	W0, WZR, WZR, #10

(2622) 0x4d6134 B	4d5e98

(2622) 0x4d6138 LDR	X3, [X24, #24]

(2622) 0x4d613c CMP	X3, X19

(2622) 0x4d6140 B.EQ	4d6278

(2622) 0x4d6144 ORR	X0, XZR, X19

(2622) 0x4d6148 BL	404000

(2622) 0x4d614c LDR	X8, [X0, #32]

(2622) 0x4d6150 ORR	X2, XZR, X19

(2622) 0x4d6154 ORR	X9, XZR, X22

(2622) 0x4d6158 ORR	X19, XZR, X0

(2622) 0x4d615c B	4d5cec

(2622) 0x4d6160 LDR	X16, [X24, #24]

(2622) 0x4d6164 CMP	X16, X19

(2622) 0x4d6168 B.EQ	4d6288

(2622) 0x4d616c ORR	X0, XZR, X19

(2622) 0x4d6170 BL	404000

(2622) 0x4d6174 LDR	X1, [X0, #32]

(2622) 0x4d6178 ORR	X2, XZR, X19

(2622) 0x4d617c ORR	X4, XZR, X22

(2622) 0x4d6180 ORR	X19, XZR, X0

(2622) 0x4d6184 B	4d5cbc

(2622) 0x4d6188 ORR	X2, XZR, X19

(2622) 0x4d618c ORR	X19, XZR, X27

(2622) 0x4d6190 B	4d6080

(2622) 0x4d6194 ORR	X2, XZR, X19

(2622) 0x4d6198 ORR	X19, XZR, X27

(2622) 0x4d619c B	4d6108

(2622) 0x4d61a0 ORR	X2, XZR, X19

(2622) 0x4d61a4 TBNZ	W12, #0, 4d6290

(2622) 0x4d61a8 CMP	X22, X15

(2622) 0x4d61ac B.NE	4d61c0

(2622) 0x4d61b0 LDR	X22, [X26, #8]

(2622) 0x4d61b4 LDR	X15, [X19, #40]

(2622) 0x4d61b8 CMP	X15, X22

(2622) 0x4d61bc B.EQ	4d5cd4

(2622) 0x4d61c0 CMP	X15, X22

(2622) 0x4d61c4 B.LT	4d60f8

(2622) 0x4d61c8 B	4d5cd4

(2622) 0x4d61cc ORR	X2, XZR, X19

(2622) 0x4d61d0 TBNZ	W30, #0, 4d62e4

(2622) 0x4d61d4 CMP	X22, X3

(2622) 0x4d61d8 B.NE	4d61ec

(2622) 0x4d61dc LDR	X22, [X26, #8]

(2622) 0x4d61e0 LDR	X3, [X19, #40]

(2622) 0x4d61e4 CMP	X3, X22

(2622) 0x4d61e8 B.EQ	4d5d04

(2622) 0x4d61ec CMP	X3, X22

(2622) 0x4d61f0 B.LT	4d6074

(2622) 0x4d61f4 B	4d5d04

  (2625) 0x4d61f8 ORR	X4, XZR, X3

  (2625) 0x4d61fc ORR	X17, XZR, X22

  (2625) 0x4d6200 CMP	X4, X17

  (2625) 0x4d6204 B.LE	4d5f60

  (2625) 0x4d6208 LDR	X2, [X19, #16]

  (2625) 0x4d620c ORR	W30, WZR, W21

  (2625) 0x4d6210 B	4d5f68

  (2629) 0x4d6214 ORR	X0, XZR, X15

  (2629) 0x4d6218 ORR	X11, XZR, X22

  (2629) 0x4d621c CMP	X0, X11

  (2629) 0x4d6220 B.LE	4d5df0

  (2629) 0x4d6224 LDR	X13, [X19, #16]

  (2629) 0x4d6228 ORR	W12, WZR, W21

  (2629) 0x4d622c B	4d5df8

(2622) 0x4d6230 CMP	X25, X19

(2622) 0x4d6234 B.EQ	4d60f8

(2622) 0x4d6238 ORR	X0, XZR, X19

(2622) 0x4d623c BL	404000

(2622) 0x4d6240 LDR	X3, [X0, #32]

(2622) 0x4d6244 ORR	X2, XZR, X19

(2622) 0x4d6248 ORR	X19, XZR, X0

(2622) 0x4d624c B	4d60d8

(2622) 0x4d6250 CMP	X25, X19

(2622) 0x4d6254 B.EQ	4d6074

(2622) 0x4d6258 ORR	X0, XZR, X19

(2622) 0x4d625c BL	404000

(2622) 0x4d6260 LDR	X11, [X0, #32]

(2622) 0x4d6264 ORR	X2, XZR, X19

(2622) 0x4d6268 ORR	X19, XZR, X0

(2622) 0x4d626c B	4d6054

(2622) 0x4d6270 CMP	X8, X9

(2622) 0x4d6274 B.GE	4d5d04

(2622) 0x4d6278 ORR	X19, XZR, X26

(2622) 0x4d627c B	4d6078

(2622) 0x4d6280 CMP	X1, X4

(2622) 0x4d6284 B.GE	4d5cd4

(2622) 0x4d6288 ORR	X19, XZR, X26

(2622) 0x4d628c B	4d60fc

(2622) 0x4d6290 LDR	X14, [X24, #24]

(2622) 0x4d6294 CMP	X19, X14

(2622) 0x4d6298 B.EQ	4d60f8

(2622) 0x4d629c ORR	X0, XZR, X19

(2622) 0x4d62a0 BL	404000

(2622) 0x4d62a4 LDR	X15, [X0, #32]

(2622) 0x4d62a8 ORR	X2, XZR, X19

(2622) 0x4d62ac ORR	X19, XZR, X0

(2622) 0x4d62b0 B	4d61a8

(2622) 0x4d62b4 LDR	X11, [X24, #24]

(2622) 0x4d62b8 CMP	X20, X11

(2622) 0x4d62bc B.EQ	4d6328

(2622) 0x4d62c0 LDR	X22, [X26, #32]

(2622) 0x4d62c4 ORR	X19, XZR, X20

(2622) 0x4d62c8 B	4d616c

(2622) 0x4d62cc LDR	X30, [X24, #24]

(2622) 0x4d62d0 CMP	X20, X30

(2622) 0x4d62d4 B.EQ	4d6338

(2622) 0x4d62d8 LDR	X22, [X26, #32]

(2622) 0x4d62dc ORR	X19, XZR, X20

(2622) 0x4d62e0 B	4d6144

(2622) 0x4d62e4 LDR	X1, [X24, #24]

(2622) 0x4d62e8 CMP	X1, X19

(2622) 0x4d62ec B.EQ	4d6074

(2622) 0x4d62f0 ORR	X0, XZR, X19

(2622) 0x4d62f4 BL	404000

(2622) 0x4d62f8 LDR	X3, [X0, #32]

(2622) 0x4d62fc ORR	X2, XZR, X19

(2622) 0x4d6300 ORR	X19, XZR, X0

(2622) 0x4d6304 B	4d61d4

(2622) 0x4d6308 CMP	X20, X25

(2622) 0x4d630c B.EQ	4d6418

(2622) 0x4d6310 ORR	X19, XZR, X20

(2622) 0x4d6314 B	4d6258

(2622) 0x4d6318 CMP	X20, X25

(2622) 0x4d631c B.EQ	4d6468

(2622) 0x4d6320 ORR	X19, XZR, X20

(2622) 0x4d6324 B	4d6238

(2622) 0x4d6328 ORR	X19, XZR, X26

(2622) 0x4d632c ORR	X2, XZR, X20

(2622) 0x4d6330 ORR	W0, WZR, W21

(2622) 0x4d6334 B	4d5e98

(2622) 0x4d6338 ORR	X19, XZR, X26

(2622) 0x4d633c ORR	X2, XZR, X20

(2622) 0x4d6340 B	4d6010

(2622) 0x4d6344 B.GE	4d5c70

(2622) 0x4d6348 MOVZ	X17, #0

(2622) 0x4d634c ORR	X19, XZR, X26

(2622) 0x4d6350 CMP	X17, #0

(2622) 0x4d6354 CCMP	X20, X2, #4, #0

(2622) 0x4d6358 CSINC	W21, WZR, WZR, #1

(2622) 0x4d635c B.EQ	4d6010

(2622) 0x4d6360 B	4d6094

(2622) 0x4d6364 B.GE	4d5c70

(2622) 0x4d6368 MOVZ	X21, #0

(2622) 0x4d636c ORR	X19, XZR, X26

(2622) 0x4d6370 CMP	X21, #0

(2622) 0x4d6374 CCMP	X20, X2, #4, #0

(2622) 0x4d6378 CSINC	W21, WZR, WZR, #1

(2622) 0x4d637c B.EQ	4d6010

(2622) 0x4d6380 LDR	X10, [X2, #32]

(2622) 0x4d6384 LDR	X0, [X19, #32]

(2622) 0x4d6388 B	4d60a8

(2622) 0x4d638c B.GE	4d5bd8

(2622) 0x4d6390 MOVZ	X0, #0

(2622) 0x4d6394 ORR	X19, XZR, X26

(2622) 0x4d6398 CMP	X0, #0

(2622) 0x4d639c CCMP	X20, X2, #4, #0

(2622) 0x4d63a0 CSINC	W0, WZR, WZR, #1

(2622) 0x4d63a4 B.EQ	4d5e98

(2622) 0x4d63a8 B	4d6118

(2622) 0x4d63ac B.GE	4d5bd8

(2622) 0x4d63b0 MOVZ	X0, #0

(2622) 0x4d63b4 ORR	X19, XZR, X26

(2622) 0x4d63b8 CMP	X0, #0

(2622) 0x4d63bc CCMP	X20, X2, #4, #0

(2622) 0x4d63c0 CSINC	W0, WZR, WZR, #1

(2622) 0x4d63c4 B.EQ	4d5e98

(2622) 0x4d63c8 LDR	X27, [X2, #32]

(2622) 0x4d63cc LDR	X17, [X19, #32]

(2622) 0x4d63d0 B	4d612c

(2622) 0x4d63d4 LDR	X19, [X24, #24]

(2622) 0x4d63d8 CMP	X20, X19

(2622) 0x4d63dc B.EQ	4d6418

(2622) 0x4d63e0 ORR	X19, XZR, X20

(2622) 0x4d63e4 B	4d62f0

(2622) 0x4d63e8 B.GE	4d5f34

(2622) 0x4d63ec LDR	X18, [X19, #24]

(2622) 0x4d63f0 CBZ	X18, 4d6188

(2622) 0x4d63f4 ORR	X19, XZR, X27

(2622) 0x4d63f8 ORR	X17, XZR, X0

(2622) 0x4d63fc B	4d6350

(2622) 0x4d6400 B.LE	4d5f34

(2622) 0x4d6404 LDR	X21, [X19, #24]

(2622) 0x4d6408 CBZ	X21, 4d6188

(2622) 0x4d640c ORR	X19, XZR, X27

(2622) 0x4d6410 ORR	X21, XZR, X0

(2622) 0x4d6414 B	4d6370

(2622) 0x4d6418 ORR	X19, XZR, X27

(2622) 0x4d641c ORR	X2, XZR, X20

(2622) 0x4d6420 B	4d6010

(2622) 0x4d6424 B.GE	4d5dc8

(2622) 0x4d6428 LDR	X9, [X19, #24]

(2622) 0x4d642c CBZ	X9, 4d6194

(2622) 0x4d6430 ORR	X19, XZR, X27

(2622) 0x4d6434 ORR	X2, XZR, X0

(2622) 0x4d6438 B	4d6398

(2622) 0x4d643c B.LE	4d5dc8

(2622) 0x4d6440 LDR	X25, [X19, #24]

(2622) 0x4d6444 CBZ	X25, 4d6194

(2622) 0x4d6448 ORR	X19, XZR, X27

(2622) 0x4d644c ORR	X2, XZR, X0

(2622) 0x4d6450 B	4d63b8

(2622) 0x4d6454 LDR	X19, [X24, #24]

(2622) 0x4d6458 CMP	X20, X19

(2622) 0x4d645c B.EQ	4d6468

(2622) 0x4d6460 ORR	X19, XZR, X20

(2622) 0x4d6464 B	4d629c

(2622) 0x4d6468 ORR	X19, XZR, X27

(2622) 0x4d646c ORR	X2, XZR, X20

(2622) 0x4d6470 ORR	W0, WZR, W21

(2622) 0x4d6474 B	4d5e98

0x4d6478 HINT	#0

0x4d647c HINT	#0

Coverage (%)	Name	Source Location	Module
►11.00+	qmcplusplus::SoaDistanceTableA[...]	NewTimer.h:249	exec
○	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►6.43+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.75+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:101	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.25+	miniqmcreference::einspline_sp[...]	einspline_spo_ref.hpp:219	exec
○	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►5.08+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:233	exec
○	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.91+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:101	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.91+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableAAOMPTarget.h:287	exec
○	qmcplusplus::ParticleSet::make[...]	stl_vector.h:993	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.74+	main._omp_fn.1	miniqmc.cpp:452	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.40+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►4.23+	qmcplusplus::ParticleSet::acce[...]	NewTimer.h:249	exec
○	main._omp_fn.1	miniqmc.cpp:453	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.38+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:90	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:183	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►3.21+	qmcplusplus::ParticleSet::make[...]	NewTimer.h:249	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.88+	miniqmcreference::einspline_sp[...]	NewTimer.h:249	exec
○	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:248	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.88+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►2.20+	qmcplusplus::ParticleSet::upda[...]	NewTimer.h:249	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.86+	miniqmcreference::einspline_sp[...]	NewTimer.h:249	exec
○	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:248	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.52+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:138	exec
○	qmcplusplus::WaveFunction::acc[...]	WaveFunction.cpp:223	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.18+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:138	exec
○	qmcplusplus::WaveFunction::acc[...]	WaveFunction.cpp:225	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.02+	qmcplusplus::SoaDistanceTableA[...]	SoaDistanceTableABOMPTarget.h:368	exec
○	qmcplusplus::ParticleSet::make[...]	stl_vector.h:993	exec
○	main._omp_fn.1	miniqmc.cpp:440	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►1.02+	qmcplusplus::WaveFunction::acc[...]	WaveFunction.cpp:225	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_0

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h:151,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-124
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/tuple:2887-2888
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_tree.h:269,283,298-299,631,733,748,778,786,1636,1947-1949,2109-2125,2217-2230,2242-2246,2373-2383,2459
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_map.h:511
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/chrono.h:214,716

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 0.67 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 75% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.33 to 2.73 cycles (1.22x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 97 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.75
Overall L1	3.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

30% of peak load performance is reached (29.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4d57e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDRB W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (6.3%)
TBNZ W21, #0, 4d5800 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4db520 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.02% of application time for run gcc_0

Source file and lines	NewTimer.cpp:84-120
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h:151,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:119-124
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/tuple:2887-2888
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.cpp:84-86,98-112,120
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_tree.h:269,283,298-299,631,733,748,778,786,1636,1947-1949,2109-2125,2217-2230,2242-2246,2373-2383,2459
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_map.h:511
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/chrono.h:214,716

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.33 to 0.67 cycles (5.00x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 97 bytes. The binary function is storing 32 bytes.

General properties

nb instructions	16
loop length	64
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

1.75 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00
cycles	1.00	1.00	0.50	0.50	0.50	0.50	0.50	0.50	0.00	0.00	0.00	0.00	3.33	3.33	3.33	1.00	1.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	1.75
Overall L1	3.33

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.33 cycles. At this rate:

30% of peak load performance is reached (29.10 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
20% of peak store performance is reached (9.60 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4d57e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #928]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDRB W21, [X0, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (6.3%)
TBNZ W21, #0, 4d5800 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv+0x20>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X27, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDR D15, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X29, X30, [SP], #96	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 4db520 <_ZN11qmcplusplus12TimerManagerINS_9TimerTypeINSt6chrono3_V212system_clockEEEE9pop_timerEPS5_>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::TimerType::stop()–	0.02	0.03
▼Loop 2622 - stl_tree.h:269-2459 - exec–	0.00	0.01
○Loop 2628 - stl_tree.h:786-1949 - exec	0.00	0.29
○Loop 2624 - stl_tree.h:786-1949 - exec	0.00	0.10
○Loop 2627 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2629 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2625 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2631 - NewTimer.cpp:99-100 - exec	0.00	0.00
○Loop 2630 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2623 - stl_tree.h:778-2115 - exec	0.00	0.00
○Loop 2626 - stl_tree.h:778-2115 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code