OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::ParticleAttrib<double, std::allocator<double> >&, bool)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalua ...	Module: exec	Source: DiracDeterminantRef.cpp:152-181 [...]	Coverage (incl. loops): 0.62% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h: 104 - 172

--------------------------------------------------------------------------------

104:       ~__new_allocator() _GLIBCXX_USE_NOEXCEPT { }

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 156

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h: 110 - 131

--------------------------------------------------------------------------------

110:     for (unsigned d = 0; d < D; ++d)

[...]

129:     Type_t res = lhs[0] * rhs[0];

130:     for (unsigned d = 1; d < D; ++d)

131:       res += lhs[d] * rhs[d];

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 56 - 248

--------------------------------------------------------------------------------

56:   explicit inline Vector(T* ref, size_t n) : nLocal(n), X(ref) {}

[...]

144:   virtual ~Vector() { free(); }

[...]

210:     if (nAllocated)

[...]

221:   inline Type_t& operator[](size_t i)

222:   {

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 152 - 181

--------------------------------------------------------------------------------

152: void DiracDeterminantRef<DU_TYPE>::evaluateGL(ParticleSet& P,

153:                                               ParticleSet::ParticleGradient& G,

154:                                               ParticleSet::ParticleLaplacian& L,

155:                                               bool fromscratch)

156: {

157:   if (UpdateMode == ORB_PBYP_RATIO)

158:   { //need to compute dpsiM and d2psiM. Do not touch psiM!

159:     SPOVGLTimer->start();

160:     Phi->evaluate_notranspose(P, FirstIndex, LastIndex, psiM_temp, dpsiM, d2psiM);

161:     SPOVGLTimer->stop();

162:   }

163:

164:   if (NumPtcls == 1)

165:   {

166:     ValueType y = psiM(0, 0);

167:     GradType rv = y * dpsiM(0, 0);

168:     G[FirstIndex] += rv;

169:     L[FirstIndex] += y * d2psiM(0, 0) - dot(rv, rv);

170:   }

171:   else

172:   {

173:     for (size_t i = 0, iat = FirstIndex; i < NumPtcls; ++i, ++iat)

174:     {

175:       mValueType dot_temp = simd::dot(psiM[i], d2psiM[i], NumOrbitals);

176:       mGradType rv        = simd::dot(psiM[i], dpsiM[i], NumOrbitals);

177:       G[iat] += rv;

178:       L[iat] += dot_temp - dot(rv, rv);

179:     }

180:   }

181: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h: 106 - 111

--------------------------------------------------------------------------------

106:     for (int iat = first, i = 0; iat < last; ++iat, ++i)

107:     {

108:       ValueVector_t v(logdet[i], OrbitalSetSize);

109:       GradVector_t g(dlogdet[i], OrbitalSetSize);

110:       ValueVector_t l(d2logdet[i], OrbitalSetSize);

111:       evaluate(P, iat, v, g, l);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 217 - 217

--------------------------------------------------------------------------------

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

0x4739c0 STP	X29, X30, [SP, #752]!

0x4739c4 ADD	X29, SP, #0

0x4739c8 ORR	X7, XZR, X0

0x4739cc LDR	W0, [X0, #12]

0x4739d0 STR	X1, [SP, #96]

0x4739d4 STP	X2, X3, [SP, #120]

0x4739d8 CBZ	W0, 473f88

(1350) 0x4739dc LDR	W14, [X7, #1156]

(1350) 0x4739e0 LDR	W30, [X7, #1144]

(1350) 0x4739e4 CMP	W14, #1

(1350) 0x4739e8 B.EQ	473f00

0x4739ec STP	X19, X20, [SP, #16]

0x4739f0 SBFM	X19, X14, #0, #31

0x4739f4 CBZ	W14, 47417c

0x4739f8 MOVZ	X12, #0

0x4739fc MOVZ	X11, #0

0x473a00 PTRUE	P6.B, ALL

0x473a04 LDR	X20, [SP, #120]

0x473a08 MOVZ	X3, #0

0x473a0c CNTD	X10, ALL

0x473a10 STP	X21, X22, [SP, #32]

0x473a14 MOVZ	W22, #64

0x473a18 LDR	X1, [SP, #128]

0x473a1c STP	X23, X24, [SP, #48]

0x473a20 MOVZ	W23, #96

0x473a24 STP	X25, X26, [SP, #64]

0x473a28 STP	X27, X28, [SP, #80]

0x473a2c MOVZ	W27, #24

0x473a30 LDR	X28, [X20, #24]

0x473a34 LDR	X16, [X7, #216]

0x473a38 LDR	X21, [X7, #256]

0x473a3c SMADDL	X0, W30, W27, X28

0x473a40 LDR	X15, [X7, #344]

0x473a44 UBFM	X18, X16, #61, #60

0x473a48 LDR	X5, [X7, #384]

0x473a4c ORR	X4, XZR, X21

0x473a50 LDR	W6, [X7, #1152]

0x473a54 UBFM	X17, X15, #61, #60

0x473a58 LDR	X2, [X1, #24]

0x473a5c ADD	X13, X2, W30,SXTW #3

0x473a60 ORR	X8, XZR, X5

0x473a64 AND	W9, W6, #1886

0x473a68 UBFM	W30, W6, #3, #31

0x473a6c SUB	W14, W6, #1

0x473a70 UBFM	W25, W6, #2, #31

0x473a74 AND	W26, W6, #64

0x473a78 AND	W24, W6, #1821

0x473a7c STR	W30, [SP, #96]

0x473a80 STR	W9, [SP, #120]

    (1353) 0x473a84 CMP	W6, #0

    (1353) 0x473a88 B.LE	473eb8

    (1353) 0x473a8c CMP	W14, #6

    (1353) 0x473a90 B.LS	473ee4

    (1353) 0x473a94 LDR	W28, [SP, #96]

    (1353) 0x473a98 MOVI	V23.2D, #0

    (1353) 0x473a9c ORR	X2, XZR, X8

    (1353) 0x473aa0 ORR	X1, XZR, X4

    (1353) 0x473aa4 ORR	V22.16B, V23.16B, V23.16B

    (1353) 0x473aa8 ORR	V21.16B, V23.16B, V23.16B

    (1353) 0x473aac UMADDL	X30, W28, W22, X4

    (1353) 0x473ab0 ORR	V0.16B, V23.16B, V23.16B

    (1353) 0x473ab4 SUB	X27, X30, X4

    (1353) 0x473ab8 SUB	X9, X27, #64

    (1353) 0x473abc UBFM	X20, X9, #6, #63

    (1353) 0x473ac0 ADD	X28, X20, #1

    (1353) 0x473ac4 ANDS	X27, X28, #4160

    (1353) 0x473ac8 B.EQ	473b54

    (1353) 0x473acc CMP	X27, #1

    (1353) 0x473ad0 B.EQ	473b28

    (1353) 0x473ad4 CMP	X27, #2

    (1353) 0x473ad8 B.EQ	473b04

    (1353) 0x473adc LDP	Q19, Q18, [X4, #16]

    (1353) 0x473ae0 LDP	Q16, Q7, [X8, #16]

    (1353) 0x473ae4 LDR	Q17, [X4, #48]

    (1353) 0x473ae8 LDR	Q6, [X8, #48]

    (1353) 0x473aec LDR	Q5, [X1], #64

    (1353) 0x473af0 LDR	Q4, [X2], #64

    (1353) 0x473af4 FMLA	V21.2D, V19.2D, V16.2D

    (1353) 0x473af8 FMLA	V22.2D, V18.2D, V7.2D

    (1353) 0x473afc FMLA	V0.2D, V5.2D, V4.2D

    (1353) 0x473b00 FMLA	V23.2D, V17.2D, V6.2D

    (1353) 0x473b04 LDP	Q24, Q20, [X2, #16]

    (1353) 0x473b08 LDP	Q2, Q1, [X1, #32]

    (1353) 0x473b0c LDP	Q25, Q3, [X1], #64

    (1353) 0x473b10 LDR	Q31, [X2, #48]

    (1353) 0x473b14 LDR	Q30, [X2], #64

    (1353) 0x473b18 FMLA	V22.2D, V2.2D, V20.2D

    (1353) 0x473b1c FMLA	V21.2D, V3.2D, V24.2D

    (1353) 0x473b20 FMLA	V23.2D, V1.2D, V31.2D

    (1353) 0x473b24 FMLA	V0.2D, V25.2D, V30.2D

    (1353) 0x473b28 LDP	Q29, Q28, [X2, #16]

    (1353) 0x473b2c LDP	Q26, Q27, [X1, #32]

    (1353) 0x473b30 LDP	Q19, Q18, [X1], #64

    (1353) 0x473b34 LDR	Q16, [X2, #48]

    (1353) 0x473b38 LDR	Q7, [X2], #64

    (1353) 0x473b3c FMLA	V22.2D, V26.2D, V28.2D

    (1353) 0x473b40 FMLA	V21.2D, V18.2D, V29.2D

    (1353) 0x473b44 FMLA	V23.2D, V27.2D, V16.2D

    (1353) 0x473b48 FMLA	V0.2D, V19.2D, V7.2D

    (1353) 0x473b4c CMP	X1, X30

    (1353) 0x473b50 B.EQ	473c24

    (1353) 0x473b54 STR	W6, [SP, #104]

    (1353) 0x473b58 STR	X19, [SP, #112]

      (1355) 0x473b5c ORR	X6, XZR, X1

      (1355) 0x473b60 ORR	X9, XZR, X2

      (1355) 0x473b64 LDP	Q17, Q6, [X1, #16]

      (1355) 0x473b68 ADD	X20, X1, #192

      (1355) 0x473b6c ADD	X19, X2, #192

      (1355) 0x473b70 LDR	Q5, [X6], #64

      (1355) 0x473b74 ADD	X1, X1, #256

      (1355) 0x473b78 LDR	Q4, [X9], #64

      (1355) 0x473b7c LDP	Q24, Q20, [X2, #16]

      (1355) 0x473b80 LDP	Q25, Q31, [X2, #48]

      (1355) 0x473b84 ADD	X28, X6, #64

      (1355) 0x473b88 ADD	X2, X2, #256

      (1355) 0x473b8c LDUR	Q19, [X1, #304]

      (1355) 0x473b90 ADD	X27, X9, #64

      (1355) 0x473b94 FMLA	V0.2D, V5.2D, V4.2D

      (1355) 0x473b98 LDP	Q1, Q2, [X6, #16]

      (1355) 0x473b9c LDP	Q3, Q30, [X9, #16]

      (1355) 0x473ba0 FMLA	V21.2D, V17.2D, V24.2D

      (1355) 0x473ba4 LDP	Q29, Q28, [X9, #48]

      (1355) 0x473ba8 LDUR	Q7, [X1, #320]

      (1355) 0x473bac FMLA	V22.2D, V6.2D, V20.2D

      (1355) 0x473bb0 LDR	Q6, [X6, #48]

      (1355) 0x473bb4 FMLA	V23.2D, V19.2D, V25.2D

      (1355) 0x473bb8 LDP	Q26, Q27, [X27, #16]

      (1355) 0x473bbc LDP	Q18, Q16, [X28, #16]

      (1355) 0x473bc0 FMLA	V21.2D, V1.2D, V3.2D

      (1355) 0x473bc4 LDR	Q3, [X28, #48]

      (1355) 0x473bc8 LDR	Q1, [X6, #64]

      (1355) 0x473bcc FMLA	V22.2D, V2.2D, V30.2D

      (1355) 0x473bd0 LDR	Q2, [X27, #48]

      (1355) 0x473bd4 FMLA	V0.2D, V7.2D, V31.2D

      (1355) 0x473bd8 LDP	Q5, Q17, [X19, #16]

      (1355) 0x473bdc FMLA	V23.2D, V6.2D, V29.2D

      (1355) 0x473be0 LDUR	Q4, [X2, #448]

      (1355) 0x473be4 LDP	Q24, Q20, [X20, #16]

      (1355) 0x473be8 FMLA	V21.2D, V18.2D, V26.2D

      (1355) 0x473bec LDUR	Q30, [X1, #448]

      (1355) 0x473bf0 LDR	Q25, [X19, #48]

      (1355) 0x473bf4 FMLA	V22.2D, V16.2D, V27.2D

      (1355) 0x473bf8 LDR	Q31, [X20, #48]

      (1355) 0x473bfc FMLA	V0.2D, V1.2D, V28.2D

      (1355) 0x473c00 FMLA	V23.2D, V3.2D, V2.2D

      (1355) 0x473c04 FMLA	V21.2D, V24.2D, V5.2D

      (1355) 0x473c08 FMLA	V22.2D, V20.2D, V17.2D

      (1355) 0x473c0c FMLA	V23.2D, V31.2D, V25.2D

      (1355) 0x473c10 FMLA	V0.2D, V30.2D, V4.2D

      (1355) 0x473c14 CMP	X1, X30

      (1355) 0x473c18 B.NE	473b5c

    (1353) 0x473c1c LDR	X19, [SP, #112]

    (1353) 0x473c20 LDR	W6, [SP, #104]

    (1353) 0x473c24 FADD	V0.2D, V0.2D, V21.2D

    (1353) 0x473c28 ORR	W20, WZR, W24

    (1353) 0x473c2c FADD	V23.2D, V22.2D, V23.2D

    (1353) 0x473c30 FADD	V21.2D, V0.2D, V23.2D

    (1353) 0x473c34 FADDP	D27, V21.2D

    (1353) 0x473c38 CMP	W6, W24

    (1353) 0x473c3c B.EQ	473ed4

    (1353) 0x473c40 ORR	W9, WZR, W20

    (1353) 0x473c44 SUB	W2, W6, W20

    (1353) 0x473c48 DUP	Z22.D, #0

    (1353) 0x473c4c WHILELO	P7.D, WZR, W2

    (1353) 0x473c50 ADD	X27, X11, X9

    (1353) 0x473c54 ADD	X30, X12, X9

    (1353) 0x473c58 ADD	X28, X21, X27,LSL #3

    (1353) 0x473c5c MOVZ	X1, #0

    (1353) 0x473c60 ADD	X20, X5, X30,LSL #3

      (1352) 0x473c64 LD1D	{Z29.D}, P7/Z, [X28, X1,LSL #3]

      (1352) 0x473c68 LD1D	{Z28.D}, P7/Z, [X20, X1,LSL #3]

      (1352) 0x473c6c ADD	X1, X1, X10

      (1352) 0x473c70 FMLA	Z22.D, P7/M, Z29.D, Z28.D

      (1352) 0x473c74 WHILELO	P7.D, W1, W2

      (1352) 0x473c78 B.NE	473c64

    (1353) 0x473c7c LDR	X9, [X7, #280]

    (1353) 0x473c80 FADDV	D26, P6, Z22.D

    (1353) 0x473c84 FADD	D27, D27, D26

    (1353) 0x473c88 LDR	X28, [X7, #320]

    (1353) 0x473c8c MADD	X20, X3, X9, XZR

    (1353) 0x473c90 CMP	W14, #2

    (1353) 0x473c94 B.LS	473ef0

    (1353) 0x473c98 ADD	X2, X20, X20,LSL #1

    (1353) 0x473c9c MOVI	V1.2D, #0

    (1353) 0x473ca0 ORR	X9, XZR, X4

    (1353) 0x473ca4 ADD	X1, X28, X2,LSL #3

    (1353) 0x473ca8 UBFM	X2, X2, #61, #60

    (1353) 0x473cac ORR	V24.16B, V1.16B, V1.16B

    (1353) 0x473cb0 ORR	V19.16B, V1.16B, V1.16B

    (1353) 0x473cb4 UMADDL	X27, W25, W23, X1

    (1353) 0x473cb8 ORR	V18.16B, V1.16B, V1.16B

    (1353) 0x473cbc ORR	V17.16B, V1.16B, V1.16B

    (1353) 0x473cc0 ORR	V16.16B, V1.16B, V1.16B

    (1353) 0x473cc4 SUB	X30, X27, X1

    (1353) 0x473cc8 TBZ	W30, #5, 473d08

    (1353) 0x473ccc LDP	Q7, Q6, [X4]

    (1353) 0x473cd0 ADD	X9, X4, #32

    (1353) 0x473cd4 LDP	Q5, Q4, [X1, #16]

    (1353) 0x473cd8 LDP	Q25, Q31, [X1, #48]

    (1353) 0x473cdc ADD	X1, X1, #96

    (1353) 0x473ce0 LDUR	Q2, [X1, #496]

    (1353) 0x473ce4 LDR	Q20, [X28, X2]

    (1353) 0x473ce8 FMLA	V17.2D, V5.2D, V7.2D

    (1353) 0x473cec FMLA	V16.2D, V20.2D, V7.D[0]

    (1353) 0x473cf0 FMLA	V18.2D, V4.2D, V7.D[1]

    (1353) 0x473cf4 FMLA	V19.2D, V25.2D, V6.D[0]

    (1353) 0x473cf8 FMLA	V24.2D, V31.2D, V6.2D

    (1353) 0x473cfc FMLA	V1.2D, V2.2D, V6.D[1]

    (1353) 0x473d00 CMP	X27, X1

    (1353) 0x473d04 B.EQ	473d7c

      (1354) 0x473d08 ORR	X2, XZR, X1

      (1354) 0x473d0c LDP	Q3, Q30, [X9]

      (1354) 0x473d10 ORR	X30, XZR, X9

      (1354) 0x473d14 ADD	X9, X9, #64

      (1354) 0x473d18 LDR	Q29, [X2], #96

      (1354) 0x473d1c LDP	Q0, Q23, [X1, #16]

      (1354) 0x473d20 LDP	Q21, Q22, [X1, #48]

      (1354) 0x473d24 ADD	X1, X1, #192

      (1354) 0x473d28 LDUR	Q7, [X1, #400]

      (1354) 0x473d2c FMLA	V16.2D, V29.2D, V3.D[0]

      (1354) 0x473d30 LDP	Q28, Q26, [X2, #16]

      (1354) 0x473d34 LDP	Q20, Q5, [X2, #48]

      (1354) 0x473d38 FMLA	V17.2D, V0.2D, V3.2D

      (1354) 0x473d3c LDUR	Q6, [X1, #416]

      (1354) 0x473d40 LDUR	Q25, [X9, #480]

      (1354) 0x473d44 FMLA	V18.2D, V23.2D, V3.D[1]

      (1354) 0x473d48 LDR	Q31, [X30, #48]

      (1354) 0x473d4c FMLA	V19.2D, V21.2D, V30.D[0]

      (1354) 0x473d50 LDR	Q4, [X2, #80]

      (1354) 0x473d54 FMLA	V24.2D, V22.2D, V30.2D

      (1354) 0x473d58 FMLA	V1.2D, V7.2D, V30.D[1]

      (1354) 0x473d5c FMLA	V16.2D, V6.2D, V25.D[0]

      (1354) 0x473d60 FMLA	V17.2D, V28.2D, V25.2D

      (1354) 0x473d64 FMLA	V18.2D, V26.2D, V25.D[1]

      (1354) 0x473d68 FMLA	V19.2D, V20.2D, V31.D[0]

      (1354) 0x473d6c FMLA	V24.2D, V5.2D, V31.2D

      (1354) 0x473d70 FMLA	V1.2D, V4.2D, V31.D[1]

      (1354) 0x473d74 CMP	X27, X1

      (1354) 0x473d78 B.NE	473d08

    (1353) 0x473d7c EXT	V3.16B, V24.16B, V1.16B, #8

    (1353) 0x473d80 EXT	V2.16B, V17.16B, V18.16B, #8

    (1353) 0x473d84 MOV	D1, V1.D[1]

    (1353) 0x473d88 MOV	D18, V18.D[1]

    (1353) 0x473d8c FADD	V16.2D, V19.2D, V16.2D

    (1353) 0x473d90 FADD	D17, D17, D24

    (1353) 0x473d94 FADD	V19.2D, V3.2D, V2.2D

    (1353) 0x473d98 FADD	D24, D1, D18

    (1353) 0x473d9c FADD	V31.2D, V19.2D, V16.2D

    (1353) 0x473da0 FADD	D26, D17, D24

    (1353) 0x473da4 CBZ	W26, 473e3c

    (1353) 0x473da8 LDR	W30, [SP, #120]

    (1353) 0x473dac ADD	X27, X20, W30,SXTW

    (1353) 0x473db0 ADD	X1, X27, X27,LSL #1

    (1353) 0x473db4 ORR	W9, WZR, W30

    (1353) 0x473db8 UBFM	X9, X9, #61, #60

    (1353) 0x473dbc ADD	X27, X28, X1,LSL #3

    (1353) 0x473dc0 UBFM	X2, X1, #61, #60

    (1353) 0x473dc4 ADD	W1, W30, #1

    (1353) 0x473dc8 LDR	D30, [X4, X9]

    (1353) 0x473dcc LDR	Q0, [X28, X2]

    (1353) 0x473dd0 LDR	D23, [X27, #16]

    (1353) 0x473dd4 FMLA	V31.2D, V0.2D, V30.D[0]

    (1353) 0x473dd8 FMADD	D26, D23, D30, D26

    (1353) 0x473ddc CMP	W6, W1

    (1353) 0x473de0 B.LE	473e3c

    (1353) 0x473de4 ADD	X27, X20, W1,SXTW

    (1353) 0x473de8 ADD	X2, X27, X27,LSL #1

    (1353) 0x473dec ADD	X9, X4, X9

    (1353) 0x473df0 ADD	W30, W30, #2

    (1353) 0x473df4 ADD	X1, X28, X2,LSL #3

    (1353) 0x473df8 UBFM	X27, X2, #61, #60

    (1353) 0x473dfc LDR	D22, [X9, #8]

    (1353) 0x473e00 LDR	Q21, [X28, X27]

    (1353) 0x473e04 LDR	D29, [X1, #16]

    (1353) 0x473e08 FMLA	V31.2D, V21.2D, V22.D[0]

    (1353) 0x473e0c FMADD	D26, D22, D29, D26

    (1353) 0x473e10 CMP	W6, W30

    (1353) 0x473e14 B.LE	473e3c

    (1353) 0x473e18 ADD	X20, X20, W30,SXTW

    (1353) 0x473e1c ADD	X30, X20, X20,LSL #1

    (1353) 0x473e20 LDR	D5, [X9, #16]

    (1353) 0x473e24 ADD	X2, X28, X30,LSL #3

    (1353) 0x473e28 UBFM	X1, X30, #61, #60

    (1353) 0x473e2c LDR	Q28, [X28, X1]

    (1353) 0x473e30 LDR	D20, [X2, #16]

    (1353) 0x473e34 FMLA	V31.2D, V28.2D, V5.D[0]

    (1353) 0x473e38 FMADD	D26, D20, D5, D26

    (1353) 0x473e3c MOV	D7, V31.D[1]

    (1353) 0x473e40 FMUL	D28, D26, D26

    (1353) 0x473e44 FMUL	D30, D31, D31

    (1353) 0x473e48 FMUL	D29, D7, D7

    (1353) 0x473e4c LDR	Q4, [X0]

    (1353) 0x473e50 FADD	D6, D29, D30

    (1353) 0x473e54 ADD	X4, X4, X18

    (1353) 0x473e58 ADD	X8, X8, X17

    (1353) 0x473e5c ADD	X11, X11, X16

    (1353) 0x473e60 ADD	X12, X12, X15

    (1353) 0x473e64 LDR	D25, [X0, #16]

    (1353) 0x473e68 ADD	X0, X0, #24

    (1353) 0x473e6c FADD	V31.2D, V4.2D, V31.2D

    (1353) 0x473e70 FADD	D26, D25, D26

    (1353) 0x473e74 STUR	Q31, [X0, #488]

    (1353) 0x473e78 STUR	D26, [X0, #504]

    (1353) 0x473e7c LDR	D3, [X13, X3,LSL #3]

    (1353) 0x473e80 FADD	D27, D27, D3

    (1353) 0x473e84 FSUB	D2, D27, S28

    (1353) 0x473e88 FSUB	D1, D2, S6

    (1353) 0x473e8c STR	D1, [X13, X3,LSL #3]

    (1353) 0x473e90 ADD	X3, X3, #1

    (1353) 0x473e94 CMP	X19, X3

    (1353) 0x473e98 B.NE	473a84

(1356) 0x473e9c LDP	X19, X20, [SP, #16]

(1356) 0x473ea0 LDP	X21, X22, [SP, #32]

(1356) 0x473ea4 LDP	X23, X24, [SP, #48]

(1356) 0x473ea8 LDP	X25, X26, [SP, #64]

(1356) 0x473eac LDP	X27, X28, [SP, #80]

(1356) 0x473eb0 LDP	X29, X30, [SP], #272

(1356) 0x473eb4 RET

  (1351) 0x473eb8 MOVI	V31.2D, #0

  (1351) 0x473ebc FMOV	D30, D31

  (1351) 0x473ec0 FMOV	D29, D31

  (1351) 0x473ec4 FMOV	D28, D31

  (1351) 0x473ec8 FMOV	D27, D31

  (1351) 0x473ecc FMOV	D26, D31

  (1351) 0x473ed0 B	473e4c

    (1353) 0x473ed4 LDR	X30, [X7, #280]

    (1353) 0x473ed8 LDR	X28, [X7, #320]

    (1353) 0x473edc MADD	X20, X3, X30, XZR

    (1353) 0x473ee0 B	473c98

    (1353) 0x473ee4 MOVI	D27, #0

    (1353) 0x473ee8 MOVZ	W20, #0

    (1353) 0x473eec B	473c40

    (1353) 0x473ef0 MOVI	V31.2D, #0

    (1353) 0x473ef4 MOVZ	W30, #0

    (1353) 0x473ef8 FMOV	D26, D31

    (1353) 0x473efc B	473dac

(1350) 0x473f00 LDR	X15, [X7, #256]

(1350) 0x473f04 MOVZ	W10, #24

(1350) 0x473f08 SBFM	X14, X30, #61, #31

(1350) 0x473f0c LDP	X17, X5, [SP, #120]

(1350) 0x473f10 SMADDL	X16, W30, W10, XZR

(1350) 0x473f14 LDR	X18, [X7, #320]

(1350) 0x473f18 LDR	D19, [X15]

(1350) 0x473f1c LDR	X13, [X17, #24]

(1350) 0x473f20 LDP	D18, D16, [X18]

(1350) 0x473f24 LDR	D17, [X18, #16]

(1350) 0x473f28 ADD	X6, X13, X16

(1350) 0x473f2c LDR	X9, [X5, #24]

(1350) 0x473f30 FMUL	D24, D19, D18

(1350) 0x473f34 FMUL	D30, D19, D16

(1350) 0x473f38 LDR	X7, [X7, #384]

(1350) 0x473f3c FMUL	D23, D19, D17

(1350) 0x473f40 STP	D24, D30, [SP, #224]

(1350) 0x473f44 FMUL	D0, D30, D30

(1350) 0x473f48 LDR	Q21, [X13, X16]

(1350) 0x473f4c LDR	Q29, [SP, #224]

(1350) 0x473f50 FMADD	D22, D24, D24, D0

(1350) 0x473f54 FADD	V28.2D, V21.2D, V29.2D

(1350) 0x473f58 STR	Q28, [X13, X16]

(1350) 0x473f5c LDR	D20, [X6, #16]

(1350) 0x473f60 FADD	D5, D20, D23

(1350) 0x473f64 STR	D5, [X6, #16]

(1350) 0x473f68 LDR	D7, [X9, X14]

(1350) 0x473f6c LDR	D6, [X7]

(1350) 0x473f70 FMADD	D4, D19, D6, D7

(1350) 0x473f74 FMSUB	D25, D23, D23, D4

(1350) 0x473f78 FSUB	D31, D25, S22

(1350) 0x473f7c STR	D31, [X9, X14]

(1350) 0x473f80 LDP	X29, X30, [SP], #272

(1350) 0x473f84 RET

(1350) 0x473f88 STP	X21, X22, [SP, #32]

(1350) 0x473f8c LDR	X0, [X7, #1128]

(1350) 0x473f90 STR	X7, [SP, #104]

(1350) 0x473f94 BL	4d5540

(1350) 0x473f98 LDR	X7, [SP, #104]

(1350) 0x473f9c ADRP	X1,

(1350) 0x473fa0 ADD	X4, X1, #320

(1350) 0x473fa4 LDR	X21, [X7, #1136]

(1350) 0x473fa8 LDR	W2, [X7, #1144]

(1350) 0x473fac LDR	W3, [X7, #1148]

(1350) 0x473fb0 LDR	X5, [X21]

(1350) 0x473fb4 STR	W2, [SP, #104]

(1350) 0x473fb8 LDR	X8, [X5, #40]

(1350) 0x473fbc CMP	X8, X4

(1350) 0x473fc0 B.NE	474154

(1350) 0x473fc4 CMP	W2, W3

(1350) 0x473fc8 B.GE	4740f0

(1350) 0x473fcc STP	X19, X20, [SP, #16]

(1350) 0x473fd0 ADRP	X19,

(1350) 0x473fd4 ADRP	X20,

(1350) 0x473fd8 SUB	W3, W3, W2

(1350) 0x473fdc MOVZ	X22, #0

(1350) 0x473fe0 ADD	X19, X19, #120

(1350) 0x473fe4 ADD	X20, X20, #2664

(1350) 0x473fe8 STP	X23, X24, [SP, #48]

(1350) 0x473fec ADD	X24, X7, #360

(1350) 0x473ff0 ADD	X23, X7, #336

(1350) 0x473ff4 STP	X25, X26, [SP, #64]

(1350) 0x473ff8 ADD	X26, X7, #296

(1350) 0x473ffc ADD	X25, X7, #272

(1350) 0x474000 STP	X27, X28, [SP, #80]

(1350) 0x474004 ADD	X28, X7, #168

(1350) 0x474008 ADD	X27, X7, #144

(1350) 0x47400c STR	X3, [SP, #112]

(1350) 0x474010 STR	X7, [SP, #136]

(1350) 0x474014 HINT	#0

(1350) 0x474018 HINT	#0

(1350) 0x47401c HINT	#0

  (1357) 0x474020 LDR	X13, [X25, #8]

  (1357) 0x474024 ADD	X5, SP, #224

  (1357) 0x474028 ADD	X4, SP, #184

  (1357) 0x47402c STR	X19, [SP, #144]

  (1357) 0x474030 ADD	X3, SP, #144

  (1357) 0x474034 LDR	X9, [X23, #8]

  (1357) 0x474038 STR	X20, [SP, #184]

  (1357) 0x47403c LDR	X30, [X27, #8]

  (1357) 0x474040 MADD	X14, X22, X13, XZR

  (1357) 0x474044 LDR	X1, [X28, #24]

  (1357) 0x474048 MADD	X11, X22, X9, XZR

  (1357) 0x47404c LDR	X10, [X24, #24]

  (1357) 0x474050 ADD	X15, X14, X14,LSL #1

  (1357) 0x474054 MADD	X0, X22, X30, XZR

  (1357) 0x474058 LDR	X16, [X26, #24]

  (1357) 0x47405c LDRSW	X18, [X21, #8]

  (1357) 0x474060 ADD	X8, X1, X0,LSL #3

  (1357) 0x474064 ORR	X0, XZR, X21

  (1357) 0x474068 STR	X19, [SP, #224]

  (1357) 0x47406c ADD	X12, X10, X11,LSL #3

  (1357) 0x474070 LDR	X7, [X21]

  (1357) 0x474074 ADD	X17, X16, X15,LSL #3

  (1357) 0x474078 STR	XZR, [SP, #160]

  (1357) 0x47407c LDR	W6, [SP, #104]

  (1357) 0x474080 STR	X18, [SP, #152]

  (1357) 0x474084 LDR	X1, [SP, #96]

  (1357) 0x474088 STR	X8, [SP, #168]

  (1357) 0x47408c STP	X18, XZR, [SP, #192]

  (1357) 0x474090 ADD	W2, W6, W22

  (1357) 0x474094 LDR	X6, [X7, #24]

  (1357) 0x474098 STR	X17, [SP, #208]

  (1357) 0x47409c STP	X18, XZR, [SP, #232]

  (1357) 0x4740a0 STR	X12, [SP, #248]

  (1357) 0x4740a4 BLR	X6

  (1357) 0x4740a8 LDR	X3, [SP, #240]

  (1357) 0x4740ac STR	X19, [SP, #224]

  (1357) 0x4740b0 CBNZ	X3, 474144

  (1357) 0x4740b4 LDR	X9, [SP, #200]

  (1357) 0x4740b8 STR	X20, [SP, #184]

  (1357) 0x4740bc CBNZ	X9, 474108

  (1357) 0x4740c0 LDR	X10, [SP, #160]

  (1357) 0x4740c4 STR	X19, [SP, #144]

  (1357) 0x4740c8 CBNZ	X10, 474124

  (1357) 0x4740cc LDR	X12, [SP, #112]

  (1357) 0x4740d0 ADD	X22, X22, #1

  (1357) 0x4740d4 CMP	X22, X12

  (1357) 0x4740d8 B.NE	474020

(1350) 0x4740dc LDR	X7, [SP, #136]

(1350) 0x4740e0 LDP	X19, X20, [SP, #16]

(1350) 0x4740e4 LDP	X23, X24, [SP, #48]

(1350) 0x4740e8 LDP	X25, X26, [SP, #64]

(1350) 0x4740ec LDP	X27, X28, [SP, #80]

(1350) 0x4740f0 STR	X7, [SP, #96]

(1350) 0x4740f4 LDR	X0, [X7, #1128]

(1350) 0x4740f8 BL	4d57e0

(1350) 0x4740fc LDR	X7, [SP, #96]

(1350) 0x474100 LDP	X21, X22, [SP, #32]

(1350) 0x474104 B	4739dc

  (1357) 0x474108 ADD	X11, X9, X9,LSL #1

  (1357) 0x47410c LDR	X0, [SP, #208]

  (1357) 0x474110 UBFM	X1, X11, #61, #60

  (1357) 0x474114 BL	403da0

  (1357) 0x474118 LDR	X10, [SP, #160]

  (1357) 0x47411c STR	X19, [SP, #144]

  (1357) 0x474120 CBZ	X10, 4740cc

  (1357) 0x474124 LDR	X0, [SP, #168]

  (1357) 0x474128 UBFM	X1, X10, #61, #60

  (1357) 0x47412c ADD	X22, X22, #1

  (1357) 0x474130 BL	403da0

  (1357) 0x474134 LDR	X13, [SP, #112]

  (1357) 0x474138 CMP	X22, X13

  (1357) 0x47413c B.NE	474020

(1350) 0x474140 B	4740dc

  (1357) 0x474144 LDR	X0, [SP, #248]

  (1357) 0x474148 UBFM	X1, X3, #61, #60

  (1357) 0x47414c BL	403da0

  (1357) 0x474150 B	4740b4

(1350) 0x474154 LDR	X1, [SP, #96]

(1350) 0x474158 ADD	X6, X7, #336

(1350) 0x47415c ADD	X5, X7, #272

(1350) 0x474160 ADD	X4, X7, #144

(1350) 0x474164 ORR	X0, XZR, X21

(1350) 0x474168 STR	X7, [SP, #96]

(1350) 0x47416c LDR	W2, [SP, #104]

(1350) 0x474170 BLR	X8

(1350) 0x474174 LDR	X7, [SP, #96]

(1350) 0x474178 B	4740f0

0x47417c LDP	X19, X20, [SP, #16]

0x474180 B	473eb0

0x474184 LDR	X4, [SP, #240]

0x474188 ORR	X22, XZR, X0

0x47418c STR	X19, [SP, #224]

0x474190 CBZ	X4, 4741a0

0x474194 LDR	X0, [SP, #248]

0x474198 UBFM	X1, X4, #61, #60

0x47419c BL	403da0

0x4741a0 LDR	X21, [SP, #200]

0x4741a4 STR	X20, [SP, #184]

0x4741a8 CBZ	X21, 4741bc

0x4741ac MOVZ	X2, #24

0x4741b0 LDR	X0, [SP, #208]

0x4741b4 MADD	X1, X21, X2, XZR

0x4741b8 BL	403da0

0x4741bc LDR	X5, [SP, #160]

0x4741c0 STR	X19, [SP, #144]

0x4741c4 CBZ	X5, 4741d4

0x4741c8 LDR	X0, [SP, #168]

0x4741cc UBFM	X1, X5, #61, #60

0x4741d0 BL	403da0

0x4741d4 ORR	X0, XZR, X22

0x4741d8 BL	404170

0x4741dc HINT	#0

Coverage (%)	Name	Source Location	Module
►50.23+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:250	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►48.65+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:152-181
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h:104,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:110,129-131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:56,144,210,221-223,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:152-181
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:106-111
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 2.50 cycles (4.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 54% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 10.17 to 7.42 cycles (1.37x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.17 to 2.00 cycles (5.08x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	70
loop length	280
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.00	5.00	5.67	5.67	5.67	5.67	5.67	5.67	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50
cycles	5.00	5.00	5.67	5.67	5.67	5.67	5.67	5.67	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Overall L1	10.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.17 cycles. At this rate:

13% of peak load performance is reached (13.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.95 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4739c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X7, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W0, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CBZ W0, 473f88 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SBFM X19, X14, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
CBZ W14, 47417c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X12, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X10, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W22, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W23, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W27, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X28, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X7, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X7, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SMADDL X0, W30, W27, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X15, [X7, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X18, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X7, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X4, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W6, [X7, #1152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X2, W30,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ORR X8, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND W9, W6, #1886	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM W30, W6, #3, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W14, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM W25, W6, #2, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W26, W6, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W24, W6, #1821	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 473eb0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X4, 4741a0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403da0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X21, 4741bc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X2, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X1, X21, X2, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
BL 403da0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X5, 4741d4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x814>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403da0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404170 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:152-181
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/new_allocator.h:104,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorOps.h:110,129-131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:56,144,210,221-223,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:152-181
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/SPOSet.h:106-111
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.17 to 2.50 cycles (4.07x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.17 to 2.00 cycles (5.08x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 136 bytes. The binary function is storing 152 bytes.

General properties

nb instructions	70
loop length	280
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

8.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	5.00	5.00	5.67	5.67	5.67	5.67	5.67	5.67	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50
cycles	5.00	5.00	5.67	5.67	5.67	5.67	5.67	5.67	0.00	0.00	0.00	0.00	10.17	9.83	10.00	6.50	6.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	8.63
Overall L1	10.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.17 cycles. At this rate:

13% of peak load performance is reached (13.38 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
31% of peak store performance is reached (14.95 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4739c0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #752]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X7, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W0, [X0, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X1, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP X2, X3, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
CBZ W0, 473f88 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x5c8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SBFM X19, X14, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
CBZ W14, 47417c <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x7bc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X12, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X11, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P6.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
LDR X20, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ X3, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CNTD X10, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W22, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X1, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W23, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ W27, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X28, [X20, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X16, [X7, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X21, [X7, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SMADDL X0, W30, W27, X28	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR X15, [X7, #344]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
UBFM X18, X16, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X5, [X7, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X4, XZR, X21	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W6, [X7, #1152]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X17, X15, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X2, [X1, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X2, W30,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
ORR X8, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
AND W9, W6, #1886	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
UBFM W30, W6, #3, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SUB W14, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
UBFM W25, W6, #2, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W26, W6, #64	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
AND W24, W6, #1821	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W30, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W9, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
B 473eb0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x4f0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X19, [SP, #224]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X4, 4741a0 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x7e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #248]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X4, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403da0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X21, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X20, [SP, #184]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X21, 4741bc <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x7fc>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ X2, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MADD X1, X21, X2, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
BL 403da0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X5, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X19, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
CBZ X5, 4741d4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE10evaluateGLERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEEb+0x814>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
UBFM X1, X5, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403da0 <@plt_start@+0xb0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404170 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evaluateGL(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus:...–	0.62	0.86
▼Loop 1350 - DiracDeterminantRef.cpp:159-181 - exec–	0.00	0.00
○Loop 1357 - SPOSet.h:106-111 - exec	0.00	0.00
▼Loop 1356 - DiracDeterminantRef.cpp:173-181 - exec–	0.00	0.00
▼Loop 1351 - OperatorTags.h:61-94 - exec–	0.00	0.00
▼Loop 1353 - DiracDeterminantRef.cpp:173-178 - exec–	0.00	0.00
○Loop 1354 - inner_product.hpp:155-155 - exec	0.39	0.53
○Loop 1355 - inner_product.hpp:83-83 - exec	0.23	0.31
○Loop 1352 - inner_product.hpp:82-83 - exec	0.00	0.00

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Code clean check

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Vectorization

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Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

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Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code