OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGrad(qmcplusplus::ParticleSet&, int)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::evalGr ...	Module: exec	Source: DiracDeterminantRef.cpp:82-91 [...]	Coverage (incl. loops): 0.36% \| (excl. loops): 0.01%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 155 - 156

--------------------------------------------------------------------------------

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 82 - 91

--------------------------------------------------------------------------------

82: typename DiracDeterminantRef<DU_TYPE>::GradType DiracDeterminantRef<DU_TYPE>::evalGrad(ParticleSet& P, int iat)

83: {

84:   const int WorkingIndex = iat - FirstIndex;

85:   RatioTimer->start();

86:   invRow_id = WorkingIndex;

87:   updateEng.getInvRow(psiM, WorkingIndex, invRow);

88:   GradType g = simd::dot(invRow.data(), dpsiM[WorkingIndex], invRow.size());

89:   RatioTimer->stop();

90:   return g;

91: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 413 - 453

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 98 - 113

--------------------------------------------------------------------------------

98:     if (delay_count == 0)

99:     {

100:       // Ainv is fresh, directly access Ainv

101:       std::copy_n(Ainv[rowchanged], invRow.size(), invRow.data());

102:       return;

103:     }

104:     const T cone(1);

105:     const T czero(0);

106:     const int norb     = Ainv.rows();

107:     const int lda_Binv = Binv.cols();

108:     // save Ainv[rowchanged] to invRow

109:     std::copy_n(Ainv[rowchanged], norb, invRow.data());

110:     // multiply V (NxK) Binv(KxK) U(KxN) invRow right to the left

111:     BLAS::gemv('T', norb, delay_count, cone, U.data(), norb, invRow.data(), 1, czero, p.data(), 1);

112:     BLAS::gemv('N', delay_count, delay_count, cone, Binv.data(), lda_Binv, p.data(), 1, czero, Binv[delay_count], 1);

113:     BLAS::gemv('N', norb, delay_count, -cone, V.data(), norb, Binv[delay_count], 1, cone, invRow.data(), 1);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 217

--------------------------------------------------------------------------------

77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

214:   inline const Type_t* operator[](size_type i) const { return X.data() + i * D2; }

215:

216:   /// returns a pointer of i-th row, g++ iterator problem

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

0x4730e0 SUB	SP, SP, #272

0x4730e4 STP	X29, X30, [SP, #32]

0x4730e8 ADD	X29, SP, #32

0x4730ec STP	X19, X20, [SP, #48]

0x4730f0 ORR	X19, XZR, X0

0x4730f4 STP	X21, X22, [SP, #64]

0x4730f8 STP	X25, X26, [SP, #96]

0x4730fc ADD	X25, X0, #520

0x473100 LDR	W1, [X0, #1144]

0x473104 LDR	X0, [X0, #1096]

0x473108 STR	D15, [SP, #128]

0x47310c SUB	W20, W2, W1

0x473110 BL	4d5540

0x473114 LDR	X0, [X19, #216]

0x473118 SBFM	X21, X20, #0, #31

0x47311c STR	W20, [X19, #1072]

0x473120 LDR	X4, [X19, #256]

0x473124 LDR	W3, [X25, #360]

0x473128 MADD	X2, X21, X0, XZR

0x47312c ADD	X1, X4, X2,LSL #3

0x473130 UBFM	X5, X2, #61, #60

0x473134 CBZ	W3, 4734c4

0x473138 STP	X23, X24, [SP, #80]

0x47313c ADD	X20, X19, #648

0x473140 ADD	X24, X19, #1032

0x473144 STP	X27, X28, [SP, #112]

0x473148 LDR	X23, [X19, #208]

0x47314c LDR	X22, [X20, #8]

0x473150 LDR	X6, [X24, #24]

0x473154 CMP	W23, #0

0x473158 B.LE	473178

0x47315c UBFM	X2, X23, #61, #31

0x473160 CMP	X2, #8

0x473164 B.EQ	473508

0x473168 ORR	X0, XZR, X6

0x47316c BL	403d70

0x473170 LDR	X6, [X24, #24]

0x473174 LDR	W3, [X25, #360]

0x473178 FMOV	D15, #1.0000000

0x47317c ADD	X27, SP, #228

0x473180 ADD	X28, SP, #240

0x473184 STR	XZR, [SP, #240]

0x473188 LDR	X8, [X19, #840]

0x47318c MOVZ	W7, #84

0x473190 MOVZ	W26, #1

0x473194 ADD	X12, X19, #816

0x473198 ADD	X5, SP, #220

0x47319c LDR	X4, [X19, #568]

0x4731a0 ADD	X2, SP, #216

0x4731a4 ADD	X0, SP, #211

0x4731a8 ADD	X1, SP, #212

0x4731ac STR	X27, [SP, #16]

0x4731b0 STRB	W7, [SP, #211]

0x4731b4 ADD	X7, SP, #224

0x4731b8 STP	X28, X8, [SP]

0x4731bc STP	W23, W3, [SP, #212]

0x4731c0 ADD	X3, SP, #232

0x4731c4 STR	X12, [SP, #168]

0x4731c8 STP	W23, W26, [SP, #220]

0x4731cc STR	W26, [SP, #228]

0x4731d0 STR	D15, [SP, #232]

0x4731d4 BL	404030

0x4731d8 LDR	W9, [X25, #360]

0x4731dc MOVZ	W10, #78

0x4731e0 ADD	X11, X19, #672

0x4731e4 STR	X28, [SP]

0x4731e8 ADD	X7, SP, #224

0x4731ec ADD	X5, SP, #220

0x4731f0 STP	W22, W26, [SP, #220]

0x4731f4 ADD	X3, SP, #232

0x4731f8 ADD	X2, SP, #216

0x4731fc LDR	X14, [SP, #168]

0x473200 ADD	X1, SP, #212

0x473204 ADD	X0, SP, #211

0x473208 STR	W10, [SP, #144]

0x47320c STP	W9, W9, [SP, #212]

0x473210 SBFM	X6, X9, #0, #31

0x473214 LDR	X13, [X20, #8]

0x473218 STR	X27, [SP, #16]

0x47321c LDR	X4, [X19, #696]

0x473220 STR	X11, [SP, #160]

0x473224 STRB	W10, [SP, #211]

0x473228 MADD	X15, X6, X13, XZR

0x47322c LDR	X6, [X14, #24]

0x473230 STR	W26, [SP, #228]

0x473234 STR	D15, [SP, #232]

0x473238 ADD	X18, X4, X15,LSL #3

0x47323c STR	XZR, [SP, #240]

0x473240 STR	X18, [SP, #8]

0x473244 BL	404030

0x473248 LDR	W25, [X25, #360]

0x47324c FMOV	D0, #-1.0000000

0x473250 ADD	X3, SP, #232

0x473254 ADD	X0, SP, #211

0x473258 STR	X28, [SP]

0x47325c ADD	X7, SP, #224

0x473260 ADD	X5, SP, #220

0x473264 LDR	X12, [SP, #160]

0x473268 ADD	X2, SP, #216

0x47326c ADD	X1, SP, #212

0x473270 STP	W23, W26, [SP, #220]

0x473274 STP	D0, D15, [SP, #232]

0x473278 STP	W23, W25, [SP, #212]

0x47327c SBFM	X4, X25, #0, #31

0x473280 LDR	X20, [X20, #8]

0x473284 STR	W26, [SP, #228]

0x473288 LDR	X23, [X12, #24]

0x47328c LDR	X26, [X24, #24]

0x473290 MADD	X28, X4, X20, XZR

0x473294 LDR	W22, [SP, #144]

0x473298 ADD	X6, X23, X28,LSL #3

0x47329c STP	X26, X27, [SP, #8]

0x4732a0 LDR	X4, [X19, #632]

0x4732a4 STRB	W22, [SP, #211]

0x4732a8 BL	404030

0x4732ac LDR	X3, [X24, #8]

0x4732b0 LDP	X27, X28, [SP, #112]

0x4732b4 LDR	X0, [X24, #24]

0x4732b8 LDP	X23, X24, [SP, #80]

(1347) 0x4732bc ORR	W16, WZR, W3

(1347) 0x4732c0 LDR	X17, [X19, #280]

(1347) 0x4732c4 LDR	X30, [X19, #320]

(1347) 0x4732c8 MADD	X21, X21, X17, XZR

(1347) 0x4732cc CMP	W3, #0

(1347) 0x4732d0 B.LE	4734ec

(1347) 0x4732d4 SUB	W1, W3, #1

(1347) 0x4732d8 ORR	W5, WZR, W3

(1347) 0x4732dc CMP	W1, #2

(1347) 0x4732e0 B.LS	4734f8

(1347) 0x4732e4 ADD	X8, X21, X21,LSL #1

(1347) 0x4732e8 UBFM	W11, W3, #2, #31

(1347) 0x4732ec MOVZ	W2, #96

(1347) 0x4732f0 MOVI	V26.2D, #0

(1347) 0x4732f4 ORR	X6, XZR, X0

(1347) 0x4732f8 ADD	X13, X30, X8,LSL #3

(1347) 0x4732fc ORR	V4.16B, V26.16B, V26.16B

(1347) 0x473300 ORR	V22.16B, V26.16B, V26.16B

(1347) 0x473304 UMADDL	X10, W11, W2, X13

(1347) 0x473308 ORR	V3.16B, V26.16B, V26.16B

(1347) 0x47330c ORR	V19.16B, V26.16B, V26.16B

(1347) 0x473310 ORR	V5.16B, V26.16B, V26.16B

(1347) 0x473314 SUB	X9, X10, X13

(1347) 0x473318 TBZ	W9, #5, 473360

(1347) 0x47331c LDP	Q28, Q29, [X0]

(1347) 0x473320 ADD	X6, X0, #32

(1347) 0x473324 LDP	Q2, Q25, [X13, #16]

(1347) 0x473328 LDP	Q24, Q30, [X13, #48]

(1347) 0x47332c LDR	Q27, [X13, #80]

(1347) 0x473330 LDR	Q6, [X13], #96

(1347) 0x473334 FMLA	V19.2D, V28.2D, V2.2D

(1347) 0x473338 FMLA	V3.2D, V25.2D, V28.D[1]

(1347) 0x47333c FMLA	V22.2D, V24.2D, V29.D[0]

(1347) 0x473340 FMLA	V4.2D, V29.2D, V30.2D

(1347) 0x473344 FMLA	V5.2D, V6.2D, V28.D[0]

(1347) 0x473348 FMLA	V26.2D, V27.2D, V29.D[1]

(1347) 0x47334c CMP	X13, X10

(1347) 0x473350 B.EQ	4733c8

(1347) 0x473354 HINT	#0

(1347) 0x473358 HINT	#0

(1347) 0x47335c HINT	#0

  (1348) 0x473360 ORR	X14, XZR, X13

  (1348) 0x473364 LDP	Q16, Q17, [X6]

  (1348) 0x473368 LDR	Q7, [X14], #96

  (1348) 0x47336c LDP	Q18, Q23, [X13, #16]

  (1348) 0x473370 LDP	Q20, Q21, [X13, #48]

  (1348) 0x473374 LDP	Q0, Q1, [X13, #80]

  (1348) 0x473378 ADD	X13, X13, #192

  (1348) 0x47337c FMLA	V5.2D, V7.2D, V16.D[0]

  (1348) 0x473380 LDP	Q28, Q29, [X6, #32]

  (1348) 0x473384 ADD	X6, X6, #64

  (1348) 0x473388 LDP	Q31, Q15, [X14, #16]

  (1348) 0x47338c FMLA	V19.2D, V16.2D, V18.2D

  (1348) 0x473390 LDP	Q2, Q25, [X14, #48]

  (1348) 0x473394 LDR	Q24, [X14, #80]

  (1348) 0x473398 FMLA	V3.2D, V23.2D, V16.D[1]

  (1348) 0x47339c FMLA	V22.2D, V20.2D, V17.D[0]

  (1348) 0x4733a0 FMLA	V4.2D, V17.2D, V21.2D

  (1348) 0x4733a4 FMLA	V26.2D, V0.2D, V17.D[1]

  (1348) 0x4733a8 FMLA	V19.2D, V28.2D, V31.2D

  (1348) 0x4733ac FMLA	V3.2D, V15.2D, V28.D[1]

  (1348) 0x4733b0 FMLA	V22.2D, V2.2D, V29.D[0]

  (1348) 0x4733b4 FMLA	V4.2D, V29.2D, V25.2D

  (1348) 0x4733b8 FMLA	V5.2D, V1.2D, V28.D[0]

  (1348) 0x4733bc FMLA	V26.2D, V24.2D, V29.D[1]

  (1348) 0x4733c0 CMP	X13, X10

  (1348) 0x4733c4 B.NE	473360

(1347) 0x4733c8 MOV	D27, V3.D[1]

(1347) 0x4733cc AND	W7, W5, #1886

(1347) 0x4733d0 EXT	V3.16B, V19.16B, V3.16B, #8

(1347) 0x4733d4 MOV	D6, V26.D[1]

(1347) 0x4733d8 EXT	V26.16B, V4.16B, V26.16B, #8

(1347) 0x4733dc FADD	V30.2D, V5.2D, V22.2D

(1347) 0x4733e0 FADD	D19, D4, D19

(1347) 0x4733e4 FADD	V22.2D, V3.2D, V26.2D

(1347) 0x4733e8 FADD	D4, D27, D6

(1347) 0x4733ec FADD	V31.2D, V22.2D, V30.2D

(1347) 0x4733f0 FADD	D15, D4, D19

(1347) 0x4733f4 ANDS	XZR, X5, #4160

(1347) 0x4733f8 B.EQ	47348c

(1347) 0x4733fc ADD	X15, X21, W7,SXTW

(1347) 0x473400 ADD	X18, X15, X15,LSL #1

(1347) 0x473404 ORR	W25, WZR, W7

(1347) 0x473408 ADD	W22, W7, #1

(1347) 0x47340c UBFM	X12, X25, #61, #60

(1347) 0x473410 ADD	X20, X30, X18,LSL #3

(1347) 0x473414 UBFM	X4, X18, #61, #60

(1347) 0x473418 LDR	D5, [X0, X12]

(1347) 0x47341c LDR	Q7, [X30, X4]

(1347) 0x473420 LDR	D16, [X20, #16]

(1347) 0x473424 FMLA	V31.2D, V7.2D, V5.D[0]

(1347) 0x473428 FMADD	D15, D5, D16, D15

(1347) 0x47342c CMP	W16, W22

(1347) 0x473430 B.LE	47348c

(1347) 0x473434 ADD	X26, X21, W22,SXTW

(1347) 0x473438 ADD	X3, X26, X26,LSL #1

(1347) 0x47343c ADD	X17, X0, X12

(1347) 0x473440 ADD	W1, W7, #2

(1347) 0x473444 ADD	X0, X30, X3,LSL #3

(1347) 0x473448 UBFM	X5, X3, #61, #60

(1347) 0x47344c LDR	D23, [X17, #8]

(1347) 0x473450 LDR	Q17, [X30, X5]

(1347) 0x473454 LDR	D18, [X0, #16]

(1347) 0x473458 FMLA	V31.2D, V17.2D, V23.D[0]

(1347) 0x47345c FMADD	D15, D23, D18, D15

(1347) 0x473460 CMP	W16, W1

(1347) 0x473464 B.LE	47348c

(1347) 0x473468 ADD	X16, X21, W1,SXTW

(1347) 0x47346c ADD	X21, X16, X16,LSL #1

(1347) 0x473470 LDR	D0, [X17, #16]

(1347) 0x473474 ADD	X7, X30, X21,LSL #3

(1347) 0x473478 UBFM	X8, X21, #61, #60

(1347) 0x47347c LDR	Q20, [X30, X8]

(1347) 0x473480 LDR	D21, [X7, #16]

(1347) 0x473484 FMLA	V31.2D, V20.2D, V0.D[0]

(1347) 0x473488 FMADD	D15, D21, D0, D15

(1347) 0x47348c LDR	X0, [X19, #1096]

(1347) 0x473490 STR	Q31, [SP, #144]

(1347) 0x473494 BL	4d57e0

(1347) 0x473498 LDR	Q1, [SP, #144]

(1347) 0x47349c FMOV	D2, D15

(1347) 0x4734a0 LDP	X29, X30, [SP, #32]

(1347) 0x4734a4 LDP	X19, X20, [SP, #48]

(1347) 0x4734a8 STR	Q1, [SP, #240]

(1347) 0x4734ac LDR	D15, [SP, #128]

(1347) 0x4734b0 LDP	X21, X22, [SP, #64]

(1347) 0x4734b4 LDP	X25, X26, [SP, #96]

(1347) 0x4734b8 LDP	D0, D1, [SP, #240]

(1347) 0x4734bc ADD	SP, SP, #272

(1347) 0x4734c0 RET

(1347) 0x4734c4 LDR	X3, [X19, #1040]

(1347) 0x4734c8 CBZ	X3, 4734ec

(1347) 0x4734cc UBFM	X2, X3, #61, #60

(1347) 0x4734d0 LDR	X0, [X19, #1056]

(1347) 0x4734d4 CMP	X2, #8

(1347) 0x4734d8 B.LE	473514

(1347) 0x4734dc BL	403d70

(1347) 0x4734e0 LDR	X3, [X19, #1040]

(1347) 0x4734e4 LDR	X0, [X19, #1056]

(1347) 0x4734e8 B	4732bc

(1347) 0x4734ec MOVI	V31.2D, #0

(1347) 0x4734f0 FMOV	D15, D31

(1347) 0x4734f4 B	47348c

(1347) 0x4734f8 MOVI	V31.2D, #0

(1347) 0x4734fc MOVZ	W7, #0

(1347) 0x473500 FMOV	D15, D31

(1347) 0x473504 B	4733fc

0x473508 LDR	D31, [X4, X5]

0x47350c STR	D31, [X6]

0x473510 B	473178

(1347) 0x473514 B.NE	4732bc

(1347) 0x473518 LDR	D1, [X4, X5]

(1347) 0x47351c STR	D1, [X0]

(1347) 0x473520 B	4732bc

0x473524 HINT	#0

0x473528 HINT	#0

0x47352c HINT	#0

0x473530 HINT	#0

0x473534 HINT	#0

0x473538 HINT	#0

0x47353c HINT	#0

Coverage (%)	Name	Source Location	Module
►49.63+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:183	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►49.21+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:183	exec
○	main._omp_fn.1	stl_vector.h:1131	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:82-91
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155-156
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:82-91
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 4.50 cycles (4.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 50% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 21.67 to 14.08 cycles (1.54x speedup).

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
2% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.67 to 2.50 cycles (8.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 319 bytes.

General properties

nb instructions	129
loop length	516
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	8.50	8.50	8.50	8.50	8.50	8.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50
cycles	4.50	4.50	8.50	8.50	8.50	8.50	8.50	8.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Overall L1	21.67

Vectorization ratios

INT

all	1%
load	0%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

10% of peak load performance is reached (10.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4730e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X25, X0, #520	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W1, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X0, #1096]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
SUB W20, W2, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X21, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STR W20, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W3, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X2, X21, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X1, X4, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X5, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ W3, 4734c4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X20, X19, #648	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X19, #1032	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X23, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W23, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 473178 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X23, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 473508 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403d70 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W3, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D15, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X27, SP, #228	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X28, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19, #840]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W7, #84	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X12, X19, #816	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #220	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, SP, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #211	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, SP, #212	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STRB W7, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (6.3%)
ADD X7, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X28, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP W23, W3, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X12, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D15, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
BL 404030 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W10, #78	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X11, X19, #672	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X28, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, SP, #220	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W22, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X2, SP, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #212	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #211	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W9, W9, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X6, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X19, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STRB W10, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (6.3%)
MADD X15, X6, X13, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X6, [X14, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D15, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X18, X4, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 404030 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W25, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X3, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #211	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X28, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, SP, #220	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, SP, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #212	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D0, D15, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP W23, W25, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X4, X25, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X12, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X28, X4, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W22, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X23, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X26, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X4, [X19, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STRB W22, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (6.3%)
BL 404030 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D31, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D31, [X6]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 473178 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:82-91
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:155-156
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:82-91
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 21.67 to 4.50 cycles (4.81x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

1% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
2% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 21.67 to 2.50 cycles (8.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 224 bytes. The binary function is storing 319 bytes.

General properties

nb instructions	129
loop length	516
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

15.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	4.50	4.50	8.50	8.50	8.50	8.50	8.50	8.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50
cycles	4.50	4.50	8.50	8.50	8.50	8.50	8.50	8.50	2.50	2.50	1.00	1.00	21.67	21.67	21.67	15.50	15.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	15.25
Overall L1	21.67

Vectorization ratios

INT

all	1%
load	0%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	1%
load	0%
store	2%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 21.67 cycles. At this rate:

10% of peak load performance is reached (10.34 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.72 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4730e0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #272	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X25, X0, #520	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W1, [X0, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X0, [X0, #1096]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR D15, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
SUB W20, W2, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X21, X20, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STR W20, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X4, [X19, #256]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W3, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD X2, X21, X0, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
ADD X1, X4, X2,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
UBFM X5, X2, #61, #60	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CBZ W3, 4734c4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x3e4>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X20, X19, #648	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X24, X19, #1032	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X23, [X19, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X22, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP W23, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 473178 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X2, X23, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP X2, #8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (50.0%)
B.EQ 473508 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x428>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403d70 <@plt_start@+0x80>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X6, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR W3, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMOV D15, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X27, SP, #228	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X28, SP, #240	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X19, #840]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W7, #84	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W26, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X12, X19, #816	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X5, SP, #220	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X4, [X19, #568]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, SP, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #211	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X1, SP, #212	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STRB W7, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (6.3%)
ADD X7, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X28, X8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP W23, W3, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X12, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D15, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
BL 404030 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W9, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W10, #78	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ADD X11, X19, #672	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X28, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, SP, #220	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP W22, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X3, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X2, SP, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X14, [SP, #168]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X1, SP, #212	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #211	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W10, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STP W9, W9, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X6, X9, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X13, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X27, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X4, [X19, #696]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X11, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STRB W10, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (6.3%)
MADD X15, X6, X13, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
LDR X6, [X14, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR D15, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
ADD X18, X4, X15,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR XZR, [SP, #240]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X18, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
BL 404030 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W25, [X25, #360]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMOV D0, #-1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
ADD X3, SP, #232	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X0, SP, #211	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR X28, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADD X7, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, SP, #220	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X12, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X2, SP, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X1, SP, #212	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W23, W26, [SP, #220]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STP D0, D15, [SP, #232]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP W23, W25, [SP, #212]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SBFM X4, X25, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X20, [X20, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W26, [SP, #228]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X23, [X12, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X26, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MADD X28, X4, X20, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
LDR W22, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADD X6, X23, X28,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X26, X27, [SP, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X4, [X19, #632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STRB W22, [SP, #211]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (6.3%)
BL 404030 <@plt_start@+0x340>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X3, [X24, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDP X27, X28, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR X0, [X24, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDR D31, [X4, X5]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
STR D31, [X6]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
B 473178 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE8evalGradERNS1_11ParticleSetEi+0x98>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::evalGrad(qmcplusplus::ParticleSet&, int)–	0.36	0.49
▼Loop 1347 - OhmmsVector.h:178-248 - exec–	0.00	0.01
○Loop 1348 - inner_product.hpp:155-155 - exec	0.35	0.48

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code