OV - exec - Function miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector<double, 3u>&)

	Function: miniqmcreference::DiracDeterminantRef<qmcplusplus::DelayedUpdate<double, double> >::ratioG ...	Module: exec	Source: DiracDeterminantRef.cpp:94-118 [...]	Coverage (incl. loops): 0.07% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 82 - 156

--------------------------------------------------------------------------------

82:   for (int i = 0; i < n; i++)

83:     res += a[i] * b[i];

[...]

155:   for (int i = 0; i < n; i++)

156:     res += a[i] * b[i];

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 178 - 248

--------------------------------------------------------------------------------

178:   inline size_t size() const { return nLocal; }

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp: 94 - 118

--------------------------------------------------------------------------------

94: typename DiracDeterminantRef<DU_TYPE>::ValueType DiracDeterminantRef<DU_TYPE>::ratioGrad(ParticleSet& P,

95:                                                                                          int iat,

96:                                                                                          GradType& grad_iat)

97: {

98:   SPOVGLTimer->start();

99:   Phi->evaluate(P, iat, psiV, dpsiV, d2psiV);

100:   SPOVGLTimer->stop();

101:   RatioTimer->start();

102:   const int WorkingIndex = iat - FirstIndex;

103:   UpdateMode             = ORB_PBYP_PARTIAL;

[...]

109:   if (invRow_id != WorkingIndex)

110:   {

111:     invRow_id = WorkingIndex;

112:     updateEng.getInvRow(psiM, WorkingIndex, invRow);

113:   }

114:   curRatio = simd::dot(invRow.data(), psiV.data(), invRow.size());

115:   grad_iat += ((RealType)1.0 / curRatio) * simd::dot(invRow.data(), dpsiV.data(), invRow.size());

116:   RatioTimer->stop();

117:   return curRatio;

118: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 61 - 94

--------------------------------------------------------------------------------

61:   inline typename BinaryReturn<T1, T2, OpMultiply>::Type_t operator()(const T1& a, const T2& b) const

62:   {

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 413 - 453

--------------------------------------------------------------------------------

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

453: 	  else if (_Num == 1)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h: 98 - 113

--------------------------------------------------------------------------------

98:     if (delay_count == 0)

99:     {

100:       // Ainv is fresh, directly access Ainv

101:       std::copy_n(Ainv[rowchanged], invRow.size(), invRow.data());

102:       return;

103:     }

104:     const T cone(1);

105:     const T czero(0);

106:     const int norb     = Ainv.rows();

107:     const int lda_Binv = Binv.cols();

108:     // save Ainv[rowchanged] to invRow

109:     std::copy_n(Ainv[rowchanged], norb, invRow.data());

110:     // multiply V (NxK) Binv(KxK) U(KxN) invRow right to the left

111:     BLAS::gemv('T', norb, delay_count, cone, U.data(), norb, invRow.data(), 1, czero, p.data(), 1);

112:     BLAS::gemv('N', delay_count, delay_count, cone, Binv.data(), lda_Binv, p.data(), 1, czero, Binv[delay_count], 1);

113:     BLAS::gemv('N', norb, delay_count, -cone, V.data(), norb, Binv[delay_count], 1, cone, invRow.data(), 1);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp: 187 - 187

--------------------------------------------------------------------------------

187:     dgemv(trans_in, n, m, alpha, amat, lda, x, incx, beta, y, incy);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h: 77 - 217

--------------------------------------------------------------------------------

77:   inline size_type rows() const { return D1; }

78:   inline size_type cols() const { return D2; }

[...]

214:   inline const Type_t* operator[](size_type i) const { return X.data() + i * D2; }

215:

216:   /// returns a pointer of i-th row, g++ iterator problem

217:   inline Type_t* operator[](size_type i) { return X.data() + i * D2; }

0x471de0 SUB	SP, SP, #224

0x471de4 STP	X29, X30, [SP, #32]

0x471de8 ADD	X29, SP, #32

0x471dec STP	X19, X20, [SP, #48]

0x471df0 ORR	X19, XZR, X0

0x471df4 ADD	X20, X0, #440

0x471df8 STP	X21, X22, [SP, #64]

0x471dfc ORR	W22, WZR, W2

0x471e00 ORR	X21, XZR, X3

0x471e04 STP	X23, X24, [SP, #80]

0x471e08 ADD	X24, X0, #400

0x471e0c ORR	X23, XZR, X1

0x471e10 LDR	X0, [X0, #1128]

0x471e14 BL	4d5540

0x471e18 LDR	X0, [X19, #1136]

0x471e1c ORR	X1, XZR, X23

0x471e20 ORR	X3, XZR, X24

0x471e24 ORR	W2, WZR, W22

0x471e28 ORR	X4, XZR, X20

0x471e2c ADD	X5, X19, #480

0x471e30 LDR	X6, [X0]

0x471e34 LDR	X7, [X6, #24]

0x471e38 BLR	X7

0x471e3c LDR	X0, [X19, #1128]

0x471e40 BL	4d57e0

0x471e44 LDR	X0, [X19, #1096]

0x471e48 BL	4d5540

0x471e4c LDR	W1, [X19, #1144]

0x471e50 MOVZ	W2, #2

0x471e54 LDR	W0, [X19, #1072]

0x471e58 STR	W2, [X19, #12]

0x471e5c SUB	W3, W22, W1

0x471e60 CMP	W0, W3

0x471e64 B.NE	472264

0x471e68 LDR	X9, [X19, #1040]

0x471e6c LDR	X0, [X19, #1056]

(1337) 0x471e70 ORR	W17, WZR, W9

(1337) 0x471e74 LDR	X30, [X24, #24]

(1337) 0x471e78 CMP	W9, #0

(1337) 0x471e7c B.LE	47245c

(1337) 0x471e80 SUB	W24, W9, #1

(1337) 0x471e84 ORR	W7, WZR, W9

(1337) 0x471e88 CMP	W24, #6

(1337) 0x471e8c B.LS	472498

(1337) 0x471e90 UBFM	W3, W9, #3, #31

(1337) 0x471e94 MOVZ	W5, #64

(1337) 0x471e98 MOVI	V26.2D, #0

(1337) 0x471e9c ORR	X1, XZR, X0

(1337) 0x471ea0 ORR	X15, XZR, X30

(1337) 0x471ea4 UMADDL	X16, W3, W5, X0

(1337) 0x471ea8 ORR	V25.16B, V26.16B, V26.16B

(1337) 0x471eac ORR	V24.16B, V26.16B, V26.16B

(1337) 0x471eb0 SUB	X8, X16, X0

(1337) 0x471eb4 ORR	V23.16B, V26.16B, V26.16B

(1337) 0x471eb8 SUB	X11, X8, #64

(1337) 0x471ebc UBFM	X12, X11, #6, #63

(1337) 0x471ec0 ADD	X14, X12, #1

(1337) 0x471ec4 ANDS	X13, X14, #4160

(1337) 0x471ec8 B.EQ	471f54

(1337) 0x471ecc CMP	X13, #1

(1337) 0x471ed0 B.EQ	471f28

(1337) 0x471ed4 CMP	X13, #2

(1337) 0x471ed8 B.EQ	471f04

(1337) 0x471edc LDP	Q4, Q2, [X0, #16]

(1337) 0x471ee0 LDP	Q19, Q5, [X30, #16]

(1337) 0x471ee4 LDR	Q20, [X0, #48]

(1337) 0x471ee8 LDR	Q6, [X30, #48]

(1337) 0x471eec LDR	Q16, [X1], #64

(1337) 0x471ef0 LDR	Q7, [X15], #64

(1337) 0x471ef4 FMLA	V24.2D, V4.2D, V19.2D

(1337) 0x471ef8 FMLA	V25.2D, V2.2D, V5.2D

(1337) 0x471efc FMLA	V23.2D, V16.2D, V7.2D

(1337) 0x471f00 FMLA	V26.2D, V20.2D, V6.2D

(1337) 0x471f04 LDP	Q30, Q22, [X15, #16]

(1337) 0x471f08 LDP	Q17, Q29, [X1, #32]

(1337) 0x471f0c LDP	Q18, Q21, [X1], #64

(1337) 0x471f10 LDR	Q27, [X15, #48]

(1337) 0x471f14 LDR	Q28, [X15], #64

(1337) 0x471f18 FMLA	V25.2D, V17.2D, V22.2D

(1337) 0x471f1c FMLA	V24.2D, V21.2D, V30.2D

(1337) 0x471f20 FMLA	V26.2D, V29.2D, V27.2D

(1337) 0x471f24 FMLA	V23.2D, V18.2D, V28.2D

(1337) 0x471f28 LDP	Q31, Q0, [X15, #16]

(1337) 0x471f2c LDP	Q3, Q1, [X1, #32]

(1337) 0x471f30 LDP	Q4, Q2, [X1], #64

(1337) 0x471f34 LDR	Q19, [X15, #48]

(1337) 0x471f38 LDR	Q5, [X15], #64

(1337) 0x471f3c FMLA	V25.2D, V3.2D, V0.2D

(1337) 0x471f40 FMLA	V24.2D, V2.2D, V31.2D

(1337) 0x471f44 FMLA	V26.2D, V1.2D, V19.2D

(1337) 0x471f48 FMLA	V23.2D, V4.2D, V5.2D

(1337) 0x471f4c CMP	X16, X1

(1337) 0x471f50 B.EQ	472010

  (1340) 0x471f54 ORR	X18, XZR, X1

  (1340) 0x471f58 ORR	X6, XZR, X15

  (1340) 0x471f5c LDP	Q20, Q6, [X1, #16]

  (1340) 0x471f60 ADD	X4, X1, #192

  (1340) 0x471f64 ADD	X23, X15, #192

  (1340) 0x471f68 LDR	Q16, [X18], #64

  (1340) 0x471f6c ADD	X1, X1, #256

  (1340) 0x471f70 LDR	Q7, [X6], #64

  (1340) 0x471f74 LDP	Q30, Q22, [X15, #16]

  (1340) 0x471f78 LDP	Q27, Q28, [X15, #48]

  (1340) 0x471f7c ADD	X22, X18, #64

  (1340) 0x471f80 ADD	X15, X15, #256

  (1340) 0x471f84 LDUR	Q4, [X1, #304]

  (1340) 0x471f88 ADD	X10, X6, #64

  (1340) 0x471f8c FMLA	V23.2D, V16.2D, V7.2D

  (1340) 0x471f90 LDP	Q17, Q29, [X18, #16]

  (1340) 0x471f94 LDP	Q18, Q21, [X6, #16]

  (1340) 0x471f98 FMLA	V24.2D, V20.2D, V30.2D

  (1340) 0x471f9c LDP	Q31, Q0, [X18, #48]

  (1340) 0x471fa0 LDP	Q3, Q2, [X6, #48]

  (1340) 0x471fa4 FMLA	V25.2D, V6.2D, V22.2D

  (1340) 0x471fa8 LDUR	Q20, [X1, #320]

  (1340) 0x471fac FMLA	V26.2D, V4.2D, V27.2D

  (1340) 0x471fb0 LDUR	Q16, [X1, #448]

  (1340) 0x471fb4 LDP	Q1, Q19, [X22, #16]

  (1340) 0x471fb8 FMLA	V24.2D, V17.2D, V18.2D

  (1340) 0x471fbc LDP	Q5, Q7, [X10, #16]

  (1340) 0x471fc0 LDR	Q18, [X10, #48]

  (1340) 0x471fc4 FMLA	V25.2D, V29.2D, V21.2D

  (1340) 0x471fc8 LDR	Q21, [X22, #48]

  (1340) 0x471fcc FMLA	V23.2D, V20.2D, V28.2D

  (1340) 0x471fd0 LDP	Q6, Q30, [X4, #16]

  (1340) 0x471fd4 FMLA	V26.2D, V31.2D, V3.2D

  (1340) 0x471fd8 LDUR	Q29, [X15, #448]

  (1340) 0x471fdc LDP	Q22, Q17, [X23, #16]

  (1340) 0x471fe0 FMLA	V24.2D, V1.2D, V5.2D

  (1340) 0x471fe4 LDR	Q27, [X23, #48]

  (1340) 0x471fe8 LDR	Q28, [X4, #48]

  (1340) 0x471fec FMLA	V25.2D, V19.2D, V7.2D

  (1340) 0x471ff0 FMLA	V23.2D, V0.2D, V2.2D

  (1340) 0x471ff4 FMLA	V26.2D, V21.2D, V18.2D

  (1340) 0x471ff8 FMLA	V24.2D, V6.2D, V22.2D

  (1340) 0x471ffc FMLA	V25.2D, V30.2D, V17.2D

  (1340) 0x472000 FMLA	V23.2D, V16.2D, V29.2D

  (1340) 0x472004 FMLA	V26.2D, V28.2D, V27.2D

  (1340) 0x472008 CMP	X16, X1

  (1340) 0x47200c B.NE	471f54

(1337) 0x472010 AND	W2, W7, #1821

(1337) 0x472014 FADD	V26.2D, V25.2D, V26.2D

(1337) 0x472018 FADD	V23.2D, V23.2D, V24.2D

(1337) 0x47201c FADD	V24.2D, V26.2D, V23.2D

(1337) 0x472020 FADDP	D3, V24.2D

(1337) 0x472024 ANDS	XZR, X7, #4224

(1337) 0x472028 B.EQ	472470

(1337) 0x47202c ORR	W9, WZR, W2

(1337) 0x472030 MOVZ	X16, #0

(1337) 0x472034 DUP	Z2.D, #0

(1337) 0x472038 ADD	X30, X30, X9,LSL #3

(1337) 0x47203c CNTD	X5, ALL

(1337) 0x472040 SUB	W2, W7, W2

(1337) 0x472044 WHILELO	P7.D, WZR, W2

(1337) 0x472048 ADD	X3, X0, X9,LSL #3

  (1338) 0x47204c LD1D	{Z0.D}, P7/Z, [X3, X16,LSL #3]

  (1338) 0x472050 LD1D	{Z1.D}, P7/Z, [X30, X16,LSL #3]

  (1338) 0x472054 ADD	X16, X16, X5

  (1338) 0x472058 FMLA	Z2.D, P7/M, Z0.D, Z1.D

  (1338) 0x47205c WHILELO	P7.D, W16, W2

  (1338) 0x472060 B.NE	47204c

(1337) 0x472064 PTRUE	P0.B, ALL

(1337) 0x472068 FADDV	D19, P0, Z2.D

(1337) 0x47206c FADD	D3, D3, D19

(1337) 0x472070 FMOV	D4, #1.0000000

(1337) 0x472074 LDR	X20, [X20, #24]

(1337) 0x472078 FDIV	D31, D4, D3

(1337) 0x47207c STR	D3, [X19, #1080]

(1337) 0x472080 DUP	V27.2D, V31.D[0]

(1337) 0x472084 CMP	W24, #2

(1337) 0x472088 B.LS	472488

(1337) 0x47208c UBFM	W8, W7, #2, #31

(1337) 0x472090 MOVZ	W11, #96

(1337) 0x472094 MOVI	V28.2D, #0

(1337) 0x472098 ORR	X13, XZR, X20

(1337) 0x47209c ORR	X1, XZR, X0

(1337) 0x4720a0 UMADDL	X12, W8, W11, X20

(1337) 0x4720a4 ORR	V29.16B, V28.16B, V28.16B

(1337) 0x4720a8 ORR	V30.16B, V28.16B, V28.16B

(1337) 0x4720ac SUB	X14, X12, X20

(1337) 0x4720b0 ORR	V22.16B, V28.16B, V28.16B

(1337) 0x4720b4 ORR	V21.16B, V28.16B, V28.16B

(1337) 0x4720b8 ORR	V20.16B, V28.16B, V28.16B

(1337) 0x4720bc TBZ	W14, #5, 472100

(1337) 0x4720c0 LDP	Q17, Q5, [X0]

(1337) 0x4720c4 ADD	X1, X0, #32

(1337) 0x4720c8 LDP	Q7, Q6, [X20, #16]

(1337) 0x4720cc LDP	Q18, Q26, [X20, #48]

(1337) 0x4720d0 LDR	Q24, [X20, #80]

(1337) 0x4720d4 LDR	Q23, [X13], #96

(1337) 0x4720d8 FMLA	V21.2D, V7.2D, V17.2D

(1337) 0x4720dc FMLA	V22.2D, V6.2D, V17.D[1]

(1337) 0x4720e0 FMLA	V30.2D, V18.2D, V5.D[0]

(1337) 0x4720e4 FMLA	V29.2D, V5.2D, V26.2D

(1337) 0x4720e8 FMLA	V20.2D, V23.2D, V17.D[0]

(1337) 0x4720ec FMLA	V28.2D, V24.2D, V5.D[1]

(1337) 0x4720f0 CMP	X12, X13

(1337) 0x4720f4 B.EQ	472170

(1337) 0x4720f8 HINT	#0

(1337) 0x4720fc HINT	#0

  (1339) 0x472100 ORR	X15, XZR, X13

  (1339) 0x472104 LDP	Q25, Q0, [X1]

  (1339) 0x472108 ORR	X18, XZR, X1

  (1339) 0x47210c ADD	X1, X1, #64

  (1339) 0x472110 LDR	Q16, [X15], #96

  (1339) 0x472114 LDP	Q1, Q2, [X13, #16]

  (1339) 0x472118 LDP	Q19, Q4, [X13, #48]

  (1339) 0x47211c LDP	Q3, Q5, [X13, #80]

  (1339) 0x472120 ADD	X13, X13, #192

  (1339) 0x472124 FMLA	V20.2D, V16.2D, V25.D[0]

  (1339) 0x472128 LDP	Q17, Q6, [X15, #16]

  (1339) 0x47212c LDP	Q7, Q26, [X15, #48]

  (1339) 0x472130 FMLA	V21.2D, V1.2D, V25.2D

  (1339) 0x472134 LDUR	Q18, [X1, #480]

  (1339) 0x472138 LDR	Q24, [X18, #48]

  (1339) 0x47213c FMLA	V22.2D, V2.2D, V25.D[1]

  (1339) 0x472140 LDR	Q23, [X15, #80]

  (1339) 0x472144 FMLA	V30.2D, V19.2D, V0.D[0]

  (1339) 0x472148 FMLA	V29.2D, V0.2D, V4.2D

  (1339) 0x47214c FMLA	V28.2D, V3.2D, V0.D[1]

  (1339) 0x472150 FMLA	V20.2D, V5.2D, V18.D[0]

  (1339) 0x472154 FMLA	V21.2D, V17.2D, V18.2D

  (1339) 0x472158 FMLA	V22.2D, V6.2D, V18.D[1]

  (1339) 0x47215c FMLA	V30.2D, V7.2D, V24.D[0]

  (1339) 0x472160 FMLA	V29.2D, V24.2D, V26.2D

  (1339) 0x472164 FMLA	V28.2D, V23.2D, V24.D[1]

  (1339) 0x472168 CMP	X12, X13

  (1339) 0x47216c B.NE	472100

(1337) 0x472170 EXT	V25.16B, V21.16B, V22.16B, #8

(1337) 0x472174 EXT	V0.16B, V29.16B, V28.16B, #8

(1337) 0x472178 MOV	D22, V22.D[1]

(1337) 0x47217c MOV	D28, V28.D[1]

(1337) 0x472180 FADD	V20.2D, V20.2D, V30.2D

(1337) 0x472184 FADD	D21, D29, D21

(1337) 0x472188 FADD	V30.2D, V25.2D, V0.2D

(1337) 0x47218c FADD	D29, D22, D28

(1337) 0x472190 FADD	V16.2D, V30.2D, V20.2D

(1337) 0x472194 FADD	D26, D29, D21

(1337) 0x472198 ANDS	XZR, X7, #4160

(1337) 0x47219c B.EQ	472220

(1337) 0x4721a0 AND	W24, W7, #1886

(1337) 0x4721a4 MOVZ	W7, #24

(1337) 0x4721a8 ORR	W6, WZR, W24

(1337) 0x4721ac UBFM	X23, X6, #61, #60

(1337) 0x4721b0 ADD	W4, W24, #1

(1337) 0x4721b4 UMADDL	X22, W24, W7, XZR

(1337) 0x4721b8 LDR	D1, [X0, X23]

(1337) 0x4721bc ADD	X10, X20, X22

(1337) 0x4721c0 LDR	Q2, [X20, X22]

(1337) 0x4721c4 LDR	D19, [X10, #16]

(1337) 0x4721c8 FMLA	V16.2D, V2.2D, V1.D[0]

(1337) 0x4721cc FMADD	D26, D19, D1, D26

(1337) 0x4721d0 CMP	W17, W4

(1337) 0x4721d4 B.LE	472220

(1337) 0x4721d8 ADD	X9, X22, #24

(1337) 0x4721dc ADD	X5, X0, X23

(1337) 0x4721e0 ADD	X30, X20, X9

(1337) 0x4721e4 ADD	W2, W24, #2

(1337) 0x4721e8 LDR	Q4, [X20, X9]

(1337) 0x4721ec LDR	D3, [X5, #8]

(1337) 0x4721f0 LDR	D5, [X30, #16]

(1337) 0x4721f4 FMLA	V16.2D, V4.2D, V3.D[0]

(1337) 0x4721f8 FMADD	D26, D3, D5, D26

(1337) 0x4721fc CMP	W17, W2

(1337) 0x472200 B.LE	472220

(1337) 0x472204 ADD	X17, X22, #48

(1337) 0x472208 LDR	D7, [X5, #16]

(1337) 0x47220c ADD	X3, X20, X17

(1337) 0x472210 LDR	Q17, [X20, X17]

(1337) 0x472214 LDR	D6, [X3, #16]

(1337) 0x472218 FMLA	V16.2D, V17.2D, V7.D[0]

(1337) 0x47221c FMADD	D26, D7, D6, D26

(1337) 0x472220 FMUL	D31, D26, D31

(1337) 0x472224 FMUL	V27.2D, V27.2D, V16.2D

(1337) 0x472228 LDR	Q16, [X21]

(1337) 0x47222c LDR	D23, [X21, #16]

(1337) 0x472230 LDR	X0, [X19, #1096]

(1337) 0x472234 FADD	V18.2D, V16.2D, V27.2D

(1337) 0x472238 FADD	D24, D23, D31

(1337) 0x47223c STR	Q18, [X21]

(1337) 0x472240 STR	D24, [X21, #16]

(1337) 0x472244 BL	4d57e0

(1337) 0x472248 LDR	D0, [X19, #1080]

(1337) 0x47224c LDP	X29, X30, [SP, #32]

(1337) 0x472250 LDP	X21, X22, [SP, #64]

(1337) 0x472254 LDP	X23, X24, [SP, #80]

(1337) 0x472258 LDP	X19, X20, [SP, #48]

(1337) 0x47225c ADD	SP, SP, #224

(1337) 0x472260 RET

(1337) 0x472264 STP	X27, X28, [SP, #112]

(1337) 0x472268 SBFM	X4, X3, #0, #31

(1337) 0x47226c ADD	X28, X19, #520

(1337) 0x472270 LDR	X8, [X19, #216]

(1337) 0x472274 STR	W3, [X19, #1072]

(1337) 0x472278 LDR	X5, [X19, #256]

(1337) 0x47227c LDR	W12, [X28, #360]

(1337) 0x472280 MADD	X9, X4, X8, XZR

(1337) 0x472284 ADD	X1, X5, X9,LSL #3

(1337) 0x472288 UBFM	X10, X9, #61, #60

(1337) 0x47228c CBZ	W12, 47242c

(1337) 0x472290 STP	X25, X26, [SP, #96]

(1337) 0x472294 ADD	X27, X19, #1032

(1337) 0x472298 ADD	X25, X19, #648

(1337) 0x47229c LDR	X11, [X25, #8]

(1337) 0x4722a0 LDR	X23, [X19, #208]

(1337) 0x4722a4 LDR	X6, [X27, #24]

(1337) 0x4722a8 STR	D15, [SP, #128]

(1337) 0x4722ac STR	X11, [SP, #144]

(1337) 0x4722b0 CMP	W23, #0

(1337) 0x4722b4 B.LE	4722d4

(1337) 0x4722b8 UBFM	X2, X23, #61, #31

(1337) 0x4722bc CMP	X2, #8

(1337) 0x4722c0 B.EQ	4724a4

(1337) 0x4722c4 ORR	X0, XZR, X6

(1337) 0x4722c8 BL	403d70

(1337) 0x4722cc LDR	X6, [X27, #24]

(1337) 0x4722d0 LDR	W12, [X28, #360]

(1337) 0x4722d4 FMOV	D15, #1.0000000

(1337) 0x4722d8 ADD	X26, SP, #204

(1337) 0x4722dc ADD	X13, SP, #216

(1337) 0x4722e0 STR	XZR, [SP, #216]

(1337) 0x4722e4 LDR	X16, [X19, #840]

(1337) 0x4722e8 MOVZ	W22, #1

(1337) 0x4722ec MOVZ	W15, #84

(1337) 0x4722f0 ADD	X14, X19, #816

(1337) 0x4722f4 ADD	X7, SP, #200

(1337) 0x4722f8 LDR	X4, [X19, #568]

(1337) 0x4722fc ADD	X5, SP, #196

(1337) 0x472300 ADD	X2, SP, #192

(1337) 0x472304 ADD	X0, SP, #187

(1337) 0x472308 ADD	X1, SP, #188

(1337) 0x47230c STR	X26, [SP, #16]

(1337) 0x472310 ADD	X3, SP, #208

(1337) 0x472314 STR	X14, [SP, #168]

(1337) 0x472318 STP	X13, X16, [SP]

(1337) 0x47231c STRB	W15, [SP, #187]

(1337) 0x472320 STP	W23, W12, [SP, #188]

(1337) 0x472324 STP	W23, W22, [SP, #196]

(1337) 0x472328 STR	W22, [SP, #204]

(1337) 0x47232c STR	D15, [SP, #208]

(1337) 0x472330 BL	404030

(1337) 0x472334 LDR	W10, [X28, #360]

(1337) 0x472338 ADD	X4, SP, #216

(1337) 0x47233c MOVZ	W6, #78

(1337) 0x472340 ADD	X18, X19, #672

(1337) 0x472344 ADD	X7, SP, #200

(1337) 0x472348 STR	W22, [SP, #204]

(1337) 0x47234c LDR	W9, [SP, #144]

(1337) 0x472350 ADD	X5, SP, #196

(1337) 0x472354 ADD	X3, SP, #208

(1337) 0x472358 STR	X4, [SP]

(1337) 0x47235c ADD	X2, SP, #192

(1337) 0x472360 ADD	X1, SP, #188

(1337) 0x472364 LDR	X11, [SP, #168]

(1337) 0x472368 ADD	X0, SP, #187

(1337) 0x47236c STP	W10, W10, [SP, #188]

(1337) 0x472370 SBFM	X8, X10, #0, #31

(1337) 0x472374 STR	W6, [SP, #156]

(1337) 0x472378 STP	W9, W22, [SP, #196]

(1337) 0x47237c LDR	X12, [X25, #8]

(1337) 0x472380 STR	X26, [SP, #16]

(1337) 0x472384 LDR	X4, [X19, #696]

(1337) 0x472388 STRB	W6, [SP, #187]

(1337) 0x47238c LDR	X6, [X11, #24]

(1337) 0x472390 MADD	X14, X8, X12, XZR

(1337) 0x472394 STR	X18, [SP, #160]

(1337) 0x472398 STR	D15, [SP, #208]

(1337) 0x47239c STR	XZR, [SP, #216]

(1337) 0x4723a0 ADD	X13, X4, X14,LSL #3

(1337) 0x4723a4 STR	X13, [SP, #8]

(1337) 0x4723a8 BL	404030

(1337) 0x4723ac LDR	W28, [X28, #360]

(1337) 0x4723b0 FMOV	D0, #-1.0000000

(1337) 0x4723b4 ADD	X15, SP, #216

(1337) 0x4723b8 ADD	X0, SP, #187

(1337) 0x4723bc STP	W23, W22, [SP, #196]

(1337) 0x4723c0 ADD	X7, SP, #200

(1337) 0x4723c4 ADD	X5, SP, #196

(1337) 0x4723c8 LDR	X4, [SP, #160]

(1337) 0x4723cc ADD	X3, SP, #208

(1337) 0x4723d0 ADD	X2, SP, #192

(1337) 0x4723d4 STR	X15, [SP]

(1337) 0x4723d8 ADD	X1, SP, #188

(1337) 0x4723dc STP	D0, D15, [SP, #208]

(1337) 0x4723e0 STP	W23, W28, [SP, #188]

(1337) 0x4723e4 SBFM	X18, X28, #0, #31

(1337) 0x4723e8 LDR	X25, [X25, #8]

(1337) 0x4723ec STR	W22, [SP, #204]

(1337) 0x4723f0 LDR	X23, [X4, #24]

(1337) 0x4723f4 LDR	X10, [X27, #24]

(1337) 0x4723f8 MADD	X22, X18, X25, XZR

(1337) 0x4723fc LDR	W6, [SP, #156]

(1337) 0x472400 STP	X10, X26, [SP, #8]

(1337) 0x472404 LDR	X4, [X19, #632]

(1337) 0x472408 STRB	W6, [SP, #187]

(1337) 0x47240c ADD	X6, X23, X22,LSL #3

(1337) 0x472410 BL	404030

(1337) 0x472414 LDR	X9, [X27, #8]

(1337) 0x472418 LDP	X25, X26, [SP, #96]

(1337) 0x47241c LDR	X0, [X27, #24]

(1337) 0x472420 LDP	X27, X28, [SP, #112]

(1337) 0x472424 LDR	D15, [SP, #128]

(1337) 0x472428 B	471e70

(1337) 0x47242c LDR	X9, [X19, #1040]

(1337) 0x472430 CBZ	X9, 472458

(1337) 0x472434 UBFM	X2, X9, #61, #60

(1337) 0x472438 LDR	X0, [X19, #1056]

(1337) 0x47243c CMP	X2, #8

(1337) 0x472440 B.LE	4724b0

(1337) 0x472444 BL	403d70

(1337) 0x472448 LDR	X9, [X19, #1040]

(1337) 0x47244c LDP	X27, X28, [SP, #112]

(1337) 0x472450 LDR	X0, [X19, #1056]

(1337) 0x472454 B	471e70

(1337) 0x472458 LDP	X27, X28, [SP, #112]

(1337) 0x47245c ADRP	X20,

(1337) 0x472460 STR	XZR, [X19, #1080]

(1337) 0x472464 LDR	Q27, [X20, #2784]

(1337) 0x472468 FMOV	D31, D27

(1337) 0x47246c B	472228

(1337) 0x472470 FMOV	D25, #1.0000000

(1337) 0x472474 LDR	X20, [X20, #24]

(1337) 0x472478 STR	D3, [X19, #1080]

(1337) 0x47247c FDIV	D31, D25, D3

(1337) 0x472480 DUP	V27.2D, V31.D[0]

(1337) 0x472484 B	47208c

(1337) 0x472488 MOVI	V16.2D, #0

(1337) 0x47248c MOVZ	W24, #0

(1337) 0x472490 FMOV	D26, D16

(1337) 0x472494 B	4721a4

(1337) 0x472498 MOVI	D3, #0

(1337) 0x47249c MOVZ	W2, #0

(1337) 0x4724a0 B	47202c

(1337) 0x4724a4 LDR	D31, [X5, X10]

(1337) 0x4724a8 STR	D31, [X6]

(1337) 0x4724ac B	4722d4

(1337) 0x4724b0 B.EQ	4724bc

(1337) 0x4724b4 LDP	X27, X28, [SP, #112]

(1337) 0x4724b8 B	471e70

(1337) 0x4724bc LDR	D1, [X5, X10]

(1337) 0x4724c0 STR	D1, [X0]

(1337) 0x4724c4 LDP	X27, X28, [SP, #112]

(1337) 0x4724c8 B	471e70

0x4724cc HINT	#0

0x4724d0 HINT	#0

0x4724d4 HINT	#0

0x4724d8 HINT	#0

0x4724dc HINT	#0

Coverage (%)	Name	Source Location	Module
►53.78+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►44.72+	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:94-118
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:94-103,109-118
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Your function is not vectorized. Only 53% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 5.17 to 4.21 cycles (1.23x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.00 cycles (2.58x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50
cycles	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

14% of peak load performance is reached (13.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 471de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X20, X0, #440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR W22, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X0, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W2, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X4, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X19, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4d57e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W0, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W2, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W3, W22, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 472264 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	DiracDeterminantRef.cpp:94-118
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:82-83,155-156
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:178,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DiracDeterminantRef.cpp:94-103,109-118
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:61-63,94
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:413,451-453
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/DelayedUpdate.h:98-113
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/BLAS.hpp:187
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsMatrix.h:77-78,214-217

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 5.17 to 2.00 cycles (2.58x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 72 bytes. The binary function is storing 68 bytes.

General properties

nb instructions	41
loop length	164
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50
cycles	2.50	2.50	3.33	3.33	3.33	3.33	3.33	3.33	0.00	0.00	0.00	0.00	5.17	4.83	5.00	2.50	2.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.50
Overall L1	5.17

Vectorization ratios

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.17 cycles. At this rate:

14% of peak load performance is reached (13.94 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
27% of peak store performance is reached (13.16 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 471de0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #224	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #32	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD X20, X0, #440	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR W22, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X21, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X24, X0, #400	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X0, [X0, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ORR X1, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X3, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W2, WZR, W22	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X4, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X5, X19, #480	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X6, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X7, [X6, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
BLR X7	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4d57e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X19, #1096]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X19, #1144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MOVZ W2, #2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR W0, [X19, #1072]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR W2, [X19, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB W3, W22, W1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W0, W3	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.NE 472264 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE9ratioGradERNS1_11ParticleSetEiRNS1_10TinyVectorIdLj3EEE+0x484>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X9, [X19, #1040]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X0, [X19, #1056]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::DiracDeterminantRef >::ratioGrad(qmcplusplus::ParticleSet&, int, qmcplusplus::TinyVector&)–	0.07	0.10
▼Loop 1337 - OhmmsVector.h:178-248 - exec–	0.00	0.01
○Loop 1339 - inner_product.hpp:155-155 - exec	0.04	0.05
○Loop 1340 - inner_product.hpp:82-83 - exec	0.03	0.04
○Loop 1338 - inner_product.hpp:82-83 - exec	0.00	0.00

Report Configuration

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code