OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&, qmcplusplus::Vector<qmcplusplus::TinyVector<double, 3u>, std::allocator<qmcplusplus::TinyVector<double, 3u> > >&, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:203-230 [...]	Coverage (incl. loops): 10.32% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 187 - 286

--------------------------------------------------------------------------------

187:   x -= spline_m->x_grid.start;

188:   y -= spline_m->y_grid.start;

189:   z -= spline_m->z_grid.start;

190:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

191:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

192:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

199:   const intptr_t ys = spline_m->y_stride;

200:   const intptr_t zs = spline_m->z_stride;

201:

202:   const size_t out_offset = spline_m->num_splines;

203:

204:   T* restrict gx = grads;

205:   T* restrict gy = grads + out_offset;

206:   T* restrict gz = grads + 2 * out_offset;

207:

208:   T* restrict hxx = hess;

209:   T* restrict hxy = hess + out_offset;

210:   T* restrict hxz = hess + 2 * out_offset;

211:   T* restrict hyy = hess + 3 * out_offset;

212:   T* restrict hyz = hess + 4 * out_offset;

213:   T* restrict hzz = hess + 5 * out_offset;

214:

215:   std::fill(vals, vals + num_splines, T());

[...]

226:   for (int i = 0; i < 4; i++)

227:     for (int j = 0; j < 4; j++)

228:     {

229:       const T* restrict coefs    = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

230:       const T* restrict coefszs  = coefs + zs;

231:       const T* restrict coefs2zs = coefs + 2 * zs;

232:       const T* restrict coefs3zs = coefs + 3 * zs;

233:

234:       const T pre20 = d2a[i] * b[j];

235:       const T pre10 = da[i] * b[j];

236:       const T pre00 = a[i] * b[j];

237:       const T pre11 = da[i] * db[j];

238:       const T pre01 = a[i] * db[j];

239:       const T pre02 = a[i] * d2b[j];

240:

241:       const int iSplitPoint = num_splines;

242:       for (int n = 0; n < iSplitPoint; n++)

243:       {

244:         T coefsv    = coefs[n];

245:         T coefsvzs  = coefszs[n];

246:         T coefsv2zs = coefs2zs[n];

247:         T coefsv3zs = coefs3zs[n];

248:

249:         T sum0 = c[0] * coefsv + c[1] * coefsvzs + c[2] * coefsv2zs + c[3] * coefsv3zs;

250:         T sum1 = dc[0] * coefsv + dc[1] * coefsvzs + dc[2] * coefsv2zs + dc[3] * coefsv3zs;

251:         T sum2 = d2c[0] * coefsv + d2c[1] * coefsvzs + d2c[2] * coefsv2zs + d2c[3] * coefsv3zs;

252:

253:         hxx[n] += pre20 * sum0;

254:         hxy[n] += pre11 * sum0;

255:         hxz[n] += pre10 * sum1;

256:         hyy[n] += pre02 * sum0;

257:         hyz[n] += pre01 * sum1;

258:         hzz[n] += pre00 * sum2;

259:         gx[n] += pre10 * sum0;

260:         gy[n] += pre01 * sum0;

261:         gz[n] += pre00 * sum1;

262:         vals[n] += pre00 * sum0;

[...]

269:   const T dxx   = dxInv * dxInv;

270:   const T dyy   = dyInv * dyInv;

271:   const T dzz   = dzInv * dzInv;

272:   const T dxy   = dxInv * dyInv;

273:   const T dxz   = dxInv * dzInv;

274:   const T dyz   = dyInv * dzInv;

275:

276:   for (int n = 0; n < num_splines; n++)

277:   {

278:     gx[n] *= dxInv;

279:     gy[n] *= dyInv;

280:     gz[n] *= dzInv;

281:     hxx[n] *= dxx;

282:     hyy[n] *= dyy;

283:     hzz[n] *= dzz;

284:     hxy[n] *= dxy;

285:     hxz[n] *= dxz;

286:     hyz[n] *= dyz;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 173

--------------------------------------------------------------------------------

170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

171:         val_dot[i] = T1(0.0);

172:       else

173:         val_dot[i] -= std::floor(val_dot[i]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h: 213 - 213

--------------------------------------------------------------------------------

213:   inline Type_t operator[](unsigned int i) const { return X[i]; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 1131 - 1263

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

--------------------------------------------------------------------------------

150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 203 - 230

--------------------------------------------------------------------------------

203:     ScopedTimer local_timer(timer);

204:

205:     auto u = Lattice.toUnit_floor(P.activeR(iat));

206:     for (int i = 0; i < nBlocks; ++i)

207:       MultiBsplineEvalRef::evaluate_vgh(einsplines[i], u[0], u[1], u[2], psi[i].data(), grad[i].data(), hess[i].data(),

208:                                         nSplinesPerBlock);

209:   }

210:

211:   inline void evaluate(const ParticleSet& P,

[...]

219:     for (int i = 0; i < nBlocks; ++i)

220:     {

221:       // in real simulation, phase needs to be applied. Here just fake computation

222:       const int first = i * nBlocks;

223:       for (int j = first; j < std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize); j++)

224:       {

225:         psi_v[j]   = psi[i][j - first];

226:         dpsi_v[j]  = grad[i][j - first];

227:         d2psi_v[j] = hess[i].data(0)[j - first];

228:       }

229:     }

230:   }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 229

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 66

--------------------------------------------------------------------------------

53:   if (x < 0)

54:   {

55:     ind = 0;

56:     dx  = T(0);

57:   }

58:   else

59:   {

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

64:     {

65:       ind = nmax;

66:       dx  = T(1) - std::numeric_limits<T>::epsilon();

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

--------------------------------------------------------------------------------

143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 68 - 79

--------------------------------------------------------------------------------

68:     a[0]   = ((A00 * tx + A01) * tx + A02) * tx + A03;

69:     a[1]   = ((A10 * tx + A11) * tx + A12) * tx + A13;

70:     a[2]   = ((A20 * tx + A21) * tx + A22) * tx + A23;

71:     a[3]   = ((A30 * tx + A31) * tx + A32) * tx + A33;

72:     da[0]  = (dA01 * tx + dA02) * tx + dA03;

73:     da[1]  = (dA11 * tx + dA12) * tx + dA13;

74:     da[2]  = (dA21 * tx + dA22) * tx + dA23;

75:     da[3]  = (dA31 * tx + dA32) * tx + dA33;

76:     d2a[0] = d2A02 * tx + d2A03;

77:     d2a[1] = d2A12 * tx + d2A13;

78:     d2a[2] = d2A22 * tx + d2A23;

79:     d2a[3] = d2A32 * tx + d2A33;

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 238 - 952

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 231 - 271

--------------------------------------------------------------------------------

231:   inline const AoSElement_t operator[](size_t i) const { return AoSElement_t(myData + i, nGhosts); }

[...]

265:   inline T* data() { return myData; }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 145 - 145

--------------------------------------------------------------------------------

145:       X[i] = base[i * offset];

0x45e9a0 SUB	SP, SP, #624

0x45e9a4 STP	X29, X30, [SP]

0x45e9a8 ADD	X29, SP, #0

0x45e9ac STP	X19, X20, [SP, #16]

0x45e9b0 ORR	X20, XZR, X0

0x45e9b4 ORR	W19, WZR, W2

0x45e9b8 STP	X21, X22, [SP, #32]

0x45e9bc ORR	X22, XZR, X4

0x45e9c0 ORR	X21, XZR, X5

0x45e9c4 STP	X23, X24, [SP, #48]

0x45e9c8 ORR	X23, XZR, X3

0x45e9cc STP	X25, X26, [SP, #64]

0x45e9d0 ORR	X25, XZR, X1

0x45e9d4 STP	X27, X28, [SP, #80]

0x45e9d8 LDR	X24, [X0, #856]

0x45e9dc ORR	X0, XZR, X24

0x45e9e0 BL	4d5540

0x45e9e4 LDR	W0, [X25, #292]

0x45e9e8 ADD	X3, X25, #296

0x45e9ec CMP	W19, W0

0x45e9f0 B.EQ	45ea00

0x45e9f4 LDR	X2, [X25, #64]

0x45e9f8 MOVZ	W1, #24

0x45e9fc SMADDL	X3, W19, W1, X2

0x45ea00 ADD	X4, X20, #216

0x45ea04 LDP	D23, D31, [X3]

0x45ea08 MOVI	D27, #0

0x45ea0c MOVZ	X5, #48304

0x45ea10 LDP	D29, D30, [X4, #24]

0x45ea14 FMOV	D28, X5

0x45ea18 LDR	D25, [X20, #216]

0x45ea1c LDR	D26, [X3, #16]

0x45ea20 FMUL	D0, D31, D29

0x45ea24 LDP	D20, D4, [X4, #40]

0x45ea28 FMUL	D1, D31, D30

0x45ea2c LDP	D19, D21, [X4, #8]

0x45ea30 LDP	D6, D22, [X4, #56]

0x45ea34 FMADD	D3, D23, D25, D0

0x45ea38 FMUL	D7, D31, D20

0x45ea3c LDR	W9, [X20, #48]

0x45ea40 FMADD	D2, D23, D19, D1

0x45ea44 FMADD	D5, D26, D4, D3

0x45ea48 FRINTM	D24, D5

0x45ea4c FMADD	D23, D23, D21, D7

0x45ea50 FMADD	D16, D26, D6, D2

0x45ea54 FRINTM	D17, D16

0x45ea58 FMADD	D31, D26, D22, D23

0x45ea5c FRINTM	D0, D31

0x45ea60 FCMPE	D5, D27

0x45ea64 FSUB	D18, D5, S24

0x45ea68 FSUB	D30, D16, S17

0x45ea6c FCCMPE	D5, D28, #4, #4

0x45ea70 CSINC	W6, WZR, WZR, #13

0x45ea74 CMP	W6, #0

0x45ea78 FCSEL	D29, D18, D27, #0

0x45ea7c FCMPE	D16, D27

0x45ea80 FCCMPE	D16, D28, #4, #4

0x45ea84 CSINC	W7, WZR, WZR, #13

0x45ea88 CMP	W7, #0

0x45ea8c FCSEL	D1, D30, D27, #0

0x45ea90 FCMPE	D31, D27

0x45ea94 STP	D29, D1, [SP, #344]

0x45ea98 FCCMPE	D31, D28, #4, #4

0x45ea9c FSUB	D28, D31, S0

0x45eaa0 CSINC	W8, WZR, WZR, #13

0x45eaa4 CMP	W8, #0

0x45eaa8 FCSEL	D27, D28, D27, #0

0x45eaac STR	D27, [SP, #360]

0x45eab0 CMP	W9, #0

0x45eab4 B.LE	45f304

0x45eab8 ORR	X10, XZR, #3840

0x45eabc STP	D8, D9, [SP, #96]

0x45eac0 ORR	X12, XZR, #3840

0x45eac4 MOVK	X10, #16325

0x45eac8 STP	D10, D11, [SP, #112]

0x45eacc MOVK	X12, #16357

0x45ead0 STP	D12, D13, [SP, #128]

0x45ead4 MOVZ	X6, #24

0x45ead8 FMOV	D1, X10

0x45eadc STP	D14, D15, [SP, #144]

0x45eae0 LDR	W30, [X20, #64]

0x45eae4 STR	X12, [SP, #208]

0x45eae8 LDR	X5, [X20, #760]

0x45eaec ADD	X11, X5, W9,UXTW #3

0x45eaf0 STP	X24, X20, [SP, #392]

0x45eaf4 SBFM	X15, X30, #0, #31

0x45eaf8 SBFM	X2, X30, #61, #31

0x45eafc STP	X23, X22, [SP, #408]

0x45eb00 LDR	X13, [X20, #784]

0x45eb04 STR	X11, [SP, #368]

0x45eb08 LDR	X14, [X20, #808]

0x45eb0c STR	W30, [SP, #380]

0x45eb10 LDR	X16, [X20, #832]

0x45eb14 STR	X13, [SP, #200]

0x45eb18 STR	X15, [SP, #384]

0x45eb1c STR	X14, [SP, #328]

0x45eb20 STR	X21, [SP, #424]

0x45eb24 STR	X16, [SP, #336]

    (1152) 0x45eb28 LDR	X9, [X5]

    (1152) 0x45eb2c LDR	D11, [SP, #344]

    (1152) 0x45eb30 LDR	D14, [SP, #352]

    (1152) 0x45eb34 LDR	D9, [X9, #40]

    (1152) 0x45eb38 LDP	D22, D8, [X9, #72]

    (1152) 0x45eb3c LDR	D10, [X9, #120]

    (1152) 0x45eb40 FSUB	D12, D11, S9

    (1152) 0x45eb44 LDR	D19, [SP, #360]

    (1152) 0x45eb48 LDR	X17, [SP, #200]

    (1152) 0x45eb4c FSUB	D15, D14, S8

    (1152) 0x45eb50 LDR	X18, [SP, #328]

    (1152) 0x45eb54 FMUL	D13, D12, D22

    (1152) 0x45eb58 LDR	X20, [SP, #336]

    (1152) 0x45eb5c FSUB	D7, D19, S10

    (1152) 0x45eb60 LDR	X28, [X17]

    (1152) 0x45eb64 LDR	X21, [X18, X6]

    (1152) 0x45eb68 FCMPE	D13, #0

    (1152) 0x45eb6c LDR	X20, [X20, X6]

    (1152) 0x45eb70 B.MI	45f5c8

    (1152) 0x45eb74 LDR	W23, [X9, #56]

    (1152) 0x45eb78 FCVTZS	W22, D13

    (1152) 0x45eb7c SUB	W10, W23, #1

    (1152) 0x45eb80 CMP	W10, W22

    (1152) 0x45eb84 B.LT	45f668

    (1152) 0x45eb88 ORR	X24, XZR, #3840

    (1152) 0x45eb8c FRINTZ	D2, D13

    (1152) 0x45eb90 FSUB	D29, D13, S2

    (1152) 0x45eb94 FMOV	D3, #0.5000000

    (1152) 0x45eb98 ORR	W10, WZR, W22

    (1152) 0x45eb9c MOVK	X24, #49093

    (1152) 0x45eba0 FMOV	D4, #-1.0000000

    (1152) 0x45eba4 FMOV	D21, #-2.0000000

    (1152) 0x45eba8 FMOV	D26, #1.5000000

    (1152) 0x45ebac FMOV	D24, #1.0000000

    (1152) 0x45ebb0 FMOV	D16, X24

    (1152) 0x45ebb4 FMOV	D5, #-0.5000000

    (1152) 0x45ebb8 FMOV	D20, #3.0000000

    (1152) 0x45ebbc FSUB	D25, D2, S13

    (1152) 0x45ebc0 LDR	D13, [SP, #208]

    (1152) 0x45ebc4 FMADD	D17, D29, D3, D4

    (1152) 0x45ebc8 FMSUB	D6, D29, D3, D3

    (1152) 0x45ebcc FMADD	D18, D29, D26, D21

    (1152) 0x45ebd0 FMSUB	D0, D29, D26, D24

    (1152) 0x45ebd4 FMADD	D27, D29, D20, D21

    (1152) 0x45ebd8 FMUL	D23, D29, D29

    (1152) 0x45ebdc FMADD	D28, D29, D6, D3

    (1152) 0x45ebe0 FMUL	D8, D29, D16

    (1152) 0x45ebe4 FADD	D30, D25, D24

    (1152) 0x45ebe8 FMADD	D9, D29, D0, D3

    (1152) 0x45ebec FMSUB	D24, D29, D20, D24

    (1152) 0x45ebf0 FMUL	D21, D23, D3

    (1152) 0x45ebf4 FMUL	D31, D29, D17

    (1152) 0x45ebf8 FMADD	D6, D29, D28, D1

    (1152) 0x45ebfc FADD	D10, D8, D3

    (1152) 0x45ec00 FMUL	D11, D29, D18

    (1152) 0x45ec04 STR	D27, [SP, #192]

    (1152) 0x45ec08 FNMUL	D4, D23, D8

    (1152) 0x45ec0c STR	D30, [SP, #184]

    (1152) 0x45ec10 FMADD	D2, D29, D31, D13

    (1152) 0x45ec14 FADD	D14, D31, D3

    (1152) 0x45ec18 STR	D9, [SP, #176]

    (1152) 0x45ec1c FMADD	D12, D29, D10, D5

    (1152) 0x45ec20 STR	D11, [SP, #168]

    (1152) 0x45ec24 FMADD	D5, D29, D12, D1

    (1152) 0x45ec28 FNEG	D27, D14

    (1152) 0x45ec2c LDR	D25, [X9, #112]

    (1152) 0x45ec30 FMUL	D15, D15, D25

    (1152) 0x45ec34 FCMPE	D15, #0

    (1152) 0x45ec38 B.MI	45f590

    (1152) 0x45ec3c LDR	W8, [X9, #96]

    (1152) 0x45ec40 FCVTZS	W12, D15

    (1152) 0x45ec44 SUB	W8, W8, #1

    (1152) 0x45ec48 CMP	W8, W12

    (1152) 0x45ec4c B.LT	45f600

    (1152) 0x45ec50 ORR	X30, XZR, #3840

    (1152) 0x45ec54 FRINTZ	D20, D15

    (1152) 0x45ec58 FSUB	D30, D15, S20

    (1152) 0x45ec5c FMOV	D18, #0.5000000

    (1152) 0x45ec60 ORR	W8, WZR, W12

    (1152) 0x45ec64 MOVK	X30, #49093

    (1152) 0x45ec68 FMOV	D0, #-1.0000000

    (1152) 0x45ec6c FMOV	D16, #1.5000000

    (1152) 0x45ec70 FMOV	D28, #-2.0000000

    (1152) 0x45ec74 FMOV	D26, #1.0000000

    (1152) 0x45ec78 FMOV	D17, X30

    (1152) 0x45ec7c FSUB	D9, D20, S15

    (1152) 0x45ec80 FMOV	D23, #3.0000000

    (1152) 0x45ec84 FMOV	D8, #-0.5000000

    (1152) 0x45ec88 FMADD	D31, D30, D18, D0

    (1152) 0x45ec8c FMADD	D3, D30, D16, D28

    (1152) 0x45ec90 FMSUB	D10, D30, D18, D18

    (1152) 0x45ec94 FMSUB	D14, D30, D16, D26

    (1152) 0x45ec98 FMUL	D11, D30, D30

    (1152) 0x45ec9c FMADD	D13, D30, D23, D28

    (1152) 0x45eca0 FADD	D12, D9, D26

    (1152) 0x45eca4 LDR	D9, [SP, #208]

    (1152) 0x45eca8 FMUL	D15, D30, D17

    (1152) 0x45ecac FMADD	D20, D30, D10, D18

    (1152) 0x45ecb0 FMADD	D19, D30, D14, D18

    (1152) 0x45ecb4 FMSUB	D26, D30, D23, D26

    (1152) 0x45ecb8 FMUL	D23, D11, D18

    (1152) 0x45ecbc FMUL	D0, D30, D31

    (1152) 0x45ecc0 FMADD	D20, D30, D20, D1

    (1152) 0x45ecc4 FADD	D16, D15, D18

    (1152) 0x45ecc8 FNMUL	D17, D11, D15

    (1152) 0x45eccc STR	D13, [SP, #248]

    (1152) 0x45ecd0 FADD	D18, D0, D18

    (1152) 0x45ecd4 STP	D19, D12, [SP, #232]

    (1152) 0x45ecd8 FMADD	D28, D30, D16, D8

    (1152) 0x45ecdc FMUL	D8, D30, D3

    (1152) 0x45ece0 STR	D17, [SP, #216]

    (1152) 0x45ece4 FMADD	D3, D30, D0, D9

    (1152) 0x45ece8 FMADD	D19, D30, D28, D1

    (1152) 0x45ecec FNEG	D28, D18

    (1152) 0x45ecf0 STR	D8, [SP, #224]

    (1152) 0x45ecf4 LDR	D31, [X9, #152]

    (1152) 0x45ecf8 FMUL	D7, D7, D31

    (1152) 0x45ecfc FCMPE	D7, #0

    (1152) 0x45ed00 B.MI	45f558

    (1152) 0x45ed04 LDR	W26, [X9, #136]

    (1152) 0x45ed08 FCVTZS	W24, D7

    (1152) 0x45ed0c SUB	W27, W26, #1

    (1152) 0x45ed10 CMP	W27, W24

    (1152) 0x45ed14 B.LT	45f6cc

    (1152) 0x45ed18 FRINTZ	D13, D7

    (1152) 0x45ed1c FSUB	D15, D7, S13

    (1152) 0x45ed20 FMOV	D12, #0.5000000

    (1152) 0x45ed24 ORR	X25, XZR, #3840

    (1152) 0x45ed28 SBFM	X13, X24, #0, #31

    (1152) 0x45ed2c FMOV	D14, #1.0000000

    (1152) 0x45ed30 FMOV	D8, #-1.0000000

    (1152) 0x45ed34 MOVK	X25, #49093

    (1152) 0x45ed38 FMOV	D17, #1.5000000

    (1152) 0x45ed3c FMOV	D10, #-2.0000000

    (1152) 0x45ed40 FSUB	D16, D13, S7

    (1152) 0x45ed44 FMOV	D9, X25

    (1152) 0x45ed48 FMOV	D13, #3.0000000

    (1152) 0x45ed4c FMOV	D0, #-0.5000000

    (1152) 0x45ed50 FMADD	D7, D15, D12, D8

    (1152) 0x45ed54 FMSUB	D8, D15, D17, D14

    (1152) 0x45ed58 FMADD	D17, D15, D17, D10

    (1152) 0x45ed5c FMUL	D18, D15, D15

    (1152) 0x45ed60 FMSUB	D11, D15, D12, D12

    (1152) 0x45ed64 FMADD	D10, D15, D13, D10

    (1152) 0x45ed68 FADD	D16, D16, D14

    (1152) 0x45ed6c FMADD	D8, D15, D8, D12

    (1152) 0x45ed70 FMSUB	D14, D15, D13, D14

    (1152) 0x45ed74 FMUL	D13, D15, D7

    (1152) 0x45ed78 LDR	D7, [SP, #208]

    (1152) 0x45ed7c STR	D17, [SP, #256]

    (1152) 0x45ed80 FMUL	D17, D15, D9

    (1152) 0x45ed84 FMADD	D9, D15, D11, D12

    (1152) 0x45ed88 FMUL	D11, D18, D12

    (1152) 0x45ed8c FMADD	D7, D15, D13, D7

    (1152) 0x45ed90 FSUB	D13, D0, S13

    (1152) 0x45ed94 FADD	D12, D17, D12

    (1152) 0x45ed98 FNMUL	D18, D18, D17

    (1152) 0x45ed9c LDR	D17, [SP, #256]

    (1152) 0x45eda0 FMADD	D9, D15, D9, D1

    (1152) 0x45eda4 FMADD	D0, D15, D12, D0

    (1152) 0x45eda8 FMUL	D17, D15, D17

    (1152) 0x45edac FMADD	D12, D15, D0, D1

    (1152) 0x45edb0 LDRSW	X14, [X9, #232]

    (1152) 0x45edb4 STP	D5, D2, [SP, #432]

    (1152) 0x45edb8 LDR	D2, [SP, #176]

    (1152) 0x45edbc STP	D6, D4, [SP, #448]

    (1152) 0x45edc0 LDR	D6, [SP, #184]

    (1152) 0x45edc4 STR	D27, [SP, #496]

    (1152) 0x45edc8 ADD	X22, X20, X14,LSL #4

    (1152) 0x45edcc UBFM	X4, X14, #61, #60

    (1152) 0x45edd0 LDR	D27, [SP, #168]

    (1152) 0x45edd4 ADD	X25, X21, X14,LSL #3

    (1152) 0x45edd8 STR	D21, [SP, #520]

    (1152) 0x45eddc ADD	X23, X22, X14,LSL #4

    (1152) 0x45ede0 LDP	D5, D21, [SP, #232]

    (1152) 0x45ede4 ADD	X24, X22, X14,LSL #3

    (1152) 0x45ede8 STR	D28, [SP, #528]

    (1152) 0x45edec ADD	X27, X23, X14,LSL #3

    (1152) 0x45edf0 LDR	D28, [SP, #192]

    (1152) 0x45edf4 ADD	X26, X21, X14,LSL #4

    (1152) 0x45edf8 STR	D24, [SP, #576]

    (1152) 0x45edfc ADD	X19, X20, X14,LSL #3

    (1152) 0x45ee00 LDP	D4, D24, [SP, #216]

    (1152) 0x45ee04 STR	D29, [SP, #584]

    (1152) 0x45ee08 LDR	D29, [SP, #248]

    (1152) 0x45ee0c STP	D19, D3, [SP, #464]

    (1152) 0x45ee10 STR	D20, [SP, #480]

    (1152) 0x45ee14 STR	D27, [SP, #504]

    (1152) 0x45ee18 STR	D4, [SP, #488]

    (1152) 0x45ee1c STR	D2, [SP, #512]

    (1152) 0x45ee20 STR	D24, [SP, #536]

    (1152) 0x45ee24 STR	D5, [SP, #544]

    (1152) 0x45ee28 STR	D23, [SP, #552]

    (1152) 0x45ee2c STR	D6, [SP, #560]

    (1152) 0x45ee30 STR	D28, [SP, #568]

    (1152) 0x45ee34 STR	D21, [SP, #592]

    (1152) 0x45ee38 STR	D29, [SP, #600]

    (1152) 0x45ee3c STR	D26, [SP, #608]

    (1152) 0x45ee40 STR	D30, [SP, #616]

    (1152) 0x45ee44 LDP	X11, X15, [X9, #16]

    (1152) 0x45ee48 LDR	X3, [X9, #32]

    (1152) 0x45ee4c CBZ	X2, 45ef54

    (1152) 0x45ee50 MOVZ	W1, #0

    (1152) 0x45ee54 ORR	X0, XZR, X28

    (1152) 0x45ee58 STP	X2, X9, [SP, #168]

    (1152) 0x45ee5c STR	D22, [SP, #184]

    (1152) 0x45ee60 STR	W10, [SP, #192]

    (1152) 0x45ee64 STR	D25, [SP, #216]

    (1152) 0x45ee68 STR	W8, [SP, #224]

    (1152) 0x45ee6c STR	D31, [SP, #232]

    (1152) 0x45ee70 STP	X11, X15, [SP, #240]

    (1152) 0x45ee74 STP	X3, X4, [SP, #256]

    (1152) 0x45ee78 STR	X13, [SP, #272]

    (1152) 0x45ee7c STP	D7, D18, [SP, #280]

    (1152) 0x45ee80 STP	D17, D16, [SP, #296]

    (1152) 0x45ee84 STP	X6, X5, [SP, #312]

    (1152) 0x45ee88 BL	403ea0

    (1152) 0x45ee8c LDR	X2, [SP, #168]

    (1152) 0x45ee90 MOVZ	W1, #0

    (1152) 0x45ee94 ORR	X0, XZR, X21

    (1152) 0x45ee98 BL	403ea0

    (1152) 0x45ee9c LDR	X2, [SP, #168]

    (1152) 0x45eea0 MOVZ	W1, #0

    (1152) 0x45eea4 ORR	X0, XZR, X25

    (1152) 0x45eea8 BL	403ea0

    (1152) 0x45eeac LDR	X2, [SP, #168]

    (1152) 0x45eeb0 MOVZ	W1, #0

    (1152) 0x45eeb4 ORR	X0, XZR, X26

    (1152) 0x45eeb8 BL	403ea0

    (1152) 0x45eebc LDR	X2, [SP, #168]

    (1152) 0x45eec0 MOVZ	W1, #0

    (1152) 0x45eec4 ORR	X0, XZR, X20

    (1152) 0x45eec8 BL	403ea0

    (1152) 0x45eecc LDR	X2, [SP, #168]

    (1152) 0x45eed0 MOVZ	W1, #0

    (1152) 0x45eed4 ORR	X0, XZR, X19

    (1152) 0x45eed8 BL	403ea0

    (1152) 0x45eedc LDR	X2, [SP, #168]

    (1152) 0x45eee0 MOVZ	W1, #0

    (1152) 0x45eee4 ORR	X0, XZR, X22

    (1152) 0x45eee8 BL	403ea0

    (1152) 0x45eeec LDR	X2, [SP, #168]

    (1152) 0x45eef0 MOVZ	W1, #0

    (1152) 0x45eef4 ORR	X0, XZR, X24

    (1152) 0x45eef8 BL	403ea0

    (1152) 0x45eefc LDR	X2, [SP, #168]

    (1152) 0x45ef00 MOVZ	W1, #0

    (1152) 0x45ef04 ORR	X0, XZR, X23

    (1152) 0x45ef08 BL	403ea0

    (1152) 0x45ef0c LDR	X2, [SP, #168]

    (1152) 0x45ef10 ORR	X0, XZR, X27

    (1152) 0x45ef14 MOVZ	W1, #0

    (1152) 0x45ef18 BL	403ea0

    (1152) 0x45ef1c ADRP	X5,

    (1152) 0x45ef20 LDR	D22, [SP, #184]

    (1152) 0x45ef24 LDP	X2, X9, [SP, #168]

    (1152) 0x45ef28 LDP	X11, X15, [SP, #240]

    (1152) 0x45ef2c LDP	X3, X4, [SP, #256]

    (1152) 0x45ef30 LDR	D25, [SP, #216]

    (1152) 0x45ef34 LDR	D31, [SP, #232]

    (1152) 0x45ef38 LDP	D7, D18, [SP, #280]

    (1152) 0x45ef3c LDP	D17, D16, [SP, #296]

    (1152) 0x45ef40 LDR	X13, [SP, #272]

    (1152) 0x45ef44 LDR	D1, [X5, #2976]

    (1152) 0x45ef48 LDP	X6, X5, [SP, #312]

    (1152) 0x45ef4c LDR	W10, [SP, #192]

    (1152) 0x45ef50 LDR	W8, [SP, #224]

    (1152) 0x45ef54 MADD	X17, X3, X13, XZR

    (1152) 0x45ef58 LDR	W16, [SP, #380]

    (1152) 0x45ef5c LDR	X9, [X9, #8]

    (1152) 0x45ef60 CMP	W16, #0

    (1152) 0x45ef64 B.LE	45f73c

    (1152) 0x45ef68 SBFM	X18, X8, #0, #31

    (1152) 0x45ef6c SBFM	X7, X10, #0, #31

    (1152) 0x45ef70 ADD	X30, X3, X3,LSL #1

    (1152) 0x45ef74 STP	D22, D25, [SP, #216]

    (1152) 0x45ef78 SUB	X16, XZR, X3,LSL #3

    (1152) 0x45ef7c UBFM	X10, X15, #61, #60

    (1152) 0x45ef80 MOVZ	X12, #1

    (1152) 0x45ef84 STP	X4, X6, [SP, #232]

    (1152) 0x45ef88 MADD	X1, X18, X15, XZR

    (1152) 0x45ef8c ADD	X14, SP, #528

    (1152) 0x45ef90 ADD	X15, SP, #464

    (1152) 0x45ef94 MADD	X0, X7, X11, X17

    (1152) 0x45ef98 ADD	X13, SP, #592

    (1152) 0x45ef9c ADD	X17, SP, #560

    (1152) 0x45efa0 ADD	X18, SP, #496

    (1152) 0x45efa4 STR	X5, [SP, #248]

    (1152) 0x45efa8 ADD	X7, X1, X3,LSL #1

    (1152) 0x45efac ADD	X8, X3, X1

    (1152) 0x45efb0 ADD	X3, X30, X1

    (1152) 0x45efb4 ADD	X1, X9, X8,LSL #3

    (1152) 0x45efb8 ADD	X30, SP, #432

    (1152) 0x45efbc ADD	X7, X9, X7,LSL #3

    (1152) 0x45efc0 ADD	X9, X9, X3,LSL #3

    (1152) 0x45efc4 STP	X7, X1, [SP, #184]

    (1152) 0x45efc8 STP	X11, X9, [SP, #168]

      (1156) 0x45efcc ADD	X6, X30, X12,LSL #3

      (1156) 0x45efd0 MOVZ	X7, #1

      (1156) 0x45efd4 ADD	X5, X17, X12,LSL #3

      (1156) 0x45efd8 LDR	X1, [SP, #176]

      (1156) 0x45efdc ADD	X4, X18, X12,LSL #3

      (1156) 0x45efe0 LDR	X8, [SP, #184]

      (1156) 0x45efe4 LDR	X11, [SP, #192]

      (1156) 0x45efe8 LDUR	D5, [X6, #504]

      (1156) 0x45efec LDUR	D3, [X5, #504]

      (1156) 0x45eff0 ADD	X5, X8, X0,LSL #3

      (1156) 0x45eff4 ADD	X3, X11, X0,LSL #3

      (1156) 0x45eff8 LDUR	D4, [X4, #504]

      (1156) 0x45effc ADD	X4, X1, X0,LSL #3

        (1155) 0x45f000 ADD	X11, X15, X7,LSL #3

        (1155) 0x45f004 MOVZ	X1, #0

        (1155) 0x45f008 ADD	X6, X3, X16

        (1155) 0x45f00c ADD	X9, X14, X7,LSL #3

        (1155) 0x45f010 ADD	X8, X13, X7,LSL #3

        (1155) 0x45f014 LDUR	D26, [X11, #504]

        (1155) 0x45f018 LDUR	D22, [X8, #504]

        (1155) 0x45f01c LDUR	D25, [X9, #504]

        (1155) 0x45f020 FMUL	D6, D3, D26

        (1155) 0x45f024 FMUL	D21, D26, D4

        (1155) 0x45f028 FMUL	D23, D26, D5

        (1155) 0x45f02c FMUL	D20, D5, D22

        (1155) 0x45f030 FMUL	D19, D4, D25

        (1155) 0x45f034 FMUL	D22, D5, D25

        (1155) 0x45f038 HINT	#0

        (1155) 0x45f03c HINT	#0

          (1154) 0x45f040 LDR	D27, [X3, X1]

          (1154) 0x45f044 LDR	D29, [X4, X1]

          (1154) 0x45f048 LDR	D0, [X6, X1]

          (1154) 0x45f04c LDR	D26, [X5, X1]

          (1154) 0x45f050 FMUL	D30, D27, D7

          (1154) 0x45f054 FMUL	D24, D27, D17

          (1154) 0x45f058 FMUL	D27, D27, D10

          (1154) 0x45f05c FMUL	D2, D29, D18

          (1154) 0x45f060 LDR	D25, [X20, X1]

          (1154) 0x45f064 FMUL	D28, D29, D11

          (1154) 0x45f068 FMUL	D29, D29, D15

          (1154) 0x45f06c FMADD	D30, D0, D12, D30

          (1154) 0x45f070 FMADD	D24, D0, D13, D24

          (1154) 0x45f074 FMADD	D27, D0, D16, D27

          (1154) 0x45f078 LDR	D0, [X21, X1]

          (1154) 0x45f07c FMADD	D2, D26, D9, D2

          (1154) 0x45f080 FMADD	D28, D26, D8, D28

          (1154) 0x45f084 FMADD	D29, D26, D14, D29

          (1154) 0x45f088 LDR	D26, [X28, X1]

          (1154) 0x45f08c FADD	D30, D30, D2

          (1154) 0x45f090 FADD	D24, D28, D24

          (1154) 0x45f094 FADD	D2, D27, D29

          (1154) 0x45f098 FMADD	D25, D6, D30, D25

          (1154) 0x45f09c FMADD	D27, D21, D30, D0

          (1154) 0x45f0a0 FMADD	D28, D23, D30, D26

          (1154) 0x45f0a4 STR	D25, [X20, X1]

          (1154) 0x45f0a8 LDR	D29, [X19, X1]

          (1154) 0x45f0ac STR	D27, [X21, X1]

          (1154) 0x45f0b0 LDR	D0, [X25, X1]

          (1154) 0x45f0b4 STR	D28, [X28, X1]

          (1154) 0x45f0b8 FMADD	D25, D19, D30, D29

          (1154) 0x45f0bc FMADD	D26, D22, D30, D0

          (1154) 0x45f0c0 STR	D25, [X19, X1]

          (1154) 0x45f0c4 LDR	D27, [X22, X1]

          (1154) 0x45f0c8 STR	D26, [X25, X1]

          (1154) 0x45f0cc LDR	D28, [X26, X1]

          (1154) 0x45f0d0 FMADD	D29, D21, D24, D27

          (1154) 0x45f0d4 FMADD	D0, D23, D24, D28

          (1154) 0x45f0d8 STR	D29, [X22, X1]

          (1154) 0x45f0dc LDR	D25, [X24, X1]

          (1154) 0x45f0e0 STR	D0, [X26, X1]

          (1154) 0x45f0e4 FMADD	D30, D20, D30, D25

          (1154) 0x45f0e8 STR	D30, [X24, X1]

          (1154) 0x45f0ec LDR	D26, [X23, X1]

          (1154) 0x45f0f0 FMADD	D24, D22, D24, D26

          (1154) 0x45f0f4 STR	D24, [X23, X1]

          (1154) 0x45f0f8 LDR	D27, [X27, X1]

          (1154) 0x45f0fc FMADD	D2, D23, D2, D27

          (1154) 0x45f100 STR	D2, [X27, X1]

          (1154) 0x45f104 ADD	X1, X1, #8

          (1154) 0x45f108 CMP	X2, X1

          (1154) 0x45f10c B.NE	45f040

        (1155) 0x45f110 ADD	X7, X7, #1

        (1155) 0x45f114 ADD	X3, X3, X10

        (1155) 0x45f118 ADD	X5, X5, X10

        (1155) 0x45f11c ADD	X4, X4, X10

        (1155) 0x45f120 CMP	X7, #5

        (1155) 0x45f124 B.NE	45f000

      (1156) 0x45f128 LDR	X7, [SP, #168]

      (1156) 0x45f12c ADD	X12, X12, #1

      (1156) 0x45f130 ADD	X0, X0, X7

      (1156) 0x45f134 CMP	X12, #5

      (1156) 0x45f138 B.NE	45efcc

    (1152) 0x45f13c LDP	D22, D25, [SP, #216]

    (1152) 0x45f140 LDP	X4, X6, [SP, #232]

    (1152) 0x45f144 LDR	X5, [SP, #248]

    (1152) 0x45f148 FMUL	D3, D22, D22

    (1152) 0x45f14c FMUL	D4, D25, D25

    (1152) 0x45f150 MOVZ	X3, #0

    (1152) 0x45f154 FMUL	D5, D31, D31

    (1152) 0x45f158 FMUL	D7, D22, D25

    (1152) 0x45f15c FMUL	D8, D22, D31

    (1152) 0x45f160 FMUL	D9, D25, D31

    (1152) 0x45f164 TBZ	W2, #3, 45f1e0

    (1152) 0x45f168 LDR	D10, [X20]

    (1152) 0x45f16c MOVZ	X3, #8

    (1152) 0x45f170 LDR	D12, [X21]

    (1152) 0x45f174 FMUL	D11, D10, D3

    (1152) 0x45f178 FMUL	D13, D12, D22

    (1152) 0x45f17c STR	D11, [X20]

    (1152) 0x45f180 LDR	D14, [X22, X4]

    (1152) 0x45f184 STR	D13, [X21]

    (1152) 0x45f188 LDR	D28, [X21, X4]

    (1152) 0x45f18c FMUL	D15, D14, D4

    (1152) 0x45f190 FMUL	D29, D28, D25

    (1152) 0x45f194 STR	D15, [X22, X4]

    (1152) 0x45f198 LDR	D16, [X23, X4]

    (1152) 0x45f19c STR	D29, [X21, X4]

    (1152) 0x45f1a0 LDR	D0, [X25, X4]

    (1152) 0x45f1a4 FMUL	D17, D16, D5

    (1152) 0x45f1a8 FMUL	D30, D0, D31

    (1152) 0x45f1ac STR	D17, [X23, X4]

    (1152) 0x45f1b0 LDR	D18, [X20, X4]

    (1152) 0x45f1b4 STR	D30, [X25, X4]

    (1152) 0x45f1b8 FMUL	D20, D18, D7

    (1152) 0x45f1bc STR	D20, [X20, X4]

    (1152) 0x45f1c0 LDR	D19, [X19, X4]

    (1152) 0x45f1c4 FMUL	D6, D19, D8

    (1152) 0x45f1c8 STR	D6, [X19, X4]

    (1152) 0x45f1cc LDR	D21, [X24, X4]

    (1152) 0x45f1d0 FMUL	D23, D21, D9

    (1152) 0x45f1d4 STR	D23, [X24, X4]

    (1152) 0x45f1d8 CMP	X2, X3

    (1152) 0x45f1dc B.EQ	45f2c8

      (1150) 0x45f1e0 LDR	D26, [X20, X3]

      (1150) 0x45f1e4 ADD	X10, X3, #8

      (1150) 0x45f1e8 LDR	D24, [X21, X3]

      (1150) 0x45f1ec FMUL	D27, D26, D3

      (1150) 0x45f1f0 FMUL	D2, D24, D22

      (1150) 0x45f1f4 STR	D27, [X20, X3]

      (1150) 0x45f1f8 LDR	D10, [X24, X3]

      (1150) 0x45f1fc STR	D2, [X21, X3]

      (1150) 0x45f200 LDR	D11, [X25, X3]

      (1150) 0x45f204 FMUL	D12, D10, D4

      (1150) 0x45f208 FMUL	D13, D11, D25

      (1150) 0x45f20c STR	D12, [X24, X3]

      (1150) 0x45f210 LDR	D14, [X27, X3]

      (1150) 0x45f214 STR	D13, [X25, X3]

      (1150) 0x45f218 LDR	D15, [X26, X3]

      (1150) 0x45f21c FMUL	D16, D14, D5

      (1150) 0x45f220 FMUL	D17, D15, D31

      (1150) 0x45f224 STR	D16, [X27, X3]

      (1150) 0x45f228 LDR	D18, [X19, X3]

      (1150) 0x45f22c STR	D17, [X26, X3]

      (1150) 0x45f230 LDR	D20, [X21, X10]

      (1150) 0x45f234 FMUL	D19, D18, D7

      (1150) 0x45f238 FMUL	D6, D20, D22

      (1150) 0x45f23c STR	D19, [X19, X3]

      (1150) 0x45f240 LDR	D21, [X22, X3]

      (1150) 0x45f244 STR	D6, [X21, X10]

      (1150) 0x45f248 LDR	D23, [X25, X10]

      (1150) 0x45f24c FMUL	D28, D21, D8

      (1150) 0x45f250 FMUL	D29, D23, D25

      (1150) 0x45f254 STR	D28, [X22, X3]

      (1150) 0x45f258 LDR	D0, [X23, X3]

      (1150) 0x45f25c STR	D29, [X25, X10]

      (1150) 0x45f260 LDR	D26, [X26, X10]

      (1150) 0x45f264 FMUL	D30, D0, D9

      (1150) 0x45f268 FMUL	D24, D26, D31

      (1150) 0x45f26c STR	D30, [X23, X3]

      (1150) 0x45f270 ADD	X3, X10, #8

      (1150) 0x45f274 LDR	D27, [X20, X10]

      (1150) 0x45f278 STR	D24, [X26, X10]

      (1150) 0x45f27c FMUL	D2, D27, D3

      (1150) 0x45f280 STR	D2, [X20, X10]

      (1150) 0x45f284 LDR	D10, [X24, X10]

      (1150) 0x45f288 FMUL	D11, D10, D4

      (1150) 0x45f28c STR	D11, [X24, X10]

      (1150) 0x45f290 LDR	D12, [X27, X10]

      (1150) 0x45f294 FMUL	D13, D12, D5

      (1150) 0x45f298 STR	D13, [X27, X10]

      (1150) 0x45f29c LDR	D14, [X19, X10]

      (1150) 0x45f2a0 FMUL	D15, D14, D7

      (1150) 0x45f2a4 STR	D15, [X19, X10]

      (1150) 0x45f2a8 LDR	D16, [X22, X10]

      (1150) 0x45f2ac FMUL	D17, D16, D8

      (1150) 0x45f2b0 STR	D17, [X22, X10]

      (1150) 0x45f2b4 LDR	D18, [X23, X10]

      (1150) 0x45f2b8 FMUL	D20, D18, D9

      (1150) 0x45f2bc STR	D20, [X23, X10]

      (1150) 0x45f2c0 CMP	X2, X3

      (1150) 0x45f2c4 B.NE	45f1e0

    (1152) 0x45f2c8 LDR	X13, [SP, #200]

    (1152) 0x45f2cc ADD	X5, X5, #8

    (1152) 0x45f2d0 ADD	X6, X6, #40

    (1152) 0x45f2d4 LDR	X15, [SP, #368]

    (1152) 0x45f2d8 ADD	X14, X13, #24

    (1152) 0x45f2dc STR	X14, [SP, #200]

    (1152) 0x45f2e0 CMP	X15, X5

    (1152) 0x45f2e4 B.NE	45eb28

(1153) 0x45f2e8 LDP	D8, D9, [SP, #96]

(1153) 0x45f2ec LDP	X24, X20, [SP, #392]

(1153) 0x45f2f0 LDP	X23, X22, [SP, #408]

(1153) 0x45f2f4 LDP	D10, D11, [SP, #112]

(1153) 0x45f2f8 LDP	D12, D13, [SP, #128]

(1153) 0x45f2fc LDP	D14, D15, [SP, #144]

(1153) 0x45f300 LDR	X21, [SP, #424]

(1153) 0x45f304 ORR	X0, XZR, X24

(1153) 0x45f308 BL	4d57e0

(1153) 0x45f30c LDR	W24, [X20, #48]

(1153) 0x45f310 CMP	W24, #0

(1153) 0x45f314 B.LE	45f538

(1153) 0x45f318 LDR	W27, [X20, #64]

(1153) 0x45f31c MOVZ	W18, #24

(1153) 0x45f320 MOVZ	X2, #0

(1153) 0x45f324 MOVZ	X17, #0

(1153) 0x45f328 MOVZ	X16, #0

(1153) 0x45f32c LDR	W19, [X20, #8]

(1153) 0x45f330 UMADDL	X18, W24, W18, XZR

(1153) 0x45f334 UBFM	X28, X24, #61, #31

(1153) 0x45f338 MOVZ	X15, #0

(1153) 0x45f33c MOVZ	W14, #0

(1153) 0x45f340 STR	X2, [SP, #168]

(1153) 0x45f344 ORR	W4, WZR, W27

  (1157) 0x45f348 CMP	W4, W19

  (1157) 0x45f34c CSEL	W25, W4, W19, #13

  (1157) 0x45f350 CMP	W14, W25

  (1157) 0x45f354 B.GE	45f510

  (1157) 0x45f358 LDR	X11, [X20, #808]

  (1157) 0x45f35c SUB	W25, W25, W14

  (1157) 0x45f360 MOVZ	X0, #0

  (1157) 0x45f364 ANDS	X26, X25, #4160

  (1157) 0x45f368 LDR	X9, [X20, #832]

  (1157) 0x45f36c LDR	X3, [X21, #24]

  (1157) 0x45f370 ADD	X8, X11, X16

  (1157) 0x45f374 LDR	X5, [X22, #24]

  (1157) 0x45f378 ADD	X1, X9, X16

  (1157) 0x45f37c LDR	X6, [X23, #24]

  (1157) 0x45f380 LDR	X2, [SP, #168]

  (1157) 0x45f384 LDR	X30, [X20, #784]

  (1157) 0x45f388 LDRSW	X7, [X8, #8]

  (1157) 0x45f38c ADD	X13, X6, X2

  (1157) 0x45f390 ADD	X11, X3, X2

  (1157) 0x45f394 LDR	X8, [X8, #24]

  (1157) 0x45f398 LDR	X10, [X30, X15]

  (1157) 0x45f39c UBFM	X2, X7, #60, #59

  (1157) 0x45f3a0 UBFM	X30, X7, #61, #60

  (1157) 0x45f3a4 LDR	X9, [X1, #24]

  (1157) 0x45f3a8 ADD	X1, X5, X17

  (1157) 0x45f3ac ADD	X12, X8, X7,LSL #3

  (1157) 0x45f3b0 ADD	X7, X8, X7,LSL #4

  (1157) 0x45f3b4 B.EQ	45f458

  (1157) 0x45f3b8 CMP	X26, #1

  (1157) 0x45f3bc B.EQ	45f424

  (1157) 0x45f3c0 CMP	X26, #2

  (1157) 0x45f3c4 B.EQ	45f3f8

  (1157) 0x45f3c8 LDR	D1, [X10]

  (1157) 0x45f3cc MOVZ	X0, #1

  (1157) 0x45f3d0 ADD	X1, X1, #24

  (1157) 0x45f3d4 LDR	X26, [SP, #168]

  (1157) 0x45f3d8 STR	D1, [X6, X26]

  (1157) 0x45f3dc LDR	D25, [X8]

  (1157) 0x45f3e0 LDR	D31, [X8, X30]

  (1157) 0x45f3e4 LDR	D22, [X8, X2]

  (1157) 0x45f3e8 STR	D25, [X5, X17]

  (1157) 0x45f3ec STP	D31, D22, [X1, #1008]

  (1157) 0x45f3f0 LDR	D3, [X9]

  (1157) 0x45f3f4 STR	D3, [X3, X26]

  (1157) 0x45f3f8 LDR	D4, [X10, X0,LSL #3]

  (1157) 0x45f3fc ADD	X1, X1, #24

  (1157) 0x45f400 STR	D4, [X13, X0,LSL #3]

  (1157) 0x45f404 LDR	D5, [X8, X0,LSL #3]

  (1157) 0x45f408 LDR	D7, [X12, X0,LSL #3]

  (1157) 0x45f40c LDR	D19, [X7, X0,LSL #3]

  (1157) 0x45f410 STP	D5, D7, [X1, #1000]

  (1157) 0x45f414 STUR	D19, [X1, #504]

  (1157) 0x45f418 LDR	D6, [X9, X0,LSL #3]

  (1157) 0x45f41c STR	D6, [X11, X0,LSL #3]

  (1157) 0x45f420 ADD	X0, X0, #1

  (1157) 0x45f424 LDR	D21, [X10, X0,LSL #3]

  (1157) 0x45f428 ADD	X1, X1, #24

  (1157) 0x45f42c STR	D21, [X13, X0,LSL #3]

  (1157) 0x45f430 LDR	D23, [X8, X0,LSL #3]

  (1157) 0x45f434 LDR	D28, [X12, X0,LSL #3]

  (1157) 0x45f438 LDR	D29, [X7, X0,LSL #3]

  (1157) 0x45f43c STP	D23, D28, [X1, #1000]

  (1157) 0x45f440 STUR	D29, [X1, #504]

  (1157) 0x45f444 LDR	D0, [X9, X0,LSL #3]

  (1157) 0x45f448 STR	D0, [X11, X0,LSL #3]

  (1157) 0x45f44c ADD	X0, X0, #1

  (1157) 0x45f450 CMP	X25, X0

  (1157) 0x45f454 B.EQ	45f510

    (1158) 0x45f458 LDR	D26, [X10, X0,LSL #3]

    (1158) 0x45f45c ADD	X2, X0, #1

    (1158) 0x45f460 ADD	X30, X1, #24

    (1158) 0x45f464 ADD	X5, X0, #2

    (1158) 0x45f468 ADD	X26, X1, #48

    (1158) 0x45f46c ADD	X3, X0, #3

    (1158) 0x45f470 ADD	X6, X1, #72

    (1158) 0x45f474 ADD	X1, X1, #96

    (1158) 0x45f478 STR	D26, [X13, X0,LSL #3]

    (1158) 0x45f47c LDR	D30, [X8, X0,LSL #3]

    (1158) 0x45f480 LDR	D24, [X12, X0,LSL #3]

    (1158) 0x45f484 LDR	D27, [X7, X0,LSL #3]

    (1158) 0x45f488 STP	D30, D24, [X1, #928]

    (1158) 0x45f48c STUR	D27, [X1, #432]

    (1158) 0x45f490 LDR	D2, [X9, X0,LSL #3]

    (1158) 0x45f494 STR	D2, [X11, X0,LSL #3]

    (1158) 0x45f498 ADD	X0, X0, #4

    (1158) 0x45f49c LDR	D16, [X10, X2,LSL #3]

    (1158) 0x45f4a0 STR	D16, [X13, X2,LSL #3]

    (1158) 0x45f4a4 LDR	D20, [X8, X2,LSL #3]

    (1158) 0x45f4a8 LDR	D17, [X12, X2,LSL #3]

    (1158) 0x45f4ac LDR	D18, [X7, X2,LSL #3]

    (1158) 0x45f4b0 STUR	D20, [X1, #440]

    (1158) 0x45f4b4 STP	D17, D18, [X30, #8]

    (1158) 0x45f4b8 LDR	D1, [X9, X2,LSL #3]

    (1158) 0x45f4bc STR	D1, [X11, X2,LSL #3]

    (1158) 0x45f4c0 LDR	D31, [X10, X5,LSL #3]

    (1158) 0x45f4c4 STR	D31, [X13, X5,LSL #3]

    (1158) 0x45f4c8 LDR	D3, [X8, X5,LSL #3]

    (1158) 0x45f4cc LDR	D22, [X12, X5,LSL #3]

    (1158) 0x45f4d0 LDR	D25, [X7, X5,LSL #3]

    (1158) 0x45f4d4 STUR	D3, [X1, #464]

    (1158) 0x45f4d8 STP	D22, D25, [X26, #8]

    (1158) 0x45f4dc LDR	D4, [X9, X5,LSL #3]

    (1158) 0x45f4e0 STR	D4, [X11, X5,LSL #3]

    (1158) 0x45f4e4 LDR	D5, [X10, X3,LSL #3]

    (1158) 0x45f4e8 STR	D5, [X13, X3,LSL #3]

    (1158) 0x45f4ec LDR	D7, [X12, X3,LSL #3]

    (1158) 0x45f4f0 LDR	D19, [X7, X3,LSL #3]

    (1158) 0x45f4f4 LDR	D6, [X8, X3,LSL #3]

    (1158) 0x45f4f8 STUR	D6, [X1, #488]

    (1158) 0x45f4fc STP	D7, D19, [X6, #8]

    (1158) 0x45f500 LDR	D21, [X9, X3,LSL #3]

    (1158) 0x45f504 STR	D21, [X11, X3,LSL #3]

    (1158) 0x45f508 CMP	X25, X0

    (1158) 0x45f50c B.NE	45f458

  (1157) 0x45f510 LDR	X25, [SP, #168]

  (1157) 0x45f514 ADD	X15, X15, #24

  (1157) 0x45f518 ADD	W4, W4, W27

  (1157) 0x45f51c ADD	W14, W14, W24

  (1157) 0x45f520 ADD	X16, X16, #40

  (1157) 0x45f524 ADD	X17, X17, X18

  (1157) 0x45f528 ADD	X10, X25, X28

  (1157) 0x45f52c STR	X10, [SP, #168]

  (1157) 0x45f530 CMP	X15, X18

  (1157) 0x45f534 B.NE	45f348

(1153) 0x45f538 LDP	X29, X30, [SP]

(1153) 0x45f53c LDP	X19, X20, [SP, #16]

(1153) 0x45f540 LDP	X21, X22, [SP, #32]

(1153) 0x45f544 LDP	X23, X24, [SP, #48]

(1153) 0x45f548 LDP	X25, X26, [SP, #64]

(1153) 0x45f54c LDP	X27, X28, [SP, #80]

(1153) 0x45f550 ADD	SP, SP, #624

(1153) 0x45f554 RET

  (1151) 0x45f558 MOVI	D11, #0

  (1151) 0x45f55c FMOV	D14, #1.0000000

  (1151) 0x45f560 LDR	D7, [SP, #208]

  (1151) 0x45f564 MOVZ	X13, #0

  (1151) 0x45f568 FMOV	D9, D1

  (1151) 0x45f56c FMOV	D10, #-2.0000000

  (1151) 0x45f570 FMOV	D12, D1

  (1151) 0x45f574 FMOV	D8, #0.5000000

  (1151) 0x45f578 FMOV	D13, #-0.5000000

  (1151) 0x45f57c FMOV	D16, D14

  (1151) 0x45f580 FMOV	D17, D11

  (1151) 0x45f584 FMOV	D18, D11

  (1151) 0x45f588 FMOV	D15, D11

  (1151) 0x45f58c B	45edb0

    (1152) 0x45f590 MOVI	D23, #0

    (1152) 0x45f594 FMOV	D26, #1.0000000

    (1152) 0x45f598 LDR	D3, [SP, #208]

    (1152) 0x45f59c MOVZ	W8, #0

    (1152) 0x45f5a0 FMOV	D10, #-2.0000000

    (1152) 0x45f5a4 FMOV	D11, #0.5000000

    (1152) 0x45f5a8 FMOV	D28, #-0.5000000

    (1152) 0x45f5ac FMOV	D20, D1

    (1152) 0x45f5b0 FMOV	D19, D1

    (1152) 0x45f5b4 FMOV	D30, D23

    (1152) 0x45f5b8 STP	D23, D23, [SP, #216]

    (1152) 0x45f5bc STP	D11, D26, [SP, #232]

    (1152) 0x45f5c0 STR	D10, [SP, #248]

    (1152) 0x45f5c4 B	45ecf4

    (1152) 0x45f5c8 MOVI	D21, #0

    (1152) 0x45f5cc FMOV	D24, #1.0000000

    (1152) 0x45f5d0 LDR	D2, [SP, #208]

    (1152) 0x45f5d4 MOVZ	W10, #0

    (1152) 0x45f5d8 FMOV	D19, #-2.0000000

    (1152) 0x45f5dc FMOV	D3, #0.5000000

    (1152) 0x45f5e0 FMOV	D27, #-0.5000000

    (1152) 0x45f5e4 FMOV	D6, D1

    (1152) 0x45f5e8 FMOV	D5, D1

    (1152) 0x45f5ec FMOV	D4, D21

    (1152) 0x45f5f0 FMOV	D29, D21

    (1152) 0x45f5f4 STP	D21, D3, [SP, #168]

    (1152) 0x45f5f8 STP	D24, D19, [SP, #184]

    (1152) 0x45f5fc B	45ec2c

    (1152) 0x45f600 ADRP	X14,

    (1152) 0x45f604 MOVI	D28, #0

    (1152) 0x45f608 MOVN	X13, #3

    (1152) 0x45f60c LDR	D20, [SP, #208]

    (1152) 0x45f610 MOVN	X11, #7

    (1152) 0x45f614 MOVN	X16, #3

    (1152) 0x45f618 LDR	D31, [X14, #2960]

    (1152) 0x45f61c MOVZ	X18, #3

    (1152) 0x45f620 MOVN	X22, #1

    (1152) 0x45f624 MOVK	X13, #49151

    (1152) 0x45f628 MOVK	X11, #16367

    (1152) 0x45f62c MOVZ	X15, #15536

    (1152) 0x45f630 MOVK	X16, #16351

    (1152) 0x45f634 FMOV	D19, D28

    (1152) 0x45f638 MOVZ	X17, #15556

    (1152) 0x45f63c MOVK	X18, #49120

    (1152) 0x45f640 FMOV	D26, X13

    (1152) 0x45f644 MOVK	X22, #16367

    (1152) 0x45f648 ADRP	X23,

    (1152) 0x45f64c FMOV	D23, X16

    (1152) 0x45f650 STP	X18, X17, [SP, #224]

    (1152) 0x45f654 FMOV	D30, X22

    (1152) 0x45f658 LDR	D3, [X23, #2968]

    (1152) 0x45f65c STR	D31, [SP, #216]

    (1152) 0x45f660 STP	X15, X11, [SP, #240]

    (1152) 0x45f664 B	45ecf4

    (1152) 0x45f668 MOVI	D27, #0

    (1152) 0x45f66c MOVN	X26, #3

    (1152) 0x45f670 MOVN	X27, #7

    (1152) 0x45f674 LDR	D6, [SP, #208]

    (1152) 0x45f678 MOVN	X4, #3

    (1152) 0x45f67c MOVZ	X1, #3

    (1152) 0x45f680 MOVN	X0, #1

    (1152) 0x45f684 MOVK	X26, #49151

    (1152) 0x45f688 MOVK	X27, #16367

    (1152) 0x45f68c ADRP	X25,

    (1152) 0x45f690 MOVZ	X19, #15536

    (1152) 0x45f694 MOVK	X4, #16351

    (1152) 0x45f698 FMOV	D24, X26

    (1152) 0x45f69c FMOV	D5, D27

    (1152) 0x45f6a0 MOVZ	X3, #15556

    (1152) 0x45f6a4 MOVK	X1, #49120

    (1152) 0x45f6a8 LDR	D4, [X25, #2960]

    (1152) 0x45f6ac MOVK	X0, #16367

    (1152) 0x45f6b0 ADRP	X7,

    (1152) 0x45f6b4 FMOV	D21, X4

    (1152) 0x45f6b8 STP	X1, X3, [SP, #168]

    (1152) 0x45f6bc FMOV	D29, X0

    (1152) 0x45f6c0 LDR	D2, [X7, #2968]

    (1152) 0x45f6c4 STP	X19, X27, [SP, #184]

    (1152) 0x45f6c8 B	45ec2c

    (1152) 0x45f6cc MOVI	D13, #0

    (1152) 0x45f6d0 MOVN	X19, #3

    (1152) 0x45f6d4 MOVN	X12, #7

    (1152) 0x45f6d8 LDR	D9, [SP, #208]

    (1152) 0x45f6dc MOVN	X30, #3

    (1152) 0x45f6e0 MOVZ	X1, #3

    (1152) 0x45f6e4 MOVN	X0, #1

    (1152) 0x45f6e8 MOVK	X19, #49151

    (1152) 0x45f6ec MOVK	X12, #16367

    (1152) 0x45f6f0 ADRP	X4,

    (1152) 0x45f6f4 MOVZ	X7, #15536

    (1152) 0x45f6f8 MOVK	X30, #16351

    (1152) 0x45f6fc FMOV	D14, X19

    (1152) 0x45f700 FMOV	D12, D13

    (1152) 0x45f704 MOVZ	X3, #15556

    (1152) 0x45f708 MOVK	X1, #49120

    (1152) 0x45f70c FMOV	D10, X12

    (1152) 0x45f710 MOVK	X0, #16367

    (1152) 0x45f714 ADRP	X11,

    (1152) 0x45f718 FMOV	D16, X7

    (1152) 0x45f71c FMOV	D11, X30

    (1152) 0x45f720 SBFM	X13, X27, #0, #31

    (1152) 0x45f724 FMOV	D8, X3

    (1152) 0x45f728 FMOV	D17, X1

    (1152) 0x45f72c FMOV	D15, X0

    (1152) 0x45f730 LDR	D18, [X4, #2960]

    (1152) 0x45f734 LDR	D7, [X11, #2968]

    (1152) 0x45f738 B	45edb0

    (1152) 0x45f73c LDR	X28, [SP, #384]

    (1152) 0x45f740 CBNZ	X28, 45f148

    (1152) 0x45f744 LDR	X13, [SP, #200]

    (1152) 0x45f748 ADD	X5, X5, #8

    (1152) 0x45f74c ADD	X6, X6, #40

    (1152) 0x45f750 LDR	X15, [SP, #368]

    (1152) 0x45f754 ADD	X14, X13, #24

    (1152) 0x45f758 STR	X14, [SP, #200]

    (1152) 0x45f75c CMP	X15, X5

    (1152) 0x45f760 B.NE	45eb28

(1153) 0x45f764 B	45f2e8

0x45f768 HINT	#0

0x45f76c HINT	#0

0x45f770 HINT	#0

0x45f774 HINT	#0

0x45f778 HINT	#0

0x45f77c HINT	#0

Coverage (%)	Name	Source Location	Module
►42.15+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►41.06+	miniqmcreference::DiracDetermi[...]	DiracDeterminantRef.cpp:100	exec
○	qmcplusplus::WaveFunction::rat[...]	WaveFunction.cpp:196	exec
○	main._omp_fn.1	stl_vector.h:1128	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.89+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►7.87+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:144	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:171	exec
○	main._omp_fn.0	miniqmc.cpp:397	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	einspline_spo_ref.hpp:203-230
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,199-215,226-262,269-286
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170-173
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1131,1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:203-211,219-230
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53-66
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238,951-952
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,265,271
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.67 to 5.00 cycles (2.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 58% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 12.67 to 9.75 cycles (1.30x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

38% of VPU loads are used in vector version.
22% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.67 to 0.50 cycles (25.33x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 156 bytes. The binary function is storing 276 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	104
loop length	416
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	8.25	8.25	8.25	8.25	12.67	12.67	12.67	8.00	8.00
cycles	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	8.25	8.25	8.25	8.25	12.67	12.67	12.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.67

Vectorization ratios

INT

all	17%
load	38%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	12%
load	38%
store	22%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.67 cycles. At this rate:

12% of peak load performance is reached (12.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45e9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #624	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W19, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X25, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X24, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X25, #292]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X25, #296	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W19, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ea00 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SMADDL X3, W19, W1, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X20, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D23, D31, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVI D27, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ X5, #48304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D29, D30, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMOV D28, X5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D25, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D26, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D31, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D20, D4, [X4, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL D1, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D19, D21, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D6, D22, [X4, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMADD D3, D23, D25, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMUL D7, D31, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR W9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMADD D2, D23, D19, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D5, D26, D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D24, D5	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D23, D23, D21, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D16, D26, D6, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D17, D16	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D31, D26, D22, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D0, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FCMPE D5, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FSUB D18, D5, S24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB D30, D16, S17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCCMPE D5, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W6, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W6, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D29, D18, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D16, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D16, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W7, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D1, D30, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D31, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STP D29, D1, [SP, #344]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FCCMPE D31, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FSUB D28, D31, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CSINC W8, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D27, D28, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
STR D27, [SP, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP W9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f304 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X12, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X10, #16325	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK X12, #16357	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ X6, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D1, X10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR W30, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X20, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X5, W9,UXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X24, X20, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SBFM X15, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X2, X30, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP X23, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X13, [X20, #784]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X11, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X14, [X20, #808]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR W30, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X20, #832]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X15, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	einspline_spo_ref.hpp:203-230
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:187-192,199-215,226-262,269-286
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170-173
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1131,1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:203-211,219-230
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53-66
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:68-79
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238,951-952
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:231,265,271
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:145

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 12.67 to 5.00 cycles (2.53x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

38% of VPU loads are used in vector version.
22% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 12.67 to 0.50 cycles (25.33x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 156 bytes. The binary function is storing 276 bytes.

Arithmetic intensity

Arithmetic intensity is 0.04 FP operations per loaded or stored byte.

General properties

nb instructions	104
loop length	416
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

12.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	8.25	8.25	8.25	8.25	12.67	12.67	12.67	8.00	8.00
cycles	1.50	1.50	5.17	5.17	5.17	5.17	5.17	5.17	8.25	8.25	8.25	8.25	12.67	12.67	12.67	8.00	8.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	12.25
Overall L1	12.67

Vectorization ratios

INT

all	17%
load	38%
store	22%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	12%
load	38%
store	22%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 12.67 cycles. At this rate:

12% of peak load performance is reached (12.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
45% of peak store performance is reached (21.79 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45e9a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #624	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W19, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X23, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X25, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X24, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X25, #292]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X25, #296	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W19, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45ea00 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x60>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X25, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SMADDL X3, W19, W1, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X20, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D23, D31, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVI D27, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ X5, #48304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D29, D30, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMOV D28, X5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D25, [X20, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D26, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D31, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D20, D4, [X4, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL D1, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D19, D21, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D6, D22, [X4, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMADD D3, D23, D25, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMUL D7, D31, D20	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR W9, [X20, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
FMADD D2, D23, D19, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D5, D26, D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D24, D5	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D23, D23, D21, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D16, D26, D6, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D17, D16	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D31, D26, D22, D23	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D0, D31	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FCMPE D5, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FSUB D18, D5, S24	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB D30, D16, S17	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCCMPE D5, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W6, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W6, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D29, D18, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D16, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D16, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W7, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D1, D30, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D31, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STP D29, D1, [SP, #344]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
FCCMPE D31, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FSUB D28, D31, S0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
CSINC W8, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D27, D28, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
STR D27, [SP, #360]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
CMP W9, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45f304 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEERNS6_INS2_10TinyVectorIdLj3EEESaISB_EEES9_+0x964>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X10, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
ORR X12, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X10, #16325	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK X12, #16357	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ X6, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
FMOV D1, X10	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR W30, [X20, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X12, [SP, #208]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X5, [X20, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X11, X5, W9,UXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
STP X24, X20, [SP, #392]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
SBFM X15, X30, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
SBFM X2, X30, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STP X23, X22, [SP, #408]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
LDR X13, [X20, #784]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X11, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X14, [X20, #808]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR W30, [SP, #380]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X16, [X20, #832]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
STR X13, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X15, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X14, [SP, #328]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X21, [SP, #424]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X16, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&, qmcplusplus::Vector, std::allocator >...–	10.32	14.30
▼Loop 1153 - einspline_spo_ref.hpp:206-230 - exec–	0.00	0.01
▼Loop 1157 - einspline_spo_ref.hpp:219-227 - exec–	0.01	0.01
○Loop 1158 - einspline_spo_ref.hpp:223-227 - exec	0.24	0.32
▼Loop 1151 - MultiBsplineRef.hpp:187-286 - exec–	0.00	0.00
▼Loop 1152 - einspline_spo_ref.hpp:206-207 - exec–	0.01	0.01
○Loop 1150 - MultiBsplineRef.hpp:276-286 - exec	0.41	0.56
▼Loop 1156 - MultiBsplineRef.hpp:226-262 - exec–	0.00	0.01
▼Loop 1155 - MultiBsplineRef.hpp:227-262 - exec–	0.00	0.01
○Loop 1154 - MultiBsplineRef.hpp:242-262 - exec	9.66	13.23

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code