OV - exec - Function miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector<double, std::allocator<double> >&)

	Function: miniqmcreference::einspline_spo_ref<double>::evaluate(qmcplusplus::ParticleSet const&, int ...	Module: exec	Source: einspline_spo_ref.hpp:172-189 [...]	Coverage (incl. loops): 22.35% \| (excl. loops): 0.01%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp: 42 - 71

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42:   x -= spline_m->x_grid.start;

43:   y -= spline_m->y_grid.start;

44:   z -= spline_m->z_grid.start;

45:   T tx, ty, tz;

46:   int ix, iy, iz;

47:   spline2::getSplineBound(x * spline_m->x_grid.delta_inv, tx, ix, spline_m->x_grid.num - 1);

48:   spline2::getSplineBound(y * spline_m->y_grid.delta_inv, ty, iy, spline_m->y_grid.num - 1);

49:   spline2::getSplineBound(z * spline_m->z_grid.delta_inv, tz, iz, spline_m->z_grid.num - 1);

[...]

57:   const intptr_t ys = spline_m->y_stride;

58:   const intptr_t zs = spline_m->z_stride;

59:

60:   constexpr T zero(0);

61:   std::fill(vals, vals + num_splines, zero);

62:

63:   for (size_t i = 0; i < 4; i++)

64:     for (size_t j = 0; j < 4; j++)

65:     {

66:       const T pre00           = a[i] * b[j];

67:       const T* restrict coefs = spline_m->coefs + (ix + i) * xs + (iy + j) * ys + iz * zs;

68:       for (size_t n = 0; n < num_splines; n++)

69:         vals[n] += pre00 *

70:             (c[0] * coefs[n] + c[1] * coefs[n + zs] + c[2] * coefs[n + 2 * zs] +

71:              c[3] * coefs[n + 3 * zs]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h: 170 - 173

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170:       if (-std::numeric_limits<T1>::epsilon() < val_dot[i] && val_dot[i] < 0)

171:         val_dot[i] = T1(0.0);

172:       else

173:         val_dot[i] -= std::floor(val_dot[i]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

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242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h: 213 - 213

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213:   inline Type_t operator[](unsigned int i) const { return X[i]; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 1263 - 1263

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1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h: 150 - 152

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150:     return TinyVector<Type_t, 3>(lhs[0] * rhs[0] + lhs[1] * rhs[3] + lhs[2] * rhs[6],

151:                                  lhs[0] * rhs[1] + lhs[1] * rhs[4] + lhs[2] * rhs[7],

152:                                  lhs[0] * rhs[2] + lhs[1] * rhs[5] + lhs[2] * rhs[8]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp: 172 - 189

--------------------------------------------------------------------------------

172:     ScopedTimer local_timer(timer);

173:

174:     auto u = Lattice.toUnit_floor(P.activeR(iat));

175:     for (int i = 0; i < nBlocks; ++i)

176:       MultiBsplineEvalRef::evaluate_v(einsplines[i], u[0], u[1], u[2], psi[i].data(), nSplinesPerBlock);

177:   }

178:

179:   inline void evaluate(const ParticleSet& P, int iat, ValueVector_t& psi_v)

180:   {

181:     evaluate_v(P, iat);

182:

183:     for (int i = 0; i < nBlocks; ++i)

184:     {

185:       // in real simulation, phase needs to be applied. Here just fake computation

186:       const int first = i * nBlocks;

187:       std::copy_n(psi[i].data(), std::min((i + 1) * nSplinesPerBlock, OrbitalSetSize) - first, psi_v.data() + first);

188:     }

189:   }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h: 683 - 709

--------------------------------------------------------------------------------

683:     { return std::copy(__first, __first + __n, __result); }

[...]

709:       if (__n2 <= 0)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 229 - 229

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229:     return X[i];

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp: 53 - 63

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53:   if (x < 0)

[...]

60:     ind = static_cast<int>(x);

61:     dx = x - ind;

62:     // upper bound

63:     if (ind > nmax)

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 143 - 143

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143:     return (active_ptcl_ == iat) ? active_pos_ : R[iat];

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp: 54 - 57

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54:     a[0] = ((A00 * tx + A01) * tx + A02) * tx + A03;

55:     a[1] = ((A10 * tx + A11) * tx + A12) * tx + A13;

56:     a[2] = ((A20 * tx + A21) * tx + A22) * tx + A23;

57:     a[3] = ((A30 * tx + A31) * tx + A32) * tx + A33;

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 238 - 952

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238:       if (__b < __a)

[...]

413: 	{ *__to = *__from; }

[...]

451: 	  if (__builtin_expect(_Num > 1, true))

452: 	    __builtin_memmove(__result, __first, sizeof(_Tp) * _Num);

[...]

951:       for (; __first != __last; ++__first)

952: 	*__first = __tmp;

0x45b980 STP	X29, X30, [SP, #736]!

0x45b984 ADD	X29, SP, #0

0x45b988 STP	X19, X20, [SP, #16]

0x45b98c ORR	X19, XZR, X0

0x45b990 ORR	W20, WZR, W2

0x45b994 STP	X21, X22, [SP, #32]

0x45b998 ORR	X21, XZR, X1

0x45b99c ORR	X22, XZR, X3

0x45b9a0 STP	X27, X28, [SP, #80]

0x45b9a4 STP	D12, D13, [SP, #128]

0x45b9a8 STP	D14, D15, [SP, #144]

0x45b9ac LDR	X28, [X0, #856]

0x45b9b0 ORR	X0, XZR, X28

0x45b9b4 BL	4d5540

0x45b9b8 LDR	W0, [X21, #292]

0x45b9bc ADD	X3, X21, #296

0x45b9c0 CMP	W20, W0

0x45b9c4 B.EQ	45b9d4

0x45b9c8 LDR	X2, [X21, #64]

0x45b9cc MOVZ	W1, #24

0x45b9d0 SMADDL	X3, W20, W1, X2

0x45b9d4 ADD	X4, X19, #216

0x45b9d8 LDP	D25, D31, [X3]

0x45b9dc MOVI	D27, #0

0x45b9e0 MOVZ	X5, #48304

0x45b9e4 LDP	D29, D30, [X4, #24]

0x45b9e8 FMOV	D28, X5

0x45b9ec LDR	D24, [X19, #216]

0x45b9f0 LDR	D26, [X3, #16]

0x45b9f4 FMUL	D0, D31, D29

0x45b9f8 LDP	D21, D4, [X4, #40]

0x45b9fc FMUL	D1, D31, D30

0x45ba00 LDP	D20, D23, [X4, #8]

0x45ba04 LDP	D22, D6, [X4, #56]

0x45ba08 FMADD	D3, D25, D24, D0

0x45ba0c FMUL	D7, D31, D21

0x45ba10 LDR	W10, [X19, #48]

0x45ba14 FMADD	D2, D25, D20, D1

0x45ba18 FMADD	D5, D26, D4, D3

0x45ba1c FRINTM	D14, D5

0x45ba20 FMADD	D13, D25, D23, D7

0x45ba24 FMADD	D12, D26, D22, D2

0x45ba28 FRINTM	D15, D12

0x45ba2c FMADD	D17, D26, D6, D13

0x45ba30 FRINTM	D18, D17

0x45ba34 FCMPE	D5, D27

0x45ba38 FSUB	D16, D5, S14

0x45ba3c FSUB	D19, D12, S15

0x45ba40 FSUB	D25, D17, S18

0x45ba44 FCCMPE	D5, D28, #4, #4

0x45ba48 CSINC	W6, WZR, WZR, #13

0x45ba4c CMP	W6, #0

0x45ba50 FCSEL	D14, D16, D27, #0

0x45ba54 FCMPE	D12, D27

0x45ba58 FCCMPE	D12, D28, #4, #4

0x45ba5c CSINC	W7, WZR, WZR, #13

0x45ba60 CMP	W7, #0

0x45ba64 FCSEL	D31, D19, D27, #0

0x45ba68 FCMPE	D17, D27

0x45ba6c STR	D31, [SP, #184]

0x45ba70 FCCMPE	D17, D28, #4, #4

0x45ba74 CSINC	W8, WZR, WZR, #13

0x45ba78 CMP	W8, #0

0x45ba7c FCSEL	D13, D25, D27, #0

0x45ba80 CMP	W10, #0

0x45ba84 B.LE	45bfc0

0x45ba88 ORR	X9, XZR, #3840

0x45ba8c ORR	X11, XZR, #3840

0x45ba90 STP	D10, D11, [SP, #112]

0x45ba94 MOVK	X9, #16325

0x45ba98 MOVK	X11, #16357

0x45ba9c STP	X23, X24, [SP, #48]

0x45baa0 FMOV	D11, X9

0x45baa4 FMOV	D12, X11

0x45baa8 STP	X25, X26, [SP, #64]

0x45baac STP	D8, D9, [SP, #96]

0x45bab0 LDR	W12, [X19, #64]

0x45bab4 STR	X22, [SP, #216]

0x45bab8 LDR	X23, [X19, #760]

0x45babc ADD	X13, X23, W10,UXTW #3

0x45bac0 STR	X13, [SP, #176]

0x45bac4 LDR	X24, [X19, #784]

0x45bac8 SBFM	X20, X12, #0, #31

0x45bacc SBFM	X25, X12, #61, #31

0x45bad0 STR	W12, [SP, #196]

0x45bad4 SUB	X21, X20, #1

0x45bad8 STP	X28, X19, [SP, #200]

    (1113) 0x45badc LDR	X28, [X23]

    (1113) 0x45bae0 LDR	D29, [SP, #184]

    (1113) 0x45bae4 LDR	X3, [X24]

    (1113) 0x45bae8 LDR	D27, [X28, #40]

    (1113) 0x45baec LDP	D8, D9, [X28, #72]

    (1113) 0x45baf0 LDR	D10, [X28, #120]

    (1113) 0x45baf4 FSUB	D28, D14, S27

    (1113) 0x45baf8 FSUB	D1, D29, S9

    (1113) 0x45bafc FSUB	D0, D13, S10

    (1113) 0x45bb00 FMUL	D30, D28, D8

    (1113) 0x45bb04 FCMPE	D30, #0

    (1113) 0x45bb08 B.MI	45c0b0

    (1113) 0x45bb0c LDR	W15, [X28, #56]

    (1113) 0x45bb10 FCVTZS	W14, D30

    (1113) 0x45bb14 SUB	W16, W15, #1

    (1113) 0x45bb18 CMP	W16, W14

    (1113) 0x45bb1c B.LT	45c0e8

    (1113) 0x45bb20 ORR	X17, XZR, #3840

    (1113) 0x45bb24 FRINTZ	D20, D30

    (1113) 0x45bb28 FSUB	D23, D30, S20

    (1113) 0x45bb2c FMOV	D2, #0.5000000

    (1113) 0x45bb30 SBFM	X19, X14, #0, #31

    (1113) 0x45bb34 MOVK	X17, #49093

    (1113) 0x45bb38 FMOV	D3, #-0.5000000

    (1113) 0x45bb3c FMOV	D26, #-1.0000000

    (1113) 0x45bb40 FMOV	D21, X17

    (1113) 0x45bb44 FMSUB	D4, D23, D2, D2

    (1113) 0x45bb48 FMUL	D24, D23, D23

    (1113) 0x45bb4c FMADD	D5, D23, D2, D26

    (1113) 0x45bb50 FMADD	D6, D23, D4, D2

    (1113) 0x45bb54 FMUL	D22, D23, D21

    (1113) 0x45bb58 FMADD	D18, D5, D24, D12

    (1113) 0x45bb5c FMADD	D16, D23, D6, D11

    (1113) 0x45bb60 FADD	D7, D22, D2

    (1113) 0x45bb64 FNMUL	D17, D22, D24

    (1113) 0x45bb68 FMADD	D15, D23, D7, D3

    (1113) 0x45bb6c FMADD	D19, D23, D15, D11

    (1113) 0x45bb70 LDR	D25, [X28, #112]

    (1113) 0x45bb74 FMUL	D31, D1, D25

    (1113) 0x45bb78 FCMPE	D31, #0

    (1113) 0x45bb7c B.MI	45c098

    (1113) 0x45bb80 LDR	W27, [X28, #96]

    (1113) 0x45bb84 FCVTZS	W26, D31

    (1113) 0x45bb88 SUB	W30, W27, #1

    (1113) 0x45bb8c CMP	W30, W26

    (1113) 0x45bb90 B.LT	45c0c8

    (1113) 0x45bb94 ORR	X0, XZR, #3840

    (1113) 0x45bb98 FRINTZ	D8, D31

    (1113) 0x45bb9c FSUB	D9, D31, S8

    (1113) 0x45bba0 FMOV	D27, #0.5000000

    (1113) 0x45bba4 SBFM	X8, X26, #0, #31

    (1113) 0x45bba8 MOVK	X0, #49093

    (1113) 0x45bbac FMOV	D10, #-0.5000000

    (1113) 0x45bbb0 FMOV	D30, #-1.0000000

    (1113) 0x45bbb4 FMOV	D28, X0

    (1113) 0x45bbb8 FMSUB	D29, D9, D27, D27

    (1113) 0x45bbbc FMUL	D1, D9, D9

    (1113) 0x45bbc0 FMADD	D20, D9, D27, D30

    (1113) 0x45bbc4 FMADD	D3, D9, D29, D27

    (1113) 0x45bbc8 FMUL	D2, D9, D28

    (1113) 0x45bbcc FMADD	D23, D20, D1, D12

    (1113) 0x45bbd0 FMADD	D4, D9, D3, D11

    (1113) 0x45bbd4 FADD	D26, D2, D27

    (1113) 0x45bbd8 FNMUL	D24, D2, D1

    (1113) 0x45bbdc FMADD	D21, D9, D26, D10

    (1113) 0x45bbe0 FMADD	D5, D9, D21, D11

    (1113) 0x45bbe4 LDR	D22, [X28, #152]

    (1113) 0x45bbe8 FMUL	D0, D0, D22

    (1113) 0x45bbec FCMPE	D0, #0

    (1113) 0x45bbf0 B.MI	45c080

    (1113) 0x45bbf4 LDR	W5, [X28, #136]

    (1113) 0x45bbf8 FCVTZS	W4, D0

    (1113) 0x45bbfc SUB	W6, W5, #1

    (1113) 0x45bc00 CMP	W6, W4

    (1113) 0x45bc04 B.LT	45c108

    (1113) 0x45bc08 ORR	X7, XZR, #3840

    (1113) 0x45bc0c FRINTZ	D6, D0

    (1113) 0x45bc10 FSUB	D7, D0, S6

    (1113) 0x45bc14 FMOV	D25, #0.5000000

    (1113) 0x45bc18 SBFM	X11, X4, #0, #31

    (1113) 0x45bc1c MOVK	X7, #49093

    (1113) 0x45bc20 FMOV	D15, #-1.0000000

    (1113) 0x45bc24 FMOV	D31, #-0.5000000

    (1113) 0x45bc28 FMOV	D9, X7

    (1113) 0x45bc2c FMSUB	D27, D7, D25, D25

    (1113) 0x45bc30 FMUL	D10, D7, D7

    (1113) 0x45bc34 FMADD	D8, D7, D25, D15

    (1113) 0x45bc38 FMADD	D28, D7, D27, D25

    (1113) 0x45bc3c FMUL	D30, D7, D9

    (1113) 0x45bc40 FMADD	D8, D8, D10, D12

    (1113) 0x45bc44 FMADD	D15, D7, D28, D11

    (1113) 0x45bc48 FADD	D29, D30, D25

    (1113) 0x45bc4c FNMUL	D9, D30, D10

    (1113) 0x45bc50 FMADD	D1, D7, D29, D31

    (1113) 0x45bc54 FMADD	D10, D7, D1, D11

    (1113) 0x45bc58 LDR	X22, [X28, #32]

    (1113) 0x45bc5c STP	D19, D18, [SP, #224]

    (1113) 0x45bc60 STP	D16, D17, [SP, #240]

    (1113) 0x45bc64 STP	D5, D23, [SP, #256]

    (1113) 0x45bc68 STP	D4, D24, [SP, #272]

    (1113) 0x45bc6c LDP	X26, X27, [X28, #16]

    (1113) 0x45bc70 CBZ	X25, 45bc90

    (1113) 0x45bc74 ORR	X0, XZR, X3

    (1113) 0x45bc78 ORR	X2, XZR, X25

    (1113) 0x45bc7c MOVZ	W1, #0

    (1113) 0x45bc80 STP	X8, X11, [SP, #160]

    (1113) 0x45bc84 BL	403ea0

    (1113) 0x45bc88 LDP	X8, X11, [SP, #160]

    (1113) 0x45bc8c ORR	X3, XZR, X0

    (1113) 0x45bc90 MADD	X12, X22, X11, XZR

    (1113) 0x45bc94 LDR	X13, [X28, #8]

    (1113) 0x45bc98 CBZ	X20, 45bf94

  (1112) 0x45bc9c UBFM	X28, X27, #61, #60

  (1112) 0x45bca0 DUP	V2.2D, V10.D[0]

  (1112) 0x45bca4 DUP	V23.2D, V8.D[0]

  (1112) 0x45bca8 UBFM	X14, X20, #1, #63

  (1112) 0x45bcac MADD	X1, X19, X26, X12

  (1112) 0x45bcb0 LDR	W18, [SP, #196]

  (1112) 0x45bcb4 DUP	V24.2D, V15.D[0]

  (1112) 0x45bcb8 DUP	V22.2D, V9.D[0]

  (1112) 0x45bcbc UBFM	X15, X27, #60, #59

  (1112) 0x45bcc0 UBFM	X14, X14, #60, #59

  (1112) 0x45bcc4 MADD	X17, X8, X28, X28

  (1112) 0x45bcc8 ADD	X6, SP, #224

  (1112) 0x45bccc ADD	X16, SP, #256

  (1112) 0x45bcd0 MADD	X2, X8, X28, X13

  (1112) 0x45bcd4 UBFM	X10, X22, #61, #60

  (1112) 0x45bcd8 AND	X8, X20, #8127

  (1112) 0x45bcdc ADD	X7, X17, X13

  (1112) 0x45bce0 AND	W28, W18, #0

  (1112) 0x45bce4 LDR	D17, [X6]

  (1112) 0x45bce8 ADD	X9, X2, X1,LSL #3

  (1112) 0x45bcec ORR	X30, XZR, X16

  (1112) 0x45bcf0 ADD	X5, X7, X1,LSL #3

    (1109) 0x45bcf4 LDR	D16, [X30]

    (1109) 0x45bcf8 FMUL	D19, D17, D16

    (1109) 0x45bcfc CMP	X21, #1

    (1109) 0x45bd00 B.LS	45c078

    (1109) 0x45bd04 LDR	D18, [X30, #8]

    (1109) 0x45bd08 ADD	X12, X9, X10,LSL #1

    (1109) 0x45bd0c DUP	V20.2D, V19.D[0]

    (1109) 0x45bd10 ADD	X17, X9, X10

    (1109) 0x45bd14 ADD	X13, X10, X5

    (1109) 0x45bd18 ADD	X11, X5, X10,LSL #1

    (1109) 0x45bd1c MOVZ	X0, #0

    (1109) 0x45bd20 ADD	X27, X10, X12

    (1109) 0x45bd24 ADD	X18, X11, X10

    (1109) 0x45bd28 FMUL	D3, D17, D18

    (1109) 0x45bd2c DUP	V21.2D, V3.D[0]

    (1109) 0x45bd30 TBZ	W14, #4, 45bda0

    (1109) 0x45bd34 LDR	Q26, [X9, X10]

    (1109) 0x45bd38 MOVZ	X0, #16

    (1109) 0x45bd3c LDR	Q4, [X12, X10]

    (1109) 0x45bd40 LDR	Q5, [X17, X10]

    (1109) 0x45bd44 LDR	Q6, [X10, X5]

    (1109) 0x45bd48 FMUL	V0.2D, V26.2D, V23.2D

    (1109) 0x45bd4c LDR	Q7, [X11, X10]

    (1109) 0x45bd50 FMUL	V25.2D, V4.2D, V22.2D

    (1109) 0x45bd54 LDR	Q29, [X9]

    (1109) 0x45bd58 LDR	Q28, [X5]

    (1109) 0x45bd5c FMUL	V31.2D, V6.2D, V23.2D

    (1109) 0x45bd60 FMLA	V25.2D, V24.2D, V5.2D

    (1109) 0x45bd64 LDR	Q1, [X13, X10]

    (1109) 0x45bd68 FMLA	V0.2D, V2.2D, V29.2D

    (1109) 0x45bd6c LDR	Q30, [X3]

    (1109) 0x45bd70 FMUL	V27.2D, V7.2D, V22.2D

    (1109) 0x45bd74 FMLA	V31.2D, V28.2D, V2.2D

    (1109) 0x45bd78 FMLA	V27.2D, V1.2D, V24.2D

    (1109) 0x45bd7c FADD	V16.2D, V0.2D, V25.2D

    (1109) 0x45bd80 FADD	V18.2D, V31.2D, V27.2D

    (1109) 0x45bd84 FMLA	V30.2D, V20.2D, V16.2D

    (1109) 0x45bd88 FMLA	V30.2D, V18.2D, V21.2D

    (1109) 0x45bd8c STR	Q30, [X3]

    (1109) 0x45bd90 CMP	X14, X0

    (1109) 0x45bd94 B.EQ	45be68

    (1109) 0x45bd98 HINT	#0

    (1109) 0x45bd9c HINT	#0

      (1111) 0x45bda0 LDR	Q3, [X17, X0]

      (1111) 0x45bda4 ADD	X4, X0, #16

      (1111) 0x45bda8 LDR	Q26, [X27, X0]

      (1111) 0x45bdac LDR	Q4, [X9, X0]

      (1111) 0x45bdb0 LDR	Q0, [X12, X0]

      (1111) 0x45bdb4 FMUL	V25.2D, V3.2D, V23.2D

      (1111) 0x45bdb8 LDR	Q31, [X13, X0]

      (1111) 0x45bdbc FMUL	V7.2D, V26.2D, V22.2D

      (1111) 0x45bdc0 LDR	Q5, [X18, X0]

      (1111) 0x45bdc4 FMLA	V25.2D, V2.2D, V4.2D

      (1111) 0x45bdc8 LDR	Q6, [X5, X0]

      (1111) 0x45bdcc LDR	Q27, [X11, X0]

      (1111) 0x45bdd0 FMLA	V7.2D, V24.2D, V0.2D

      (1111) 0x45bdd4 LDR	Q1, [X3, X0]

      (1111) 0x45bdd8 FMUL	V30.2D, V31.2D, V23.2D

      (1111) 0x45bddc FMUL	V16.2D, V5.2D, V22.2D

      (1111) 0x45bde0 LDR	Q0, [X17, X4]

      (1111) 0x45bde4 LDR	Q26, [X27, X4]

      (1111) 0x45bde8 FMLA	V30.2D, V6.2D, V2.2D

      (1111) 0x45bdec LDR	Q28, [X13, X4]

      (1111) 0x45bdf0 LDR	Q3, [X9, X4]

      (1111) 0x45bdf4 FMLA	V16.2D, V27.2D, V24.2D

      (1111) 0x45bdf8 LDR	Q4, [X12, X4]

      (1111) 0x45bdfc FADD	V29.2D, V25.2D, V7.2D

      (1111) 0x45be00 LDR	Q18, [X18, X4]

      (1111) 0x45be04 FMUL	V25.2D, V0.2D, V23.2D

      (1111) 0x45be08 FMUL	V31.2D, V26.2D, V22.2D

      (1111) 0x45be0c LDR	Q5, [X5, X4]

      (1111) 0x45be10 FMUL	V6.2D, V28.2D, V23.2D

      (1111) 0x45be14 LDR	Q7, [X11, X4]

      (1111) 0x45be18 FADD	V27.2D, V30.2D, V16.2D

      (1111) 0x45be1c FMLA	V1.2D, V20.2D, V29.2D

      (1111) 0x45be20 ORR	V16.16B, V6.16B, V6.16B

      (1111) 0x45be24 FMLA	V25.2D, V2.2D, V3.2D

      (1111) 0x45be28 FMLA	V1.2D, V27.2D, V21.2D

      (1111) 0x45be2c FMLA	V31.2D, V24.2D, V4.2D

      (1111) 0x45be30 FMUL	V28.2D, V18.2D, V22.2D

      (1111) 0x45be34 FMLA	V16.2D, V5.2D, V2.2D

      (1111) 0x45be38 STR	Q1, [X3, X0]

      (1111) 0x45be3c ADD	X0, X0, #32

      (1111) 0x45be40 LDR	Q1, [X3, X4]

      (1111) 0x45be44 FMLA	V28.2D, V7.2D, V24.2D

      (1111) 0x45be48 FADD	V30.2D, V25.2D, V31.2D

      (1111) 0x45be4c ORR	V26.16B, V1.16B, V1.16B

      (1111) 0x45be50 FADD	V0.2D, V16.2D, V28.2D

      (1111) 0x45be54 FMLA	V26.2D, V20.2D, V30.2D

      (1111) 0x45be58 FMLA	V26.2D, V0.2D, V21.2D

      (1111) 0x45be5c STR	Q26, [X3, X4]

      (1111) 0x45be60 CMP	X14, X0

      (1111) 0x45be64 B.NE	45bda0

    (1109) 0x45be68 CBZ	W28, 45c054

    (1109) 0x45be6c ORR	X19, XZR, X8

    (1109) 0x45be70 ADD	X17, X22, X19

    (1109) 0x45be74 UBFM	X27, X19, #61, #60

    (1109) 0x45be78 ADD	X12, X17, X22

    (1109) 0x45be7c UBFM	X11, X17, #61, #60

    (1109) 0x45be80 ADD	X13, X12, X22

    (1109) 0x45be84 UBFM	X18, X12, #61, #60

    (1109) 0x45be88 LDR	D20, [X9, X27]

    (1109) 0x45be8c UBFM	X4, X13, #61, #60

    (1109) 0x45be90 ADD	X0, X19, #1

    (1109) 0x45be94 LDR	D3, [X9, X18]

    (1109) 0x45be98 LDR	D21, [X9, X4]

    (1109) 0x45be9c LDR	D4, [X9, X11]

    (1109) 0x45bea0 LDR	D29, [X5, X4]

    (1109) 0x45bea4 FMUL	D18, D15, D3

    (1109) 0x45bea8 LDR	D25, [X5, X18]

    (1109) 0x45beac FMUL	D31, D9, D21

    (1109) 0x45beb0 LDR	D5, [X5, X27]

    (1109) 0x45beb4 FMADD	D7, D4, D8, D18

    (1109) 0x45beb8 LDR	D6, [X5, X11]

    (1109) 0x45bebc FMUL	D27, D9, D29

    (1109) 0x45bec0 FMADD	D16, D20, D10, D31

    (1109) 0x45bec4 FMUL	D1, D15, D25

    (1109) 0x45bec8 LDR	D0, [X3, X27]

    (1109) 0x45becc LDR	D21, [X30, #8]

    (1109) 0x45bed0 FMADD	D28, D10, D5, D27

    (1109) 0x45bed4 FMADD	D26, D8, D6, D1

    (1109) 0x45bed8 FMUL	D4, D17, D21

    (1109) 0x45bedc FADD	D30, D7, D16

    (1109) 0x45bee0 FADD	D20, D26, D28

    (1109) 0x45bee4 FMADD	D3, D19, D30, D0

    (1109) 0x45bee8 FMADD	D29, D20, D4, D3

    (1109) 0x45beec STR	D29, [X3, X27]

    (1109) 0x45bef0 CMP	X20, X0

    (1109) 0x45bef4 B.LS	45bf6c

    (1109) 0x45bef8 ADD	X19, X0, X22

    (1109) 0x45befc ADD	X17, X27, #8

    (1109) 0x45bf00 ADD	X27, X22, X19

    (1109) 0x45bf04 UBFM	X13, X19, #61, #60

    (1109) 0x45bf08 ADD	X12, X22, X27

    (1109) 0x45bf0c UBFM	X11, X27, #61, #60

    (1109) 0x45bf10 LDR	D18, [X9, X17]

    (1109) 0x45bf14 UBFM	X18, X12, #61, #60

    (1109) 0x45bf18 LDR	D25, [X9, X11]

    (1109) 0x45bf1c LDR	D5, [X9, X18]

    (1109) 0x45bf20 LDR	D6, [X9, X13]

    (1109) 0x45bf24 LDR	D27, [X5, X18]

    (1109) 0x45bf28 FMUL	D16, D15, D25

    (1109) 0x45bf2c LDR	D31, [X5, X11]

    (1109) 0x45bf30 FMUL	D1, D9, D5

    (1109) 0x45bf34 LDR	D7, [X5, X17]

    (1109) 0x45bf38 FMADD	D0, D6, D8, D16

    (1109) 0x45bf3c LDR	D26, [X5, X13]

    (1109) 0x45bf40 FMUL	D28, D9, D27

    (1109) 0x45bf44 FMADD	D30, D18, D10, D1

    (1109) 0x45bf48 FMUL	D20, D15, D31

    (1109) 0x45bf4c LDR	D3, [X3, X17]

    (1109) 0x45bf50 FMADD	D21, D7, D10, D28

    (1109) 0x45bf54 FMADD	D29, D26, D8, D20

    (1109) 0x45bf58 FADD	D18, D0, D30

    (1109) 0x45bf5c FADD	D25, D29, D21

    (1109) 0x45bf60 FMADD	D19, D19, D18, D3

    (1109) 0x45bf64 FMADD	D4, D25, D4, D19

    (1109) 0x45bf68 STR	D4, [X3, X17]

    (1109) 0x45bf6c ADD	X30, X30, #16

    (1109) 0x45bf70 ADD	X4, SP, #288

    (1109) 0x45bf74 ADD	X9, X9, X15

    (1109) 0x45bf78 ADD	X5, X5, X15

    (1109) 0x45bf7c CMP	X30, X4

    (1109) 0x45bf80 B.NE	45bcf4

    (1110) 0x45bf84 ADD	X6, X6, #8

    (1110) 0x45bf88 ADD	X1, X1, X26

    (1110) 0x45bf8c CMP	X6, X16

    (1110) 0x45bf90 B.NE	45bce4

    (1113) 0x45bf94 LDR	X30, [SP, #176]

    (1113) 0x45bf98 ADD	X23, X23, #8

    (1113) 0x45bf9c ADD	X24, X24, #24

    (1113) 0x45bfa0 CMP	X30, X23

    (1113) 0x45bfa4 B.NE	45badc

(1114) 0x45bfa8 LDP	D8, D9, [SP, #96]

(1114) 0x45bfac LDP	X23, X24, [SP, #48]

(1114) 0x45bfb0 LDP	X25, X26, [SP, #64]

(1114) 0x45bfb4 LDP	X28, X19, [SP, #200]

(1114) 0x45bfb8 LDP	D10, D11, [SP, #112]

(1114) 0x45bfbc LDR	X22, [SP, #216]

(1114) 0x45bfc0 ORR	X0, XZR, X28

(1114) 0x45bfc4 MOVZ	X21, #0

(1114) 0x45bfc8 BL	4d57e0

(1114) 0x45bfcc LDR	W27, [X19, #48]

(1114) 0x45bfd0 MOVZ	W20, #0

(1114) 0x45bfd4 CMP	W27, #0

(1114) 0x45bfd8 B.LE	45c038

  (1115) 0x45bfdc LDR	W2, [X19, #64]

  (1115) 0x45bfe0 MADD	W9, W27, W20, WZR

  (1115) 0x45bfe4 ADD	W20, W20, #1

  (1115) 0x45bfe8 LDR	W5, [X19, #8]

  (1115) 0x45bfec MADD	W3, W20, W2, WZR

  (1115) 0x45bff0 CMP	W3, W5

  (1115) 0x45bff4 CSEL	W7, W3, W5, #13

  (1115) 0x45bff8 SUB	W8, W7, W9

  (1115) 0x45bffc CMP	W8, #0

  (1115) 0x45c000 B.LE	45c02c

  (1115) 0x45c004 LDR	X15, [X22, #24]

  (1115) 0x45c008 UBFM	X10, X9, #61, #31

  (1115) 0x45c00c UBFM	X2, X8, #61, #31

  (1115) 0x45c010 LDR	X14, [X19, #784]

  (1115) 0x45c014 ADD	X0, X15, X10

  (1115) 0x45c018 LDR	X1, [X14, X21]

  (1115) 0x45c01c CMP	X2, #8

  (1115) 0x45c020 B.EQ	45c128

  (1115) 0x45c024 BL	403d70

  (1115) 0x45c028 LDR	W27, [X19, #48]

  (1115) 0x45c02c ADD	X21, X21, #24

  (1115) 0x45c030 CMP	W20, W27

  (1115) 0x45c034 B.LT	45bfdc

(1114) 0x45c038 LDP	D12, D13, [SP, #128]

(1114) 0x45c03c LDP	X19, X20, [SP, #16]

(1114) 0x45c040 LDP	X21, X22, [SP, #32]

(1114) 0x45c044 LDP	X27, X28, [SP, #80]

(1114) 0x45c048 LDP	D14, D15, [SP, #144]

(1114) 0x45c04c LDP	X29, X30, [SP], #288

(1114) 0x45c050 RET

  (1112) 0x45c054 ADD	X30, X30, #16

  (1112) 0x45c058 ADD	X19, SP, #288

  (1112) 0x45c05c CMP	X19, X30

  (1112) 0x45c060 B.EQ	45bf84

  (1112) 0x45c064 LDR	D19, [X30]

  (1112) 0x45c068 ADD	X9, X9, X15

  (1112) 0x45c06c ADD	X5, X5, X15

  (1112) 0x45c070 FMUL	D19, D17, D19

  (1112) 0x45c074 B	45bd04

    (1109) 0x45c078 MOVZ	X19, #0

    (1109) 0x45c07c B	45be70

    (1113) 0x45c080 FMOV	D15, D11

    (1113) 0x45c084 MOVI	D9, #0

    (1113) 0x45c088 MOVZ	X11, #0

    (1113) 0x45c08c FMOV	D8, D12

    (1113) 0x45c090 FMOV	D10, D11

    (1113) 0x45c094 B	45bc58

    (1113) 0x45c098 FMOV	D4, D11

    (1113) 0x45c09c MOVI	D24, #0

    (1113) 0x45c0a0 MOVZ	X8, #0

    (1113) 0x45c0a4 FMOV	D23, D12

    (1113) 0x45c0a8 FMOV	D5, D11

    (1113) 0x45c0ac B	45bbe4

    (1113) 0x45c0b0 FMOV	D16, D11

    (1113) 0x45c0b4 MOVI	D17, #0

    (1113) 0x45c0b8 MOVZ	X19, #0

    (1113) 0x45c0bc FMOV	D18, D12

    (1113) 0x45c0c0 FMOV	D19, D11

    (1113) 0x45c0c4 B	45bb70

    (1113) 0x45c0c8 ADRP	X1,

    (1113) 0x45c0cc ADRP	X2,

    (1113) 0x45c0d0 MOVI	D5, #0

    (1113) 0x45c0d4 FMOV	D4, D12

    (1113) 0x45c0d8 SBFM	X8, X30, #0, #31

    (1113) 0x45c0dc LDR	D24, [X1, #2960]

    (1113) 0x45c0e0 LDR	D23, [X2, #2968]

    (1113) 0x45c0e4 B	45bbe4

    (1113) 0x45c0e8 ADRP	X18,

    (1113) 0x45c0ec ADRP	X22,

    (1113) 0x45c0f0 MOVI	D19, #0

    (1113) 0x45c0f4 FMOV	D16, D12

    (1113) 0x45c0f8 SBFM	X19, X16, #0, #31

    (1113) 0x45c0fc LDR	D17, [X18, #2960]

    (1113) 0x45c100 LDR	D18, [X22, #2968]

    (1113) 0x45c104 B	45bb70

    (1113) 0x45c108 ADRP	X10,

    (1113) 0x45c10c ADRP	X9,

    (1113) 0x45c110 MOVI	D10, #0

    (1113) 0x45c114 FMOV	D15, D12

    (1113) 0x45c118 SBFM	X11, X6, #0, #31

    (1113) 0x45c11c LDR	D9, [X10, #2960]

    (1113) 0x45c120 LDR	D8, [X9, #2968]

    (1113) 0x45c124 B	45bc58

  (1115) 0x45c128 LDR	D17, [X1]

  (1115) 0x45c12c STR	D17, [X15, X10]

  (1115) 0x45c130 B	45c02c

0x45c134 HINT	#0

0x45c138 HINT	#0

0x45c13c HINT	#0

Coverage (%)	Name	Source Location	Module
►50.24+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:248	exec
○	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:993	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6
►48.73+	miniqmcreference::DiracDetermi[...]	OhmmsVector.h:248	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:266	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,57-71
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170-173
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238,413,451-452,951-952

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.88 to 4.17 cycles (2.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 57% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 10.88 to 7.58 cycles (1.43x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

38% of VPU loads are used in vector version.
26% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.88 to 0.50 cycles (21.75x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Try to change order in which elements are evaluated (using parentheses) in arithmetic expressions containing both ADD/SUB and MUL operations to enable your compiler to generate FMA instructions wherever possible. For instance a + b*c is a valid FMA (MUL then ADD). However (a+b)* c cannot be translated into an FMA (ADD then MUL).

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 140 bytes. The binary function is storing 204 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	8.25	8.25	8.25	8.25	9.83	9.50	9.67	5.00	5.00
cycles	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	8.25	8.25	8.25	8.25	9.83	9.50	9.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Overall L1	10.88

Vectorization ratios

INT

all	19%
load	38%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	12%
load	38%
store	26%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.88 cycles. At this rate:

13% of peak load performance is reached (12.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (18.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45b980

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W20, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X28, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X21, #292]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X21, #296	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W20, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b9d4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SMADDL X3, W20, W1, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X19, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D25, D31, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVI D27, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ X5, #48304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP D29, D30, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMOV D28, X5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D24, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D26, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D31, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D21, D4, [X4, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL D1, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D20, D23, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D22, D6, [X4, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMADD D3, D25, D24, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMUL D7, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR W10, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMADD D2, D25, D20, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D5, D26, D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D14, D5	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D13, D25, D23, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D12, D26, D22, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D15, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D17, D26, D6, D13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D18, D17	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FCMPE D5, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FSUB D16, D5, S14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB D19, D12, S15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB D25, D17, S18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCCMPE D5, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W6, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W6, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D14, D16, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D12, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D12, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W7, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D31, D19, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D17, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR D31, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
FCCMPE D17, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W8, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D13, D25, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
CMP W10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45bfc0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X11, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK X9, #16325	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X11, #16357	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV D11, X9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D12, X11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR W12, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X22, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X23, [X19, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X23, W10,UXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
STR X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [X19, #784]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X20, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X12, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STR W12, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X21, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X28, X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.01% of application time for run gcc_0

Source file and lines	einspline_spo_ref.hpp:172-189
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineRef.hpp:42-49,57-71
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/CrystalLattice.h:170-173
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/Tensor.h:213
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVectorTensorOps.h:150-152
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/einspline_spo_ref.hpp:172-189
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algo.h:683,709
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:229
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineEvalHelper.hpp:53,60-63
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:143
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/Spline2/MultiBsplineData.hpp:54-57
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238,413,451-452,951-952

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 10.88 to 4.17 cycles (2.61x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

38% of VPU loads are used in vector version.
26% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU multiply instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 10.88 to 0.50 cycles (21.75x speedup).

FMA

Detected 6 FMA (fused multiply-add) operations. Presence of both ADD/SUB and MUL operations.

Workaround

Matching between your function (in the source code) and the binary function

The binary function is composed of 18 FP arithmetical operations:

9: addition or subtraction (6 inside FMA instructions)
9: multiply (6 inside FMA instructions)

The binary function is loading 140 bytes. The binary function is storing 204 bytes.

Arithmetic intensity

Arithmetic intensity is 0.05 FP operations per loaded or stored byte.

General properties

nb instructions	90
loop length	360
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

10.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	8.25	8.25	8.25	8.25	9.83	9.50	9.67	5.00	5.00
cycles	1.50	1.50	4.83	4.83	4.83	4.83	4.83	4.83	8.25	8.25	8.25	8.25	9.83	9.50	9.67	5.00	5.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	10.88
Overall L1	10.88

Vectorization ratios

INT

all	19%
load	38%
store	26%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	12%
load	38%
store	26%
mul	0%
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 10.88 cycles. At this rate:

13% of peak load performance is reached (12.87 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
39% of peak store performance is reached (18.76 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 45b980

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #736]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W20, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X28, [X0, #856]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR X0, XZR, X28	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d5540 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE5startEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W0, [X21, #292]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X3, X21, #296	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
CMP W20, W0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 45b9d4 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x54>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X2, [X21, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
MOVZ W1, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
SMADDL X3, W20, W1, X2	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
ADD X4, X19, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDP D25, D31, [X3]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
MOVI D27, #0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ X5, #48304	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDP D29, D30, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMOV D28, X5	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
LDR D24, [X19, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR D26, [X3, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
FMUL D0, D31, D29	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D21, D4, [X4, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMUL D1, D31, D30	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDP D20, D23, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDP D22, D6, [X4, #56]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
FMADD D3, D25, D24, D0	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMUL D7, D31, D21	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	3	0.25	scal (50.0%)
LDR W10, [X19, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
FMADD D2, D25, D20, D1	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D5, D26, D4, D3	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D14, D5	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D13, D25, D23, D7	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FMADD D12, D26, D22, D2	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D15, D12	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FMADD D17, D26, D6, D13	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	4	0.25	scal (50.0%)
FRINTM D18, D17	1	0	0	0	0	0	0	0	0	0.50	0	0.50	0	0	0	0	0	0	3	0.50	scal (50.0%)
FCMPE D5, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FSUB D16, D5, S14	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB D19, D12, S15	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FSUB D25, D17, S18	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FCCMPE D5, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W6, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W6, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D14, D16, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D12, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
FCCMPE D12, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W7, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W7, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D31, D19, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
FCMPE D17, D27	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
STR D31, [SP, #184]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
FCCMPE D17, D28, #4, #4	1	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CSINC W8, WZR, WZR, #13	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W8, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
FCSEL D13, D25, D27, #0	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	2	0.25	scal (50.0%)
CMP W10, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 45bfc0 <_ZN16miniqmcreference17einspline_spo_refIdE8evaluateERKN11qmcplusplus11ParticleSetEiRNS2_6VectorIdSaIdEEE+0x640>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X9, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X11, XZR, #3840	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVK X9, #16325	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVK X11, #16357	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
FMOV D11, X9	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
FMOV D12, X11	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR W12, [X19, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
STR X22, [SP, #216]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X23, [X19, #760]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X13, X23, W10,UXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (50.0%)
STR X13, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X24, [X19, #784]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
SBFM X20, X12, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SBFM X25, X12, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
STR W12, [SP, #196]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X21, X20, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X28, X19, [SP, #200]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::einspline_spo_ref::evaluate(qmcplusplus::ParticleSet const&, int, qmcplusplus::Vector >&)–	22.35	30.96
▼Loop 1114 - einspline_spo_ref.hpp:175-189 - exec–	0.00	0.01
▼Loop 1112 - MultiBsplineRef.hpp:42-71 - exec–	0.00	0.01
○Loop 1113 - einspline_spo_ref.hpp:175-176 - exec	0.00	0.01
▼Loop 1109 - MultiBsplineRef.hpp:64-71 - exec–	0.00	0.00
○Loop 1111 - MultiBsplineRef.hpp:68-71 - exec	22.33	30.58
○Loop 1110 - MultiBsplineRef.hpp:63-63 - exec	0.00	0.00
○Loop 1115 - einspline_spo_ref.hpp:183-187 - exec	0.00	0.01

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Expensive FP math instructions/calls

FMA

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Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

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Cycles summary

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Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

FMA

Workaround

Matching between your function (in the source code) and the binary function

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code