OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::computeU3(qmcplusplus::ParticleSet const&, int, double const*, double*, double*, double*, bool)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::computeU3(qmcpl ...	Module: exec	Source: TwoBodyJastrowRef.h:254-279 [...]	Coverage (incl. loops): 0.16% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 1147 - 1150

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1147:       operator[](size_type __n) const _GLIBCXX_NOEXCEPT

1148:       {

1149: 	__glibcxx_requires_subscript(__n);

1150: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 223

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223:     return X[i];

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 254 - 279

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254: inline void TwoBodyJastrowRef<FT>::computeU3(const ParticleSet& P,

[...]

262:   const int jelmax = triangle ? iat : N;

[...]

268:   const int igt = P.GroupID[iat] * NumGroups;

269:   for (int jg = 0; jg < NumGroups; ++jg)

270:   {

271:     const FuncType& f2(*F[igt + jg]);

[...]

279: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

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313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h: 238 - 1151

--------------------------------------------------------------------------------

238:       if (__b < __a)

[...]

952: 	*__first = __tmp;

[...]

1146:       if (__n <= 0)

1147: 	return __first;

1148:

1149:       __glibcxx_requires_can_increment(__first, __n);

1150:

1151:       std::__fill_a(__first, __first + __n, __value);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 276 - 336

--------------------------------------------------------------------------------

276:   real_type dSquareDeltaRinv = DeltaRInv * DeltaRInv;

277:   constexpr real_type cOne(1);

278:

279:   //    START_MARK_FIRST();

280:

281:   ASSUME_ALIGNED(distIndices);

282:   ASSUME_ALIGNED(distArrayCompressed);

283:   int iCount                 = 0;

284:   int iLimit                 = iEnd - iStart;

[...]

291:   for (int jat = 0; jat < iLimit; jat++)

292:   {

293:     real_type r = distArray[jat];

294:     if (r < cutoff_radius && iStart + jat != iat)

295:     {

296:       distIndices[iCount]         = jat;

297:       distArrayCompressed[iCount] = r;

298:       iCount++;

[...]

305:     real_type r    = distArrayCompressed[j];

306:     int iScatter   = distIndices[j];

307:     real_type rinv = cOne / r;

308:     r *= DeltaRInv;

309:     int iGather   = (int)r;

310:     real_type t   = r - real_type(iGather);

311:     real_type tp0 = t * t * t;

312:     real_type tp1 = t * t;

313:     real_type tp2 = t;

314:

315:     real_type sCoef0 = SplineCoefs[iGather + 0];

316:     real_type sCoef1 = SplineCoefs[iGather + 1];

317:     real_type sCoef2 = SplineCoefs[iGather + 2];

318:     real_type sCoef3 = SplineCoefs[iGather + 3];

319:

320:     // clang-format off

321:     laplArray[iScatter] = dSquareDeltaRinv *

322:       (sCoef0*( d2A[ 2]*tp2 + d2A[ 3])+

323:        sCoef1*( d2A[ 6]*tp2 + d2A[ 7])+

324:        sCoef2*( d2A[10]*tp2 + d2A[11])+

325:        sCoef3*( d2A[14]*tp2 + d2A[15]));

326:

327:     gradArray[iScatter] = DeltaRInv * rinv *

328:       (sCoef0*( dA[ 1]*tp1 + dA[ 2]*tp2 + dA[ 3])+

329:        sCoef1*( dA[ 5]*tp1 + dA[ 6]*tp2 + dA[ 7])+

330:        sCoef2*( dA[ 9]*tp1 + dA[10]*tp2 + dA[11])+

331:        sCoef3*( dA[13]*tp1 + dA[14]*tp2 + dA[15]));

332:

333:     valArray[iScatter] = (sCoef0*(A[ 0]*tp0 + A[ 1]*tp1 + A[ 2]*tp2 + A[ 3])+

334:         sCoef1*(A[ 4]*tp0 + A[ 5]*tp1 + A[ 6]*tp2 + A[ 7])+

335:         sCoef2*(A[ 8]*tp0 + A[ 9]*tp1 + A[10]*tp2 + A[11])+

336:         sCoef3*(A[12]*tp0 + A[13]*tp1 + A[14]*tp2 + A[15]));

0x43bca0 ADDVL	SP, SP, #62

0x43bca4 SUB	SP, SP, #1088

0x43bca8 STP	X29, X30, [SP]

0x43bcac ADD	X29, SP, #0

0x43bcb0 STP	X19, X20, [SP, #16]

0x43bcb4 ORR	W19, WZR, W2

0x43bcb8 ORR	W20, WZR, W2

0x43bcbc STP	X21, X22, [SP, #32]

0x43bcc0 ORR	X21, XZR, X0

0x43bcc4 ORR	X22, XZR, X3

0x43bcc8 STP	X23, X24, [SP, #48]

0x43bccc ORR	X24, XZR, X5

0x43bcd0 ORR	X23, XZR, X6

0x43bcd4 STP	X25, X26, [SP, #64]

0x43bcd8 ORR	X26, XZR, X1

0x43bcdc ORR	X25, XZR, X4

0x43bce0 STP	X27, X28, [SP, #80]

0x43bce4 TBNZ	W7, #0, 43bcec

0x43bce8 LDR	W20, [X0, #144]

0x43bcec CMP	W20, #0

0x43bcf0 B.LE	43bd28

0x43bcf4 UBFM	X27, X20, #61, #31

0x43bcf8 MOVZ	W1, #0

0x43bcfc ORR	X2, XZR, X27

0x43bd00 ORR	X0, XZR, X25

0x43bd04 BL	403ea0

0x43bd08 ORR	X2, XZR, X27

0x43bd0c MOVZ	W1, #0

0x43bd10 ORR	X0, XZR, X24

0x43bd14 BL	403ea0

0x43bd18 ORR	X2, XZR, X27

0x43bd1c ORR	X0, XZR, X23

0x43bd20 MOVZ	W1, #0

0x43bd24 BL	403ea0

0x43bd28 LDR	X0, [X26, #24]

0x43bd2c LDR	X16, [X21, #160]

0x43bd30 LDR	W1, [X0, X19,SXTW #2]

0x43bd34 MADD	W3, W1, W16, WZR

0x43bd38 CBZ	X16, 43caf0

0x43bd3c STP	D8, D9, [SP, #96]

0x43bd40 MOVZ	X2, #0

0x43bd44 PTRUE	P7.B, ALL

0x43bd48 STP	D10, D11, [SP, #112]

0x43bd4c STP	D12, D13, [SP, #128]

0x43bd50 STP	D14, D15, [SP, #144]

0x43bd54 LDR	X4, [X26, #616]

0x43bd58 LDR	X13, [X21, #464]

0x43bd5c LDR	X12, [X21, #488]

0x43bd60 LDR	X14, [X4, #24]

0x43bd64 LDR	X5, [X21, #512]

0x43bd68 ADD	X15, X5, W3,SXTW #3

    (676) 0x43bd6c LDR	X9, [X15, X2,LSL #3]

    (676) 0x43bd70 LDR	W10, [X14, X2,LSL #2]

    (676) 0x43bd74 ADD	X2, X2, #1

    (676) 0x43bd78 LDR	W6, [X14, X2,LSL #2]

    (676) 0x43bd7c LDR	D31, [X9, #568]

    (676) 0x43bd80 CMP	W6, W20

    (676) 0x43bd84 CSEL	W7, W6, W20, #13

    (676) 0x43bd88 SUB	W8, W7, W10

    (676) 0x43bd8c FMUL	D30, D31, D31

    (676) 0x43bd90 CMP	W8, #0

    (676) 0x43bd94 B.LE	43cad8

    (676) 0x43bd98 SBFM	X17, X10, #61, #31

    (676) 0x43bd9c ANDS	X18, X8, #4224

    (676) 0x43bda0 LDR	D29, [X9, #8]

    (676) 0x43bda4 MOVZ	X0, #0

    (676) 0x43bda8 MOVZ	W11, #0

    (676) 0x43bdac ADD	X28, X22, X17

    (676) 0x43bdb0 SBFM	X30, X8, #0, #31

    (676) 0x43bdb4 B.EQ	43bef0

    (676) 0x43bdb8 CMP	X18, #1

    (676) 0x43bdbc B.EQ	43bec0

    (676) 0x43bdc0 CMP	X18, #2

    (676) 0x43bdc4 B.EQ	43be98

    (676) 0x43bdc8 CMP	X18, #3

    (676) 0x43bdcc B.EQ	43be70

    (676) 0x43bdd0 CMP	X18, #4

    (676) 0x43bdd4 B.EQ	43be48

    (676) 0x43bdd8 CMP	X18, #5

    (676) 0x43bddc B.EQ	43be20

    (676) 0x43bde0 CMP	X18, #6

    (676) 0x43bde4 B.EQ	43bdf8

    (676) 0x43bde8 LDR	D28, [X22, X17]

    (676) 0x43bdec FCMPE	D29, D28

    (676) 0x43bdf0 B.GT	43cb28

    (676) 0x43bdf4 MOVZ	X0, #1

    (676) 0x43bdf8 LDR	D0, [X28, X0,LSL #3]

    (676) 0x43bdfc FCMPE	D29, D0

    (676) 0x43be00 B.LS	43be1c

    (676) 0x43be04 ADD	W26, W10, W0

    (676) 0x43be08 CMP	W19, W26

    (676) 0x43be0c B.EQ	43be1c

    (676) 0x43be10 STR	W0, [X12, X11,UXTW #2]

    (676) 0x43be14 STR	D0, [X13, X11,UXTW #3]

    (676) 0x43be18 ADD	W11, W11, #1

    (676) 0x43be1c ADD	X0, X0, #1

    (676) 0x43be20 LDR	D1, [X28, X0,LSL #3]

    (676) 0x43be24 FCMPE	D29, D1

    (676) 0x43be28 B.LS	43be44

    (676) 0x43be2c ADD	W27, W10, W0

    (676) 0x43be30 CMP	W19, W27

    (676) 0x43be34 B.EQ	43be44

    (676) 0x43be38 STR	W0, [X12, X11,UXTW #2]

    (676) 0x43be3c STR	D1, [X13, X11,UXTW #3]

    (676) 0x43be40 ADD	W11, W11, #1

    (676) 0x43be44 ADD	X0, X0, #1

    (676) 0x43be48 LDR	D2, [X28, X0,LSL #3]

    (676) 0x43be4c FCMPE	D29, D2

    (676) 0x43be50 B.LS	43be6c

    (676) 0x43be54 ADD	W1, W10, W0

    (676) 0x43be58 CMP	W19, W1

    (676) 0x43be5c B.EQ	43be6c

    (676) 0x43be60 STR	W0, [X12, X11,UXTW #2]

    (676) 0x43be64 STR	D2, [X13, X11,UXTW #3]

    (676) 0x43be68 ADD	W11, W11, #1

    (676) 0x43be6c ADD	X0, X0, #1

    (676) 0x43be70 LDR	D3, [X28, X0,LSL #3]

    (676) 0x43be74 FCMPE	D29, D3

    (676) 0x43be78 B.LS	43be94

    (676) 0x43be7c ADD	W3, W10, W0

    (676) 0x43be80 CMP	W19, W3

    (676) 0x43be84 B.EQ	43be94

    (676) 0x43be88 STR	W0, [X12, X11,UXTW #2]

    (676) 0x43be8c STR	D3, [X13, X11,UXTW #3]

    (676) 0x43be90 ADD	W11, W11, #1

    (676) 0x43be94 ADD	X0, X0, #1

    (676) 0x43be98 LDR	D4, [X28, X0,LSL #3]

    (676) 0x43be9c FCMPE	D29, D4

    (676) 0x43bea0 B.LS	43bebc

    (676) 0x43bea4 ADD	W4, W10, W0

    (676) 0x43bea8 CMP	W19, W4

    (676) 0x43beac B.EQ	43bebc

    (676) 0x43beb0 STR	W0, [X12, X11,UXTW #2]

    (676) 0x43beb4 STR	D4, [X13, X11,UXTW #3]

    (676) 0x43beb8 ADD	W11, W11, #1

    (676) 0x43bebc ADD	X0, X0, #1

    (676) 0x43bec0 LDR	D5, [X28, X0,LSL #3]

    (676) 0x43bec4 FCMPE	D29, D5

    (676) 0x43bec8 B.LS	43bee4

    (676) 0x43becc ADD	W5, W10, W0

    (676) 0x43bed0 CMP	W19, W5

    (676) 0x43bed4 B.EQ	43bee4

    (676) 0x43bed8 STR	W0, [X12, X11,UXTW #2]

    (676) 0x43bedc STR	D5, [X13, X11,UXTW #3]

    (676) 0x43bee0 ADD	W11, W11, #1

    (676) 0x43bee4 ADD	X0, X0, #1

    (676) 0x43bee8 CMP	X0, X30

    (676) 0x43beec B.EQ	43c038

      (677) 0x43bef0 LDR	D6, [X28, X0,LSL #3]

      (677) 0x43bef4 FCMPE	D29, D6

      (677) 0x43bef8 B.LS	43bf14

      (677) 0x43befc ADD	W6, W10, W0

      (677) 0x43bf00 CMP	W19, W6

      (677) 0x43bf04 B.EQ	43bf14

      (677) 0x43bf08 STR	W0, [X12, X11,UXTW #2]

      (677) 0x43bf0c STR	D6, [X13, X11,UXTW #3]

      (677) 0x43bf10 ADD	W11, W11, #1

      (677) 0x43bf14 ADD	X0, X0, #1

      (677) 0x43bf18 LDR	D7, [X28, X0,LSL #3]

      (677) 0x43bf1c FCMPE	D29, D7

      (677) 0x43bf20 B.LS	43bf3c

      (677) 0x43bf24 ADD	W7, W10, W0

      (677) 0x43bf28 CMP	W19, W7

      (677) 0x43bf2c B.EQ	43bf3c

      (677) 0x43bf30 STR	W0, [X12, X11,UXTW #2]

      (677) 0x43bf34 STR	D7, [X13, X11,UXTW #3]

      (677) 0x43bf38 ADD	W11, W11, #1

      (677) 0x43bf3c ADD	X18, X0, #1

      (677) 0x43bf40 LDR	D8, [X28, X18,LSL #3]

      (677) 0x43bf44 FCMPE	D29, D8

      (677) 0x43bf48 B.LS	43bf64

      (677) 0x43bf4c ADD	W8, W10, W18

      (677) 0x43bf50 CMP	W19, W8

      (677) 0x43bf54 B.EQ	43bf64

      (677) 0x43bf58 STR	W18, [X12, X11,UXTW #2]

      (677) 0x43bf5c STR	D8, [X13, X11,UXTW #3]

      (677) 0x43bf60 ADD	W11, W11, #1

      (677) 0x43bf64 ADD	X21, X0, #2

      (677) 0x43bf68 LDR	D9, [X28, X21,LSL #3]

      (677) 0x43bf6c FCMPE	D29, D9

      (677) 0x43bf70 B.LS	43bf8c

      (677) 0x43bf74 ADD	W26, W10, W21

      (677) 0x43bf78 CMP	W19, W26

      (677) 0x43bf7c B.EQ	43bf8c

      (677) 0x43bf80 STR	W21, [X12, X11,UXTW #2]

      (677) 0x43bf84 STR	D9, [X13, X11,UXTW #3]

      (677) 0x43bf88 ADD	W11, W11, #1

      (677) 0x43bf8c ADD	X27, X0, #3

      (677) 0x43bf90 LDR	D10, [X28, X27,LSL #3]

      (677) 0x43bf94 FCMPE	D29, D10

      (677) 0x43bf98 B.LS	43bfb4

      (677) 0x43bf9c ADD	W1, W10, W27

      (677) 0x43bfa0 CMP	W19, W1

      (677) 0x43bfa4 B.EQ	43bfb4

      (677) 0x43bfa8 STR	W27, [X12, X11,UXTW #2]

      (677) 0x43bfac STR	D10, [X13, X11,UXTW #3]

      (677) 0x43bfb0 ADD	W11, W11, #1

      (677) 0x43bfb4 ADD	X3, X0, #4

      (677) 0x43bfb8 LDR	D11, [X28, X3,LSL #3]

      (677) 0x43bfbc FCMPE	D29, D11

      (677) 0x43bfc0 B.LS	43bfdc

      (677) 0x43bfc4 ADD	W4, W10, W3

      (677) 0x43bfc8 CMP	W19, W4

      (677) 0x43bfcc B.EQ	43bfdc

      (677) 0x43bfd0 STR	W3, [X12, X11,UXTW #2]

      (677) 0x43bfd4 STR	D11, [X13, X11,UXTW #3]

      (677) 0x43bfd8 ADD	W11, W11, #1

      (677) 0x43bfdc ADD	X5, X0, #5

      (677) 0x43bfe0 LDR	D12, [X28, X5,LSL #3]

      (677) 0x43bfe4 FCMPE	D29, D12

      (677) 0x43bfe8 B.LS	43c004

      (677) 0x43bfec ADD	W6, W10, W5

      (677) 0x43bff0 CMP	W19, W6

      (677) 0x43bff4 B.EQ	43c004

      (677) 0x43bff8 STR	W5, [X12, X11,UXTW #2]

      (677) 0x43bffc STR	D12, [X13, X11,UXTW #3]

      (677) 0x43c000 ADD	W11, W11, #1

      (677) 0x43c004 ADD	X7, X0, #6

      (677) 0x43c008 LDR	D13, [X28, X7,LSL #3]

      (677) 0x43c00c FCMPE	D29, D13

      (677) 0x43c010 B.LS	43c02c

      (677) 0x43c014 ADD	W18, W10, W7

      (677) 0x43c018 CMP	W19, W18

      (677) 0x43c01c B.EQ	43c02c

      (677) 0x43c020 STR	W7, [X12, X11,UXTW #2]

      (677) 0x43c024 STR	D13, [X13, X11,UXTW #3]

      (677) 0x43c028 ADD	W11, W11, #1

      (677) 0x43c02c ADD	X0, X0, #7

      (677) 0x43c030 CMP	X0, X30

      (677) 0x43c034 B.NE	43bef0

    (676) 0x43c038 CBZ	W11, 43cad8

    (676) 0x43c03c LDP	X28, X30, [X9, #24]

    (676) 0x43c040 SUB	W10, W11, #1

    (676) 0x43c044 LDR	D20, [X9, #176]

    (676) 0x43c048 STR	X28, [SP, #776]

    (676) 0x43c04c STR	X30, [SP, #784]

    (676) 0x43c050 LDP	X8, X21, [X9, #40]

    (676) 0x43c054 LDR	D18, [X9, #208]

    (676) 0x43c058 STR	X8, [SP, #792]

    (676) 0x43c05c STR	X21, [SP, #800]

    (676) 0x43c060 LDP	X26, X27, [X9, #56]

    (676) 0x43c064 STR	X26, [SP, #808]

    (676) 0x43c068 STR	X27, [SP, #816]

    (676) 0x43c06c LDP	X1, X3, [X9, #72]

    (676) 0x43c070 STR	X1, [SP, #824]

    (676) 0x43c074 STR	X3, [SP, #832]

    (676) 0x43c078 LDP	X5, X4, [X9, #88]

    (676) 0x43c07c STR	X5, [SP, #840]

    (676) 0x43c080 STR	X4, [SP, #848]

    (676) 0x43c084 LDP	D28, D15, [X9, #160]

    (676) 0x43c088 STR	D20, [SP, #1064]

    (676) 0x43c08c STR	D28, [SP, #1056]

    (676) 0x43c090 LDP	D17, D19, [X9, #192]

    (676) 0x43c094 STR	D17, [SP, #1072]

    (676) 0x43c098 LDP	X6, X7, [X9, #224]

    (676) 0x43c09c STR	X7, [SP, #752]

    (676) 0x43c0a0 STR	X6, [SP, #744]

    (676) 0x43c0a4 LDR	D14, [X9, #240]

    (676) 0x43c0a8 LDR	D16, [X9, #272]

    (676) 0x43c0ac STR	D14, [SP, #1080]

    (676) 0x43c0b0 LDP	X18, X0, [X9, #256]

    (676) 0x43c0b4 STR	X18, [SP, #760]

    (676) 0x43c0b8 STR	X0, [SP, #768]

    (676) 0x43c0bc LDP	X28, X30, [X9, #104]

    (676) 0x43c0c0 LDP	D24, D23, [X9, #296]

    (676) 0x43c0c4 LDP	D29, D27, [X9, #328]

    (676) 0x43c0c8 LDP	D22, D21, [X9, #360]

    (676) 0x43c0cc LDP	D26, D25, [X9, #392]

    (676) 0x43c0d0 STR	X28, [SP, #856]

    (676) 0x43c0d4 STR	X30, [SP, #864]

    (676) 0x43c0d8 LDP	X8, X21, [X9, #120]

    (676) 0x43c0dc LDR	X0, [X9, #536]

    (676) 0x43c0e0 STR	X8, [SP, #872]

    (676) 0x43c0e4 STR	X21, [SP, #880]

    (676) 0x43c0e8 LDP	X9, X26, [X9, #136]

    (676) 0x43c0ec STR	X9, [SP, #888]

    (676) 0x43c0f0 STR	X26, [SP, #896]

    (676) 0x43c0f4 CMP	W10, #2

    (676) 0x43c0f8 B.LS	43cb14

    (676) 0x43c0fc DUP	V5.2D, V20.D[0]

    (676) 0x43c100 LDR	D20, [SP, #744]

    (676) 0x43c104 DUP	V0.2D, V24.D[0]

    (676) 0x43c108 ADD	X9, X23, X17

    (676) 0x43c10c ADD	X8, X24, X17

    (676) 0x43c110 DUP	V1.2D, V28.D[0]

    (676) 0x43c114 DUP	V9.2D, V22.D[0]

    (676) 0x43c118 ADD	X7, X25, X17

    (676) 0x43c11c ORR	X4, XZR, X12

    (676) 0x43c120 DUP	V11.2D, V21.D[0]

    (676) 0x43c124 DUP	V3.2D, V15.D[0]

    (676) 0x43c128 UBFM	W17, W11, #2, #31

    (676) 0x43c12c ADD	X28, X12, W17,UXTW #4

    (676) 0x43c130 ORR	X10, XZR, X13

    (676) 0x43c134 DUP	V13.2D, V26.D[0]

    (676) 0x43c138 DUP	V2.2D, V23.D[0]

    (676) 0x43c13c STR	Q0, [SP, #160]

    (676) 0x43c140 DUP	V4.2D, V29.D[0]

    (676) 0x43c144 DUP	V7.2D, V27.D[0]

    (676) 0x43c148 LDR	D0, [SP, #752]

    (676) 0x43c14c DUP	V8.2D, V17.D[0]

    (676) 0x43c150 DUP	V10.2D, V19.D[0]

    (676) 0x43c154 DUP	V28.2D, V20.D[0]

    (676) 0x43c158 STR	Q3, [SP, #272]

    (676) 0x43c15c DUP	V12.2D, V18.D[0]

    (676) 0x43c160 LDR	D3, [SP, #760]

    (676) 0x43c164 DUP	V17.2D, V25.D[0]

    (676) 0x43c168 DUP	V14.2D, V14.D[0]

    (676) 0x43c16c STR	Q13, [SP, #224]

    (676) 0x43c170 DUP	V6.2D, V31.D[0]

    (676) 0x43c174 LDR	D13, [SP, #792]

    (676) 0x43c178 STR	Q5, [SP, #288]

    (676) 0x43c17c LDR	D5, [SP, #768]

    (676) 0x43c180 STR	Q28, [SP, #352]

    (676) 0x43c184 LDR	D28, [SP, #800]

    (676) 0x43c188 STR	Q9, [SP, #544]

    (676) 0x43c18c LDR	D9, [SP, #776]

    (676) 0x43c190 DUP	V20.2D, V13.D[0]

    (676) 0x43c194 STR	Q11, [SP, #560]

    (676) 0x43c198 LDR	D11, [SP, #784]

    (676) 0x43c19c STR	Q1, [SP, #256]

    (676) 0x43c1a0 DUP	V1.2D, V0.D[0]

    (676) 0x43c1a4 STR	Q2, [SP, #176]

    (676) 0x43c1a8 DUP	V2.2D, V30.D[0]

    (676) 0x43c1ac STR	Q4, [SP, #192]

    (676) 0x43c1b0 DUP	V4.2D, V3.D[0]

    (676) 0x43c1b4 STR	Q7, [SP, #208]

    (676) 0x43c1b8 DUP	V7.2D, V5.D[0]

    (676) 0x43c1bc STR	Q8, [SP, #304]

    (676) 0x43c1c0 DUP	V8.2D, V16.D[0]

    (676) 0x43c1c4 STR	Q10, [SP, #320]

    (676) 0x43c1c8 DUP	V10.2D, V9.D[0]

    (676) 0x43c1cc STR	Q12, [SP, #336]

    (676) 0x43c1d0 DUP	V12.2D, V11.D[0]

    (676) 0x43c1d4 STP	Q17, Q1, [SP, #576]

    (676) 0x43c1d8 DUP	V17.2D, V28.D[0]

    (676) 0x43c1dc STR	Q2, [SP, #240]

    (676) 0x43c1e0 STR	Q4, [SP, #368]

    (676) 0x43c1e4 STR	Q10, [SP, #384]

    (676) 0x43c1e8 STR	Q12, [SP, #400]

    (676) 0x43c1ec STR	Q14, [SP, #608]

    (676) 0x43c1f0 STR	Q7, [SP, #624]

    (676) 0x43c1f4 STR	Q8, [SP, #640]

    (676) 0x43c1f8 STR	Q20, [SP, #656]

    (676) 0x43c1fc STR	Q17, [SP, #672]

    (676) 0x43c200 STR	X16, [SP, #904]

    (676) 0x43c204 ADD	X16, SP, #1000

    (676) 0x43c208 STR	X12, [SP, #920]

    (676) 0x43c20c ADD	X12, SP, #936

    (676) 0x43c210 STR	W20, [SP, #916]

    (676) 0x43c214 STR	X13, [SP, #928]

    (676) 0x43c218 ADD	X13, SP, #968

    (676) 0x43c21c STP	D31, D30, [X12]

    (676) 0x43c220 STP	D24, D23, [X12, #16]

    (676) 0x43c224 STP	D29, D27, [X13]

    (676) 0x43c228 STP	D22, D21, [X13, #16]

    (676) 0x43c22c LDR	D0, [SP, #840]

    (676) 0x43c230 FMOV	D9, X21

    (676) 0x43c234 LDR	D31, [SP, #808]

    (676) 0x43c238 LDR	D24, [SP, #816]

    (676) 0x43c23c LDR	D29, [SP, #824]

    (676) 0x43c240 DUP	V1.2D, V0.D[0]

    (676) 0x43c244 LDR	D22, [SP, #832]

    (676) 0x43c248 DUP	V30.2D, V31.D[0]

    (676) 0x43c24c LDR	D2, [SP, #848]

    (676) 0x43c250 DUP	V23.2D, V24.D[0]

    (676) 0x43c254 STR	Q1, [SP, #448]

    (676) 0x43c258 DUP	V1.2D, V9.D[0]

    (676) 0x43c25c LDR	D3, [SP, #856]

    (676) 0x43c260 DUP	V27.2D, V29.D[0]

    (676) 0x43c264 STR	Q30, [SP, #416]

    (676) 0x43c268 LDR	D7, [SP, #872]

    (676) 0x43c26c DUP	V21.2D, V22.D[0]

    (676) 0x43c270 STR	Q23, [SP, #432]

    (676) 0x43c274 LDR	D10, [SP, #888]

    (676) 0x43c278 DUP	V14.2D, V2.D[0]

    (676) 0x43c27c STR	Q27, [SP, #688]

    (676) 0x43c280 LDR	D5, [SP, #864]

    (676) 0x43c284 DUP	V4.2D, V3.D[0]

    (676) 0x43c288 STR	Q21, [SP, #704]

    (676) 0x43c28c LDR	D12, [SP, #896]

    (676) 0x43c290 DUP	V8.2D, V7.D[0]

    (676) 0x43c294 STR	Q14, [SP, #720]

    (676) 0x43c298 DUP	V11.2D, V10.D[0]

    (676) 0x43c29c STR	Q4, [SP, #464]

    (676) 0x43c2a0 DUP	V0.2D, V5.D[0]

    (676) 0x43c2a4 STR	Q8, [SP, #480]

    (676) 0x43c2a8 DUP	V17.2D, V12.D[0]

    (676) 0x43c2ac STR	Q11, [SP, #496]

    (676) 0x43c2b0 STP	D26, D25, [X16]

    (676) 0x43c2b4 STP	D15, D19, [X16, #16]

    (676) 0x43c2b8 STR	D18, [SP, #1032]

    (676) 0x43c2bc STR	D16, [SP, #1040]

    (676) 0x43c2c0 STR	X2, [SP, #1048]

      (679) 0x43c2c4 LDP	Q18, Q15, [X10], #32

      (679) 0x43c2c8 MOVI	V20.4S, #2

      (679) 0x43c2cc MOVI	V28.4S, #3

      (679) 0x43c2d0 MOVI	V23.4S, #1

      (679) 0x43c2d4 LDP	W2, W20, [X4, #4]

      (679) 0x43c2d8 ADD	X4, X4, #16

      (679) 0x43c2dc SBFM	X1, X2, #61, #31

      (679) 0x43c2e0 SBFM	X5, X20, #61, #31

      (679) 0x43c2e4 ADD	X17, X9, X1

      (679) 0x43c2e8 ADD	X13, X1, X8

      (679) 0x43c2ec FMUL	V19.2D, V18.2D, V6.2D

      (679) 0x43c2f0 ADD	X3, X1, X7

      (679) 0x43c2f4 FMUL	V31.2D, V15.2D, V6.2D

      (679) 0x43c2f8 FDIV	V29.2D, V6.2D, V15.2D

      (679) 0x43c2fc LDR	Q15, [SP, #224]

      (679) 0x43c300 FDIV	V7.2D, V6.2D, V18.2D

      (679) 0x43c304 FCVTZS	V16.2D, V19.2D

      (679) 0x43c308 FCVTZS	V25.2D, V31.2D

      (679) 0x43c30c STR	Q29, [SP, #512]

      (679) 0x43c310 FRINTZ	V26.2D, V19.2D

      (679) 0x43c314 FRINTZ	V29.2D, V31.2D

      (679) 0x43c318 UZP1	V13.4S, V16.4S, V25.4S

      (679) 0x43c31c FSUB	V30.2D, V19.2D, V26.2D

      (679) 0x43c320 FSUB	V31.2D, V31.2D, V29.2D

      (679) 0x43c324 ADD	V24.4S, V13.4S, V20.4S

      (679) 0x43c328 ADD	V22.4S, V13.4S, V28.4S

      (679) 0x43c32c ADD	V27.4S, V13.4S, V23.4S

      (679) 0x43c330 SSHLL	V21.2D, V13.2S, #32

      (679) 0x43c334 SSHLL2	V20.2D, V13.4S, #32

      (679) 0x43c338 FMUL	V29.2D, V30.2D, V30.2D

      (679) 0x43c33c SSHLL	V2.2D, V24.2S, #32

      (679) 0x43c340 SSHLL	V14.2D, V22.2S, #32

      (679) 0x43c344 FMOV	X6, D21

      (679) 0x43c348 SSHLL2	V4.2D, V22.4S, #32

      (679) 0x43c34c MOV	X21, V21.D[1]

      (679) 0x43c350 SSHLL	V5.2D, V27.2S, #32

      (679) 0x43c354 MOV	X18, V20.D[1]

      (679) 0x43c358 MOV	X27, V2.D[1]

      (679) 0x43c35c SSHLL2	V22.2D, V27.4S, #32

      (679) 0x43c360 FMOV	X2, D14

      (679) 0x43c364 SSHLL2	V3.2D, V24.4S, #32

      (679) 0x43c368 MOV	X26, V4.D[1]

      (679) 0x43c36c MOV	X1, V5.D[1]

      (679) 0x43c370 MOV	X12, V14.D[1]

      (679) 0x43c374 LDR	Q27, [SP, #640]

      (679) 0x43c378 MOV	X30, V3.D[1]

      (679) 0x43c37c LDR	D8, [X0, X27,LSL #3]

      (679) 0x43c380 FMOV	X27, D4

      (679) 0x43c384 LDR	D12, [X0, X2,LSL #3]

      (679) 0x43c388 FMOV	X2, D5

      (679) 0x43c38c LDP	Q5, Q4, [SP, #576]

      (679) 0x43c390 ORR	V26.16B, V27.16B, V27.16B

      (679) 0x43c394 FMOV	X16, D2

      (679) 0x43c398 LDP	Q21, Q14, [SP, #608]

      (679) 0x43c39c MOV	X20, V22.D[1]

      (679) 0x43c3a0 LDR	D9, [X0, X12,LSL #3]

      (679) 0x43c3a4 LDR	D18, [X0, X6,LSL #3]

      (679) 0x43c3a8 FMOV	X6, D3

      (679) 0x43c3ac LDP	Q19, Q24, [SP, #352]

      (679) 0x43c3b0 ORR	V23.16B, V5.16B, V5.16B

      (679) 0x43c3b4 LDR	D16, [X0, X1,LSL #3]

      (679) 0x43c3b8 MOV	V12.D[1], V9.D[0]

      (679) 0x43c3bc FMLA	V26.2D, V30.2D, V14.2D

      (679) 0x43c3c0 ORR	V25.16B, V21.16B, V21.16B

      (679) 0x43c3c4 LDR	D9, [X0, X30,LSL #3]

      (679) 0x43c3c8 FMOV	X30, D20

      (679) 0x43c3cc FMLA	V23.2D, V30.2D, V15.2D

      (679) 0x43c3d0 LDR	D15, [X0, X2,LSL #3]

      (679) 0x43c3d4 FMOV	X2, D22

      (679) 0x43c3d8 LDR	D10, [X0, X16,LSL #3]

      (679) 0x43c3dc FMLA	V25.2D, V30.2D, V4.2D

      (679) 0x43c3e0 LDR	D13, [X0, X6,LSL #3]

      (679) 0x43c3e4 FMLA	V26.2D, V29.2D, V24.2D

      (679) 0x43c3e8 LDR	Q24, [SP, #368]

      (679) 0x43c3ec MOV	V15.D[1], V16.D[0]

      (679) 0x43c3f0 LDR	D28, [X0, X27,LSL #3]

      (679) 0x43c3f4 MOV	V10.D[1], V8.D[0]

      (679) 0x43c3f8 FMUL	V22.2D, V31.2D, V31.2D

      (679) 0x43c3fc FMLA	V27.2D, V31.2D, V14.2D

      (679) 0x43c400 LDR	D16, [X0, X26,LSL #3]

      (679) 0x43c404 MOV	V13.D[1], V9.D[0]

      (679) 0x43c408 LDR	D20, [X0, X30,LSL #3]

      (679) 0x43c40c FMLA	V25.2D, V29.2D, V19.2D

      (679) 0x43c410 LDR	D19, [X0, X2,LSL #3]

      (679) 0x43c414 LDR	Q3, [SP, #352]

      (679) 0x43c418 FMLA	V21.2D, V31.2D, V4.2D

      (679) 0x43c41c MOV	V28.D[1], V16.D[0]

      (679) 0x43c420 LDP	Q2, Q8, [SP, #544]

      (679) 0x43c424 FMLA	V27.2D, V22.2D, V24.2D

      (679) 0x43c428 LDURSW	X12, [X4, #496]

      (679) 0x43c42c ORR	V24.16B, V5.16B, V5.16B

      (679) 0x43c430 LDUR	W16, [X4, #508]

      (679) 0x43c434 FMUL	V25.2D, V10.2D, V25.2D

      (679) 0x43c438 FMLA	V21.2D, V22.2D, V3.2D

      (679) 0x43c43c LDR	D4, [X0, X21,LSL #3]

      (679) 0x43c440 UBFM	X6, X12, #61, #60

      (679) 0x43c444 LDR	Q9, [SP, #224]

      (679) 0x43c448 FMUL	V3.2D, V29.2D, V1.2D

      (679) 0x43c44c ORR	V11.16B, V8.16B, V8.16B

      (679) 0x43c450 SBFM	X1, X16, #61, #31

      (679) 0x43c454 LDP	Q14, Q16, [SP, #320]

      (679) 0x43c458 ADD	X27, X9, X1

      (679) 0x43c45c ADD	X12, X1, X8

      (679) 0x43c460 FMUL	V26.2D, V12.2D, V26.2D

      (679) 0x43c464 ADD	X16, X1, X7

      (679) 0x43c468 MOV	V18.D[1], V4.D[0]

      (679) 0x43c46c LDR	Q4, [SP, #720]

      (679) 0x43c470 FMLA	V11.2D, V30.2D, V2.2D

      (679) 0x43c474 LDR	Q5, [SP, #448]

      (679) 0x43c478 FMLA	V24.2D, V31.2D, V9.2D

      (679) 0x43c47c LDR	D9, [X0, X20,LSL #3]

      (679) 0x43c480 FMLA	V16.2D, V30.2D, V14.2D

      (679) 0x43c484 ORR	V14.16B, V8.16B, V8.16B

      (679) 0x43c488 MOV	V19.D[1], V9.D[0]

      (679) 0x43c48c LDR	Q9, [SP, #304]

      (679) 0x43c490 FMUL	V8.2D, V30.2D, V29.2D

      (679) 0x43c494 FMUL	V11.2D, V10.2D, V11.2D

      (679) 0x43c498 FMLA	V14.2D, V31.2D, V2.2D

      (679) 0x43c49c FMLA	V16.2D, V29.2D, V9.2D

      (679) 0x43c4a0 STR	Q11, [SP, #528]

      (679) 0x43c4a4 LDR	Q11, [SP, #256]

      (679) 0x43c4a8 FMUL	V2.2D, V29.2D, V4.2D

      (679) 0x43c4ac FMUL	V4.2D, V22.2D, V4.2D

      (679) 0x43c4b0 FMLA	V25.2D, V15.2D, V16.2D

      (679) 0x43c4b4 LDR	Q16, [SP, #480]

      (679) 0x43c4b8 FMLA	V2.2D, V8.2D, V5.2D

      (679) 0x43c4bc LDR	D5, [X0, X18,LSL #3]

      (679) 0x43c4c0 FMLA	V3.2D, V8.2D, V16.2D

      (679) 0x43c4c4 LDP	Q9, Q16, [SP, #272]

      (679) 0x43c4c8 MOV	V20.D[1], V5.D[0]

      (679) 0x43c4cc LDR	Q5, [SP, #448]

      (679) 0x43c4d0 FMUL	V23.2D, V12.2D, V23.2D

      (679) 0x43c4d4 FMUL	V21.2D, V13.2D, V21.2D

      (679) 0x43c4d8 FMUL	V14.2D, V13.2D, V14.2D

      (679) 0x43c4dc FMUL	V24.2D, V28.2D, V24.2D

      (679) 0x43c4e0 FMUL	V27.2D, V28.2D, V27.2D

      (679) 0x43c4e4 FMLA	V16.2D, V30.2D, V9.2D

      (679) 0x43c4e8 FMUL	V9.2D, V31.2D, V22.2D

      (679) 0x43c4ec FMLA	V16.2D, V29.2D, V11.2D

      (679) 0x43c4f0 FMLA	V4.2D, V9.2D, V5.2D

      (679) 0x43c4f4 FMLA	V26.2D, V18.2D, V16.2D

      (679) 0x43c4f8 LDP	Q16, Q11, [SP, #464]

      (679) 0x43c4fc FMUL	V5.2D, V22.2D, V1.2D

      (679) 0x43c500 FADD	V25.2D, V26.2D, V25.2D

      (679) 0x43c504 FMLA	V5.2D, V9.2D, V11.2D

      (679) 0x43c508 FMUL	V26.2D, V25.2D, V7.2D

      (679) 0x43c50c LDR	Q7, [SP, #432]

      (679) 0x43c510 ORR	V25.16B, V0.16B, V0.16B

      (679) 0x43c514 FMLA	V25.2D, V30.2D, V16.2D

      (679) 0x43c518 FMUL	V16.2D, V29.2D, V7.2D

      (679) 0x43c51c LDP	Q11, Q7, [SP, #192]

      (679) 0x43c520 FADD	V2.2D, V25.2D, V2.2D

      (679) 0x43c524 FMLA	V7.2D, V30.2D, V11.2D

      (679) 0x43c528 FMUL	V25.2D, V2.2D, V10.2D

      (679) 0x43c52c LDR	Q10, [SP, #400]

      (679) 0x43c530 LDR	Q2, [SP, #496]

      (679) 0x43c534 FMUL	V29.2D, V29.2D, V10.2D

      (679) 0x43c538 LDP	Q11, Q10, [SP, #416]

      (679) 0x43c53c FMLA	V16.2D, V8.2D, V11.2D

      (679) 0x43c540 LDR	Q11, [SP, #384]

      (679) 0x43c544 FMLA	V29.2D, V8.2D, V11.2D

      (679) 0x43c548 LDR	Q11, [SP, #528]

      (679) 0x43c54c FMLA	V11.2D, V15.2D, V7.2D

      (679) 0x43c550 LDP	Q7, Q8, [SP, #160]

      (679) 0x43c554 FMLA	V8.2D, V30.2D, V7.2D

      (679) 0x43c558 ORR	V7.16B, V17.16B, V17.16B

      (679) 0x43c55c FMLA	V7.2D, V30.2D, V2.2D

      (679) 0x43c560 LDR	Q2, [SP, #464]

      (679) 0x43c564 FMLA	V23.2D, V18.2D, V8.2D

      (679) 0x43c568 ORR	V8.16B, V0.16B, V0.16B

      (679) 0x43c56c FMLA	V8.2D, V31.2D, V2.2D

      (679) 0x43c570 FADD	V3.2D, V3.2D, V7.2D

      (679) 0x43c574 FADD	V23.2D, V23.2D, V11.2D

      (679) 0x43c578 FMUL	V11.2D, V22.2D, V10.2D

      (679) 0x43c57c FMUL	V7.2D, V3.2D, V12.2D

      (679) 0x43c580 LDR	Q12, [SP, #240]

      (679) 0x43c584 FADD	V4.2D, V8.2D, V4.2D

      (679) 0x43c588 LDP	Q10, Q8, [SP, #400]

      (679) 0x43c58c FMUL	V23.2D, V23.2D, V12.2D

      (679) 0x43c590 FMLA	V11.2D, V9.2D, V8.2D

      (679) 0x43c594 STR	D23, [X9, X6]

      (679) 0x43c598 LDR	Q12, [SP, #384]

      (679) 0x43c59c FMUL	V8.2D, V13.2D, V4.2D

      (679) 0x43c5a0 LDR	Q2, [SP, #496]

      (679) 0x43c5a4 ST1	{V23.D[1]}, [X17]

      (679) 0x43c5a8 LDP	Q13, Q3, [SP, #192]

      (679) 0x43c5ac ORR	V23.16B, V17.16B, V17.16B

      (679) 0x43c5b0 FMUL	V10.2D, V22.2D, V10.2D

      (679) 0x43c5b4 FMLA	V23.2D, V31.2D, V2.2D

      (679) 0x43c5b8 FMLA	V10.2D, V9.2D, V12.2D

      (679) 0x43c5bc LDP	Q9, Q12, [SP, #304]

      (679) 0x43c5c0 FMLA	V3.2D, V31.2D, V13.2D

      (679) 0x43c5c4 LDP	Q4, Q13, [SP, #160]

      (679) 0x43c5c8 FADD	V5.2D, V5.2D, V23.2D

      (679) 0x43c5cc FMLA	V14.2D, V19.2D, V3.2D

      (679) 0x43c5d0 LDP	Q3, Q2, [SP, #656]

      (679) 0x43c5d4 FMUL	V28.2D, V28.2D, V5.2D

      (679) 0x43c5d8 FMLA	V13.2D, V31.2D, V4.2D

      (679) 0x43c5dc FMLA	V24.2D, V20.2D, V13.2D

      (679) 0x43c5e0 LDR	Q13, [SP, #288]

      (679) 0x43c5e4 FADD	V14.2D, V24.2D, V14.2D

      (679) 0x43c5e8 LDR	Q24, [SP, #336]

      (679) 0x43c5ec FMLA	V24.2D, V31.2D, V12.2D

      (679) 0x43c5f0 FMLA	V24.2D, V22.2D, V9.2D

      (679) 0x43c5f4 LDP	Q12, Q9, [SP, #256]

      (679) 0x43c5f8 FMLA	V21.2D, V19.2D, V24.2D

      (679) 0x43c5fc FMLA	V13.2D, V31.2D, V9.2D

      (679) 0x43c600 FMLA	V13.2D, V22.2D, V12.2D

      (679) 0x43c604 ORR	V22.16B, V2.16B, V2.16B

      (679) 0x43c608 FMLA	V22.2D, V30.2D, V3.2D

      (679) 0x43c60c FMLA	V27.2D, V20.2D, V13.2D

      (679) 0x43c610 FADD	V29.2D, V29.2D, V22.2D

      (679) 0x43c614 FMLA	V7.2D, V18.2D, V29.2D

      (679) 0x43c618 FADD	V18.2D, V27.2D, V21.2D

      (679) 0x43c61c LDR	Q21, [SP, #512]

      (679) 0x43c620 LDP	Q27, Q13, [SP, #688]

      (679) 0x43c624 ORR	V23.16B, V13.16B, V13.16B

      (679) 0x43c628 FMLA	V13.2D, V31.2D, V27.2D

      (679) 0x43c62c FMLA	V23.2D, V30.2D, V27.2D

      (679) 0x43c630 ORR	V30.16B, V2.16B, V2.16B

      (679) 0x43c634 FMLA	V30.2D, V31.2D, V3.2D

      (679) 0x43c638 FADD	V31.2D, V11.2D, V13.2D

      (679) 0x43c63c LDR	Q11, [SP, #240]

      (679) 0x43c640 FADD	V16.2D, V16.2D, V23.2D

      (679) 0x43c644 FMLA	V8.2D, V19.2D, V31.2D

      (679) 0x43c648 FMLA	V25.2D, V15.2D, V16.2D

      (679) 0x43c64c FADD	V15.2D, V10.2D, V30.2D

      (679) 0x43c650 FMUL	V19.2D, V18.2D, V21.2D

      (679) 0x43c654 FMLA	V28.2D, V20.2D, V15.2D

      (679) 0x43c658 FADD	V20.2D, V25.2D, V7.2D

      (679) 0x43c65c FMUL	V7.2D, V14.2D, V11.2D

      (679) 0x43c660 STR	D7, [X9, X5]

      (679) 0x43c664 FADD	V25.2D, V28.2D, V8.2D

      (679) 0x43c668 ST1	{V7.D[1]}, [X27]

      (679) 0x43c66c STR	D26, [X6, X8]

      (679) 0x43c670 ST1	{V26.D[1]}, [X13]

      (679) 0x43c674 STR	D19, [X5, X8]

      (679) 0x43c678 ST1	{V19.D[1]}, [X12]

      (679) 0x43c67c STR	D20, [X6, X7]

      (679) 0x43c680 ST1	{V20.D[1]}, [X3]

      (679) 0x43c684 STR	D25, [X5, X7]

      (679) 0x43c688 ST1	{V25.D[1]}, [X16]

      (679) 0x43c68c CMP	X4, X28

      (679) 0x43c690 B.NE	43c2c4

    (676) 0x43c694 ADD	X10, SP, #936

    (676) 0x43c698 ADD	X28, SP, #968

    (676) 0x43c69c LDR	X16, [SP, #904]

    (676) 0x43c6a0 ADD	X17, SP, #1000

    (676) 0x43c6a4 AND	W27, W11, #1886

    (676) 0x43c6a8 LDR	X12, [SP, #920]

    (676) 0x43c6ac LDR	X13, [SP, #928]

    (676) 0x43c6b0 LDR	D18, [SP, #1032]

    (676) 0x43c6b4 LDR	D16, [SP, #1040]

    (676) 0x43c6b8 LDR	X2, [SP, #1048]

    (676) 0x43c6bc LDP	D31, D30, [X10]

    (676) 0x43c6c0 LDP	D24, D23, [X10, #16]

    (676) 0x43c6c4 LDP	D29, D27, [X28]

    (676) 0x43c6c8 LDP	D22, D21, [X28, #16]

    (676) 0x43c6cc LDP	D26, D25, [X17]

    (676) 0x43c6d0 LDP	D15, D19, [X17, #16]

    (676) 0x43c6d4 LDR	W20, [SP, #916]

    (676) 0x43c6d8 CMP	W27, W11

    (676) 0x43c6dc B.EQ	43cad8

    (680) 0x43c6e0 ORR	W3, WZR, W27

    (680) 0x43c6e4 DUP	Z14.D, Z31.D[0]

    (680) 0x43c6e8 DUP	Z13.D, Z26.D[0]

    (680) 0x43c6ec DUP	Z3.D, Z30.D[0]

    (680) 0x43c6f0 SUB	W11, W11, W27

    (680) 0x43c6f4 ADD	X5, X13, X3,LSL #3

    (680) 0x43c6f8 WHILELO	P4.S, WZR, W11

    (680) 0x43c6fc DUP	Z17.D, Z29.D[0]

    (680) 0x43c700 PUNPKLO	P5.H, P4.B

    (680) 0x43c704 PUNPKHI	P6.H, P4.B

    (680) 0x43c708 DUP	Z29.D, Z24.D[0]

    (680) 0x43c70c LD1D	{Z26.D}, P6/Z, [X5, #1, MUL VL]

    (680) 0x43c710 LD1D	{Z24.D}, P5/Z, [X13, X3,LSL #3]

    (680) 0x43c714 FMUL	Z30.D, Z26.D, Z14.D

    (680) 0x43c718 FMUL	Z2.D, Z24.D, Z14.D

    (680) 0x43c71c MOVPRFX	Z0, Z30

    (680) 0x43c720 FCVTZS	Z0.S, P7/M, Z30.D

    (680) 0x43c724 MOVPRFX	Z6, Z2

    (680) 0x43c728 FCVTZS	Z6.S, P7/M, Z2.D

    (680) 0x43c72c UZP1	Z8.S, Z6.S, Z0.S

    (680) 0x43c730 MOVPRFX	Z28, Z8

    (680) 0x43c734 ADD	Z28.S, Z28.S, #3

    (680) 0x43c738 MOVPRFX	Z31, Z8

    (680) 0x43c73c ADD	Z31.S, Z31.S, #2

    (680) 0x43c740 DUP	Z12.D, Z27.D[0]

    (680) 0x43c744 DUP	Z5.D, Z23.D[0]

    (680) 0x43c748 DUP	Z4.D, Z21.D[0]

    (680) 0x43c74c MOVPRFX	Z1, Z8

    (680) 0x43c750 ADD	Z1.S, Z1.S, #1

    (680) 0x43c754 DUP	Z23.D, Z22.D[0]

    (680) 0x43c758 SUNPKHI	Z21.D, Z28

    (680) 0x43c75c SUNPKLO	Z22.D, Z1

    (680) 0x43c760 SUNPKLO	Z27.D, Z28

    (680) 0x43c764 SUNPKHI	Z20.D, Z31

    (680) 0x43c768 SUNPKLO	Z28.D, Z31

    (680) 0x43c76c SUNPKLO	Z31.D, Z8

    (680) 0x43c770 LD1D	{Z6.D}, P5/Z, [X0, Z22.D,LSL #3]

    (680) 0x43c774 DUP	Z11.D, Z25.D[0]

    (680) 0x43c778 SUNPKHI	Z9.D, Z1

    (680) 0x43c77c SUNPKHI	Z7.D, Z8

    (680) 0x43c780 MOVPRFX	Z22, Z2

    (680) 0x43c784 FRINTZ	Z22.D, P7/M, Z2.D

    (680) 0x43c788 LD1D	{Z8.D}, P5/Z, [X0, Z31.D,LSL #3]

    (680) 0x43c78c FSUB	Z31.D, Z2.D, Z22.D

    (680) 0x43c790 MOVPRFX	Z2, Z11

    (680) 0x43c794 FMLA	Z2.D, P7/M, Z31.D, Z13.D

    (680) 0x43c798 LD1D	{Z0.D}, P6/Z, [X0, Z9.D,LSL #3]

    (680) 0x43c79c LD1D	{Z1.D}, P6/Z, [X0, Z21.D,LSL #3]

    (680) 0x43c7a0 LD1D	{Z9.D}, P5/Z, [X0, Z27.D,LSL #3]

    (680) 0x43c7a4 LD1D	{Z21.D}, P6/Z, [X0, Z20.D,LSL #3]

    (680) 0x43c7a8 MOVPRFX	Z22, Z12

    (680) 0x43c7ac FMLA	Z22.D, P7/M, Z31.D, Z17.D

    (680) 0x43c7b0 LD1D	{Z20.D}, P5/Z, [X0, Z28.D,LSL #3]

    (680) 0x43c7b4 FMUL	Z28.D, Z9.D, Z2.D

    (680) 0x43c7b8 FMUL	Z2.D, Z6.D, Z22.D

    (680) 0x43c7bc LD1D	{Z27.D}, P6/Z, [X0, Z7.D,LSL #3]

    (680) 0x43c7c0 MOVPRFX	Z7, Z4

    (680) 0x43c7c4 FMLA	Z7.D, P7/M, Z31.D, Z23.D

    (680) 0x43c7c8 FMAD	Z7.D, P7/M, Z20.D, Z28.D

    (680) 0x43c7cc MOVPRFX	Z28, Z5

    (680) 0x43c7d0 FMLA	Z28.D, P7/M, Z31.D, Z29.D

    (680) 0x43c7d4 FMAD	Z28.D, P7/M, Z8.D, Z2.D

    (680) 0x43c7d8 MOVPRFX	Z2, Z30

    (680) 0x43c7dc FRINTZ	Z2.D, P7/M, Z30.D

    (680) 0x43c7e0 FSUB	Z30.D, Z30.D, Z2.D

    (680) 0x43c7e4 FMLA	Z11.D, P7/M, Z30.D, Z13.D

    (680) 0x43c7e8 LD1W	{Z25.S}, P4/Z, [X12, X3,LSL #2]

    (680) 0x43c7ec FADD	Z7.D, Z7.D, Z28.D

    (680) 0x43c7f0 SUNPKLO	Z10.D, Z25

    (680) 0x43c7f4 FMUL	Z22.D, Z7.D, Z3.D

    (680) 0x43c7f8 FMAD	Z23.D, P7/M, Z30.D, Z4.D

    (680) 0x43c7fc ST1D	{Z22.D}, P5, [X9, Z10.D,LSL #3]

    (680) 0x43c800 FMAD	Z17.D, P7/M, Z30.D, Z12.D

    (680) 0x43c804 FMAD	Z29.D, P7/M, Z30.D, Z5.D

    (680) 0x43c808 FMUL	Z12.D, Z1.D, Z11.D

    (680) 0x43c80c FMUL	Z17.D, Z0.D, Z17.D

    (680) 0x43c810 FMAD	Z23.D, P7/M, Z21.D, Z12.D

    (680) 0x43c814 FMAD	Z29.D, P7/M, Z27.D, Z17.D

    (680) 0x43c818 PTRUE	P0.B, ALL

    (680) 0x43c81c FADD	Z13.D, Z29.D, Z23.D

    (680) 0x43c820 FMUL	Z11.D, Z13.D, Z3.D

    (680) 0x43c824 FMUL	Z28.D, Z31.D, Z31.D

    (680) 0x43c828 SUNPKHI	Z25.D, Z25

    (680) 0x43c82c DUP	Z16.D, Z16.D[0]

    (680) 0x43c830 ST1D	{Z11.D}, P6, [X9, Z25.D,LSL #3]

    (680) 0x43c834 ADD	X0, SP, #768

    (680) 0x43c838 ADD	X6, SP, #760

    (680) 0x43c83c LD1RD	{Z22.D}, P0/Z, [X0]

    (680) 0x43c840 PTRUE	P1.B, ALL

    (680) 0x43c844 MOVPRFX	Z29, Z16

    (680) 0x43c848 FMLA	Z29.D, P7/M, Z31.D, Z22.D

    (680) 0x43c84c PTRUE	P2.B, ALL

    (680) 0x43c850 PTRUE	P0.B, ALL

    (680) 0x43c854 LD1RD	{Z11.D}, P0/Z, [X6]

    (680) 0x43c858 FMLA	Z29.D, P7/M, Z28.D, Z11.D

    (680) 0x43c85c FMUL	Z29.D, Z9.D, Z29.D

    (680) 0x43c860 DUP	Z18.D, Z18.D[0]

    (680) 0x43c864 ADD	X9, SP, #1064

    (680) 0x43c868 ADD	X21, SP, #1072

    (680) 0x43c86c LD1RD	{Z13.D}, P1/Z, [X9]

    (680) 0x43c870 LD1RD	{Z17.D}, P2/Z, [X21]

    (680) 0x43c874 DUP	Z19.D, Z19.D[0]

    (680) 0x43c878 ADD	X18, SP, #752

    (680) 0x43c87c MOVPRFX	Z3, Z18

    (680) 0x43c880 FMLA	Z3.D, P7/M, Z31.D, Z19.D

    (680) 0x43c884 ADD	X26, SP, #1080

    (680) 0x43c888 FMLA	Z3.D, P7/M, Z28.D, Z17.D

    (680) 0x43c88c DUP	Z15.D, Z15.D[0]

    (680) 0x43c890 FMUL	Z3.D, Z6.D, Z3.D

    (680) 0x43c894 ADD	X4, SP, #1056

    (680) 0x43c898 ADD	X1, SP, #744

    (680) 0x43c89c PTRUE	P3.B, ALL

    (680) 0x43c8a0 PTRUE	P4.B, ALL

    (680) 0x43c8a4 LD1RD	{Z12.D}, P3/Z, [X18]

    (680) 0x43c8a8 LD1RD	{Z7.D}, P4/Z, [X26]

    (680) 0x43c8ac PTRUE	P1.B, ALL

    (680) 0x43c8b0 MOVPRFX	Z4, Z7

    (680) 0x43c8b4 FMLA	Z4.D, P7/M, Z31.D, Z12.D

    (680) 0x43c8b8 LD1RD	{Z23.D}, P1/Z, [X4]

    (680) 0x43c8bc PTRUE	P2.B, ALL

    (680) 0x43c8c0 LD1RD	{Z5.D}, P2/Z, [X1]

    (680) 0x43c8c4 FMLA	Z4.D, P7/M, Z28.D, Z5.D

    (680) 0x43c8c8 FMAD	Z4.D, P7/M, Z20.D, Z29.D

    (680) 0x43c8cc MOVPRFX	Z29, Z13

    (680) 0x43c8d0 FMLA	Z29.D, P7/M, Z31.D, Z15.D

    (680) 0x43c8d4 FMLA	Z29.D, P7/M, Z28.D, Z23.D

    (680) 0x43c8d8 FMAD	Z29.D, P7/M, Z8.D, Z3.D

    (680) 0x43c8dc FMAD	Z19.D, P7/M, Z30.D, Z18.D

    (680) 0x43c8e0 FMAD	Z15.D, P7/M, Z30.D, Z13.D

    (680) 0x43c8e4 FDUP	Z2.D, #112

    (680) 0x43c8e8 FADD	Z4.D, Z29.D, Z4.D

    (680) 0x43c8ec FDIVR	Z26.D, P7/M, Z26.D, Z2.D

    (680) 0x43c8f0 FMUL	Z29.D, Z30.D, Z30.D

    (680) 0x43c8f4 FMAD	Z22.D, P7/M, Z30.D, Z16.D

    (680) 0x43c8f8 FDIVR	Z24.D, P7/M, Z24.D, Z2.D

    (680) 0x43c8fc FMLA	Z22.D, P7/M, Z29.D, Z11.D

    (680) 0x43c900 FMUL	Z24.D, Z24.D, Z14.D

    (680) 0x43c904 PTRUE	P0.B, ALL

    (680) 0x43c908 FMUL	Z24.D, Z4.D, Z24.D

    (680) 0x43c90c ST1D	{Z24.D}, P5, [X8, Z10.D,LSL #3]

    (680) 0x43c910 FMAD	Z12.D, P7/M, Z30.D, Z7.D

    (680) 0x43c914 FMAD	Z17.D, P7/M, Z29.D, Z19.D

    (680) 0x43c918 FMUL	Z14.D, Z26.D, Z14.D

    (680) 0x43c91c FMUL	Z19.D, Z1.D, Z22.D

    (680) 0x43c920 FMUL	Z26.D, Z0.D, Z17.D

    (680) 0x43c924 FMAD	Z5.D, P7/M, Z29.D, Z12.D

    (680) 0x43c928 FMAD	Z23.D, P7/M, Z29.D, Z15.D

    (680) 0x43c92c FMAD	Z5.D, P7/M, Z21.D, Z19.D

    (680) 0x43c930 FMAD	Z23.D, P7/M, Z27.D, Z26.D

    (680) 0x43c934 PTRUE	P3.B, ALL

    (680) 0x43c938 FADD	Z18.D, Z23.D, Z5.D

    (680) 0x43c93c PTRUE	P4.B, ALL

    (680) 0x43c940 FMUL	Z22.D, Z18.D, Z14.D

    (680) 0x43c944 PTRUE	P1.B, ALL

    (680) 0x43c948 ST1D	{Z22.D}, P6, [X8, Z25.D,LSL #3]

    (680) 0x43c94c PTRUE	P2.B, ALL

    (680) 0x43c950 ADD	X30, SP, #784

    (680) 0x43c954 LD1RD	{Z15.D}, P0/Z, [X30]

    (680) 0x43c958 PTRUE	P0.B, ALL

    (680) 0x43c95c ADD	X8, SP, #816

    (680) 0x43c960 ADD	X27, SP, #880

    (680) 0x43c964 LD1RD	{Z12.D}, P3/Z, [X8]

    (680) 0x43c968 LD1RD	{Z13.D}, P4/Z, [X27]

    (680) 0x43c96c PTRUE	P3.B, ALL

    (680) 0x43c970 PTRUE	P4.B, ALL

    (680) 0x43c974 ADD	X10, SP, #808

    (680) 0x43c978 ADD	X28, SP, #824

    (680) 0x43c97c LD1RD	{Z14.D}, P1/Z, [X10]

    (680) 0x43c980 LD1RD	{Z22.D}, P2/Z, [X28]

    (680) 0x43c984 PTRUE	P1.B, ALL

    (680) 0x43c988 PTRUE	P2.B, ALL

    (680) 0x43c98c ADD	X17, SP, #832

    (680) 0x43c990 ADD	X3, SP, #848

    (680) 0x43c994 LD1RD	{Z7.D}, P3/Z, [X17]

    (680) 0x43c998 LD1RD	{Z17.D}, P4/Z, [X3]

    (680) 0x43c99c ADD	X11, SP, #872

    (680) 0x43c9a0 ADD	X5, SP, #888

    (680) 0x43c9a4 LD1RD	{Z24.D}, P0/Z, [X11]

    (680) 0x43c9a8 LD1RD	{Z18.D}, P1/Z, [X5]

    (680) 0x43c9ac PTRUE	P0.B, ALL

    (680) 0x43c9b0 ADD	X0, SP, #896

    (680) 0x43c9b4 ADD	X18, SP, #800

    (680) 0x43c9b8 LD1RD	{Z2.D}, P2/Z, [X0]

    (680) 0x43c9bc LD1RD	{Z11.D}, P0/Z, [X18]

    (680) 0x43c9c0 FMUL	Z26.D, Z28.D, Z12.D

    (680) 0x43c9c4 ADD	X8, SP, #1088

    (680) 0x43c9c8 PTRUE	P3.B, ALL

    (680) 0x43c9cc STR	Z7, [X8, #1, MUL VL]

    (680) 0x43c9d0 ORR	Z19.D, Z7.D, Z7.D

    (680) 0x43c9d4 ADD	X9, SP, #776

    (680) 0x43c9d8 FMUL	Z7.D, Z28.D, Z15.D

    (680) 0x43c9dc LD1RD	{Z16.D}, P3/Z, [X9]

    (680) 0x43c9e0 ADD	X26, SP, #1088

    (680) 0x43c9e4 STR	Z11, [X26, MUL VL]

    (680) 0x43c9e8 FMUL	Z11.D, Z31.D, Z28.D

    (680) 0x43c9ec FMLA	Z26.D, P7/M, Z11.D, Z14.D

    (680) 0x43c9f0 FMLA	Z7.D, P7/M, Z11.D, Z16.D

    (680) 0x43c9f4 FMLA	Z19.D, P7/M, Z31.D, Z22.D

    (680) 0x43c9f8 ADD	X21, SP, #792

    (680) 0x43c9fc FADD	Z19.D, Z19.D, Z26.D

    (680) 0x43ca00 LDR	Z26, [X8, MUL VL]

    (680) 0x43ca04 FMUL	Z6.D, Z19.D, Z6.D

    (680) 0x43ca08 ADD	X6, SP, #840

    (680) 0x43ca0c ADD	X4, SP, #856

    (680) 0x43ca10 PTRUE	P4.B, ALL

    (680) 0x43ca14 ADD	X1, SP, #864

    (680) 0x43ca18 LD1RD	{Z23.D}, P4/Z, [X21]

    (680) 0x43ca1c PTRUE	P1.B, ALL

    (680) 0x43ca20 FMLA	Z26.D, P7/M, Z31.D, Z23.D

    (680) 0x43ca24 LD1RD	{Z3.D}, P1/Z, [X6]

    (680) 0x43ca28 FADD	Z26.D, Z26.D, Z7.D

    (680) 0x43ca2c PTRUE	P2.B, ALL

    (680) 0x43ca30 FMUL	Z7.D, Z28.D, Z13.D

    (680) 0x43ca34 LD1RD	{Z5.D}, P2/Z, [X4]

    (680) 0x43ca38 FMAD	Z26.D, P7/M, Z8.D, Z6.D

    (680) 0x43ca3c FMLA	Z7.D, P7/M, Z11.D, Z24.D

    (680) 0x43ca40 FMUL	Z8.D, Z28.D, Z17.D

    (680) 0x43ca44 PTRUE	P3.B, ALL

    (680) 0x43ca48 MOVPRFX	Z28, Z2

    (680) 0x43ca4c FMLA	Z28.D, P7/M, Z31.D, Z18.D

    (680) 0x43ca50 LD1RD	{Z4.D}, P3/Z, [X1]

    (680) 0x43ca54 FMLA	Z8.D, P7/M, Z11.D, Z3.D

    (680) 0x43ca58 FMAD	Z31.D, P7/M, Z5.D, Z4.D

    (680) 0x43ca5c FADD	Z11.D, Z28.D, Z7.D

    (680) 0x43ca60 FADD	Z31.D, Z31.D, Z8.D

    (680) 0x43ca64 FMUL	Z9.D, Z11.D, Z9.D

    (680) 0x43ca68 FMAD	Z20.D, P7/M, Z31.D, Z9.D

    (680) 0x43ca6c FADD	Z20.D, Z26.D, Z20.D

    (680) 0x43ca70 ST1D	{Z20.D}, P5, [X7, Z10.D,LSL #3]

    (680) 0x43ca74 LDR	Z10, [X8, #1, MUL VL]

    (680) 0x43ca78 FMAD	Z22.D, P7/M, Z30.D, Z10.D

    (680) 0x43ca7c LDR	Z19, [X8, MUL VL]

    (680) 0x43ca80 FMUL	Z12.D, Z29.D, Z12.D

    (680) 0x43ca84 FMUL	Z15.D, Z29.D, Z15.D

    (680) 0x43ca88 FMAD	Z23.D, P7/M, Z30.D, Z19.D

    (680) 0x43ca8c FMUL	Z13.D, Z29.D, Z13.D

    (680) 0x43ca90 FMUL	Z17.D, Z29.D, Z17.D

    (680) 0x43ca94 FMAD	Z18.D, P7/M, Z30.D, Z2.D

    (680) 0x43ca98 FMUL	Z29.D, Z30.D, Z29.D

    (680) 0x43ca9c FMAD	Z30.D, P7/M, Z5.D, Z4.D

    (680) 0x43caa0 FMAD	Z14.D, P7/M, Z29.D, Z12.D

    (680) 0x43caa4 FMAD	Z24.D, P7/M, Z29.D, Z13.D

    (680) 0x43caa8 FADD	Z14.D, Z22.D, Z14.D

    (680) 0x43caac FMAD	Z16.D, P7/M, Z29.D, Z15.D

    (680) 0x43cab0 FMUL	Z0.D, Z0.D, Z14.D

    (680) 0x43cab4 FADD	Z22.D, Z23.D, Z16.D

    (680) 0x43cab8 FMAD	Z29.D, P7/M, Z3.D, Z17.D

    (680) 0x43cabc FMAD	Z27.D, P7/M, Z22.D, Z0.D

    (680) 0x43cac0 FADD	Z24.D, Z24.D, Z18.D

    (680) 0x43cac4 FADD	Z30.D, Z29.D, Z30.D

    (680) 0x43cac8 FMUL	Z1.D, Z1.D, Z24.D

    (680) 0x43cacc FMAD	Z21.D, P7/M, Z30.D, Z1.D

    (680) 0x43cad0 FADD	Z21.D, Z27.D, Z21.D

    (680) 0x43cad4 ST1D	{Z21.D}, P6, [X7, Z25.D,LSL #3]

    (676) 0x43cad8 CMP	X16, X2

    (676) 0x43cadc B.NE	43bd6c

(681) 0x43cae0 LDP	D8, D9, [SP, #96]

(681) 0x43cae4 LDP	D10, D11, [SP, #112]

(681) 0x43cae8 LDP	D12, D13, [SP, #128]

(681) 0x43caec LDP	D14, D15, [SP, #144]

(681) 0x43caf0 LDP	X29, X30, [SP]

(681) 0x43caf4 LDP	X19, X20, [SP, #16]

(681) 0x43caf8 LDP	X21, X22, [SP, #32]

(681) 0x43cafc LDP	X23, X24, [SP, #48]

(681) 0x43cb00 LDP	X25, X26, [SP, #64]

(681) 0x43cb04 LDP	X27, X28, [SP, #80]

(681) 0x43cb08 ADDVL	SP, SP, #2

(681) 0x43cb0c ADD	SP, SP, #1088

(681) 0x43cb10 RET

  (678) 0x43cb14 MOVZ	W27, #0

  (678) 0x43cb18 ADD	X9, X23, X17

  (678) 0x43cb1c ADD	X8, X24, X17

  (678) 0x43cb20 ADD	X7, X25, X17

  (678) 0x43cb24 B	43c6e0

    (676) 0x43cb28 CMP	W19, W10

    (676) 0x43cb2c B.EQ	43bdf4

    (676) 0x43cb30 MOVZ	X21, #0

    (676) 0x43cb34 MOVZ	W11, #1

    (676) 0x43cb38 STR	WZR, [X12, X21]

    (676) 0x43cb3c STR	D28, [X13, X21]

    (676) 0x43cb40 B	43bdf4

0x43cb44 HINT	#0

0x43cb48 HINT	#0

0x43cb4c HINT	#0

0x43cb50 HINT	#0

0x43cb54 HINT	#0

0x43cb58 HINT	#0

0x43cb5c HINT	#0

Coverage (%)	Name	Source Location	Module
►99.15+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:315	exec
○	qmcplusplus::WaveFunction::acc[...]	NewTimer.h:249	exec
○	main._omp_fn.1	refwrap.h:350	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	TwoBodyJastrowRef.h:254-279
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1147-1150
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:254,262,268-271,279
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238,952,1146-1151
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:276-284,291-298,305-336

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.38 to 2.00 cycles (3.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 61% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 6.38 to 5.33 cycles (1.20x speedup).

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.38 to 1.50 cycles (4.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 160 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	6.33	6.33	6.33	3.00	3.00
cycles	3.00	3.00	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	6.33	6.33	6.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	6.38

Vectorization ratios

all	12%
load	0%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

10% of peak load performance is reached (10.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
52% of peak store performance is reached (25.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43bca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADDVL SP, SP, #62	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB SP, SP, #1088	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR W19, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W20, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X26, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
TBNZ W7, #0, 43bcec <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 43bd28 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X27, X20, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X2, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403ea0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403ea0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403ea0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X0, X19,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W3, W1, W16, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CBZ X16, 43caf0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X4, [X26, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X21, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X21, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X21, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X5, W3,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	TwoBodyJastrowRef.h:254-279
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:1147-1150
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:254,262,268-271,279
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_algobase.h:238,952,1146-1151
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:276-284,291-298,305-336

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.38 to 2.00 cycles (3.19x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

12% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
40% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.38 to 1.50 cycles (4.25x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 64 bytes. The binary function is storing 160 bytes.

General properties

nb instructions	58
loop length	232
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

6.38 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	3.00	3.00	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	6.33	6.33	6.33	3.00	3.00
cycles	3.00	3.00	4.83	4.83	4.83	4.83	4.83	4.83	2.00	2.00	0.00	0.00	6.33	6.33	6.33	3.00	3.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	6.38
Overall L1	6.38

Vectorization ratios

all	12%
load	0%
store	40%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.38 cycles. At this rate:

10% of peak load performance is reached (10.04 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
52% of peak store performance is reached (25.10 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 43bca0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
ADDVL SP, SP, #62	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
SUB SP, SP, #1088	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STP X29, X30, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR W19, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W20, WZR, W2	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X22, XZR, X3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X24, XZR, X5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X23, XZR, X6	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X26, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X25, XZR, X4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
TBNZ W7, #0, 43bcec <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x4c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [X0, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
CMP W20, #0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 43bd28 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0x88>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
UBFM X27, X20, #61, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X2, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X25	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403ea0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X0, XZR, X24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 403ea0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X2, XZR, X27	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X23	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W1, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
BL 403ea0 <@plt_start@+0x1b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X0, [X26, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X16, [X21, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR W1, [X0, X19,SXTW #2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
MADD W3, W1, W16, WZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	N/A
CBZ X16, 43caf0 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9computeU3ERKNS1_11ParticleSetEiPKdPdSA_SA_b+0xe50>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
MOVZ X2, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
PTRUE P7.B, ALL	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	scal (100.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR X4, [X26, #616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X13, [X21, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X12, [X21, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X14, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X5, [X21, #512]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X15, X5, W3,SXTW #3	1	0	0	0	0	0	0	0.50	0.50	0	0	0	0	0	0	0	0	0	2	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::computeU3(qmcplusplus::ParticleSet const&, int, double const, double, double, double, bool)–	0.16	0.22
▼Loop 681 - TwoBodyJastrowRef.h:269-279 - exec–	0.00	0.00
▼Loop 678 - TwoBodyJastrowRef.h:269-271 - exec–	0.00	0.00
▼Loop 676 - TwoBodyJastrowRef.h:269-271 - exec–	0.01	0.01
○Loop 677 - BsplineFunctor.h:291-298 - exec	0.13	0.18
○Loop 679 - BsplineFunctor.h:305-336 - exec	0.01	0.02
○Loop 680 - BsplineFunctor.h:305-336 - exec	0.00	0.01

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code