OV - exec - Function qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSet&)

	Function: qmcplusplus::SoaDistanceTableABOMPTarget<double, 3u, 40>::evaluate(qmcplusplus::ParticleSe ...	Module: exec	Source: SoaDistanceTableABOMPTarget.h:61-233 [...]	Coverage (incl. loops): 5.96% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

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242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 993 - 1131

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993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1128:       operator[](size_type __n) _GLIBCXX_NOEXCEPT

1129:       {

1130: 	__glibcxx_requires_subscript(__n);

1131: 	return *(this->_M_impl._M_start + __n);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp: 46 - 46

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46:   return ((n + ND - 1) / ND) * ND;

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

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193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 149 - 248

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149:     if (nAllocated)

[...]

156:     nLocal     = n;

157:     nAllocated = 0;

[...]

223:     return X[i];

[...]

248:   inline pointer data() { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 280 - 298

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280:     T displ_0 = px[iat] - x0;

281:     T displ_1 = py[iat] - y0;

282:     T displ_2 = pz[iat] - z0;

283:

284:     T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

285:     T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

286:     T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

287:

288:     //put them in the box

289:     ar_0 -= round(ar_0);

290:     ar_1 -= round(ar_1);

291:     ar_2 -= round(ar_2);

292:

293:     //unit2cart

294:     dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

295:     dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

296:     dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

297:

298:     temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp: 78 - 79

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78:     free(p);

79:   }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp: 38 - 38

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38:   return a < b ? a : b;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 154 - 267

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154:     nAllocated = 0;

[...]

167:     if (nAllocated)

[...]

174:     nLocal  = n;

175:     nGhosts = n_padded;

176:     myData  = ptr;

[...]

267:   inline const T* data() const { return myData; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h: 61 - 233

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61:     if (num_sources_ * num_targets_ == 0)

62:       return;

63:     if (distances_.size())

64:       return;

65:

66:     // initialize memory containers and views

67:     const size_t num_padded  = getAlignedSize<T>(num_sources_);

68:     const size_t stride_size = getPerTargetPctlStrideSize();

69:     r_dr_memorypool_.resize(stride_size * num_targets_);

70:

71:     distances_.resize(num_targets_);

72:     displacements_.resize(num_targets_);

73:     for (int i = 0; i < num_targets_; ++i)

74:     {

75:       distances_[i].attachReference(r_dr_memorypool_.data() + i * stride_size, num_sources_);

76:       displacements_[i].attachReference(num_sources_, num_padded,

77:                                         r_dr_memorypool_.data() + i * stride_size + num_padded);

[...]

180:   size_t getPerTargetPctlStrideSize() const override { return getAlignedSize<T>(num_sources_) * (D + 1); }

181:

182:   /** evaluate the full table */

183:   inline void evaluate(ParticleSet& P) override

184:   {

185:     resize();

186:

187:     ScopedTimer local_timer(evaluate_timer_);

188:     // be aware of the sign of Displacement

189:     const int num_targets_local = num_targets_;

190:     const int num_sources_local = num_sources_;

191:     const int num_padded        = getAlignedSize<T>(num_sources_);

192:

193:     target_pos.resize(num_targets_ * D);

194:     for (size_t iat = 0; iat < num_targets_; iat++)

195:       for (size_t idim = 0; idim < D; idim++)

196:         target_pos[iat * D + idim] = P.R[iat][idim];

197:

198:     auto* target_pos_ptr = target_pos.data();

199:     auto* source_pos_ptr = origin_.getCoordinates().getAllParticlePos().data();

[...]

205:     const size_t num_teams     = (num_sources_ + ChunkSizePerTeam - 1) / ChunkSizePerTeam;

206:     const size_t stride_size   = getPerTargetPctlStrideSize();

207:

208:     {

209:       ScopedTimer offload(offload_timer_);

210:       PRAGMA_OFFLOAD("omp target teams distribute collapse(2) num_teams(num_targets_*num_teams) \

211:                         map(to: source_pos_ptr[:num_padded*D]) \

212:                         map(always, to: target_pos_ptr[:num_targets_*D]) \

213:                         map(always, from: r_dr_ptr[:num_targets_*stride_size])")

214:       for (int iat = 0; iat < num_targets_local; ++iat)

215:         for (int team_id = 0; team_id < num_teams; team_id++)

216:         {

217:           const int first = ChunkSizePerTeam * team_id;

218:           const int last  = omptarget::min(first + ChunkSizePerTeam, num_sources_local);

219:

220:           T pos[D];

221:           for (int idim = 0; idim < D; idim++)

222:             pos[idim] = target_pos_ptr[iat * D + idim];

223:

224:           auto* r_iat_ptr  = r_dr_ptr + iat * stride_size;

225:           auto* dr_iat_ptr = r_iat_ptr + num_padded;

226:

227:           PRAGMA_OFFLOAD("omp parallel for")

228:           for (int iel = first; iel < last; iel++)

229:             DTD_BConds<T, D, SC>::computeDistancesOffload(pos, source_pos_ptr, num_padded, r_iat_ptr, dr_iat_ptr,

230:                                                           num_padded, iel);

231:         }

232:     }

233:   }

0x53cec0 STP	X29, X30, [SP, #864]!

0x53cec4 ADD	X29, SP, #0

0x53cec8 STP	X19, X20, [SP, #16]

0x53cecc STP	X21, X22, [SP, #32]

0x53ced0 ORR	X22, XZR, X0

0x53ced4 STP	X23, X24, [SP, #48]

0x53ced8 STP	X25, X26, [SP, #64]

0x53cedc STP	X27, X28, [SP, #80]

0x53cee0 STP	D14, D15, [SP, #96]

0x53cee4 STR	X1, [SP, #120]

0x53cee8 LDP	X2, X1, [X0, #16]

0x53ceec MADD	X3, X2, X1, XZR

0x53cef0 CBZ	X3, 53cf08

0x53cef4 LDR	X4, [X0, #72]

0x53cef8 ADD	X21, X0, #72

0x53cefc LDR	X5, [X21, #8]

0x53cf00 CMP	X5, X4

0x53cf04 B.EQ	53d3a0

(4219) 0x53cf08 LDR	X20, [X22, #440]

(4219) 0x53cf0c ADD	X21, X22, #384

(4219) 0x53cf10 ORR	X0, XZR, X20

(4219) 0x53cf14 BL	4d5540

(4219) 0x53cf18 LDP	X23, X26, [X22, #16]

(4219) 0x53cf1c MOVI	D0, #0

(4219) 0x53cf20 ORR	X0, XZR, X21

(4219) 0x53cf24 ADD	X8, X23, #3

(4219) 0x53cf28 ADD	X1, X26, X26,LSL #1

(4219) 0x53cf2c AND	X27, X8, #8062

(4219) 0x53cf30 BL	517b20

(4219) 0x53cf34 LDR	X30, [X22, #24]

(4219) 0x53cf38 LDR	X25, [X21, #24]

(4219) 0x53cf3c CBZ	X30, 53d174

(4219) 0x53cf40 LDR	X9, [SP, #120]

(4219) 0x53cf44 LDR	X0, [X9, #64]

(4219) 0x53cf48 CMP	X30, #1

(4219) 0x53cf4c B.EQ	53d524

(4219) 0x53cf50 ADD	X10, X0, #47

(4219) 0x53cf54 SUB	X1, X10, X25

(4219) 0x53cf58 CMP	X1, #94

(4219) 0x53cf5c B.LS	53d524

(4219) 0x53cf60 AND	X11, X30, #8127

(4219) 0x53cf64 ORR	X12, XZR, #3841

(4219) 0x53cf68 ADD	X24, X11, X30,LSR #1

(4219) 0x53cf6c MOVK	X12, #43691

(4219) 0x53cf70 ORR	X2, XZR, X25

(4219) 0x53cf74 MOVK	X12, #2730

(4219) 0x53cf78 ORR	X18, XZR, X0

(4219) 0x53cf7c UBFM	X13, X24, #60, #59

(4219) 0x53cf80 ADD	X19, X25, X24,LSL #4

(4219) 0x53cf84 SUB	X14, X13, #48

(4219) 0x53cf88 UBFM	X15, X14, #4, #63

(4219) 0x53cf8c MADD	X16, X15, X12, XZR

(4219) 0x53cf90 ADD	X17, X16, #1

(4219) 0x53cf94 ANDS	X28, X17, #4224

(4219) 0x53cf98 B.EQ	53d07c

(4219) 0x53cf9c CMP	X28, #1

(4219) 0x53cfa0 B.EQ	53d05c

(4219) 0x53cfa4 CMP	X28, #2

(4219) 0x53cfa8 B.EQ	53d044

(4219) 0x53cfac CMP	X28, #3

(4219) 0x53cfb0 B.EQ	53d02c

(4219) 0x53cfb4 CMP	X28, #4

(4219) 0x53cfb8 B.EQ	53d014

(4219) 0x53cfbc CMP	X28, #5

(4219) 0x53cfc0 B.EQ	53cffc

(4219) 0x53cfc4 CMP	X28, #6

(4219) 0x53cfc8 B.EQ	53cfe4

(4219) 0x53cfcc LDP	Q31, Q30, [X0]

(4219) 0x53cfd0 ADD	X2, X25, #48

(4219) 0x53cfd4 ADD	X18, X0, #48

(4219) 0x53cfd8 LDR	Q29, [X0, #32]

(4219) 0x53cfdc STR	Q29, [X25, #32]

(4219) 0x53cfe0 STP	Q31, Q30, [X25]

(4219) 0x53cfe4 LDP	Q0, Q1, [X18]

(4219) 0x53cfe8 ADD	X2, X2, #48

(4219) 0x53cfec ADD	X18, X18, #48

(4219) 0x53cff0 LDUR	Q2, [X18, #496]

(4219) 0x53cff4 STUR	Q2, [X2, #496]

(4219) 0x53cff8 STP	Q0, Q1, [X2, #2000]

(4219) 0x53cffc LDP	Q3, Q4, [X18]

(4219) 0x53d000 ADD	X2, X2, #48

(4219) 0x53d004 ADD	X18, X18, #48

(4219) 0x53d008 LDUR	Q5, [X18, #496]

(4219) 0x53d00c STUR	Q5, [X2, #496]

(4219) 0x53d010 STP	Q3, Q4, [X2, #2000]

(4219) 0x53d014 LDP	Q6, Q7, [X18]

(4219) 0x53d018 ADD	X2, X2, #48

(4219) 0x53d01c ADD	X18, X18, #48

(4219) 0x53d020 LDUR	Q14, [X18, #496]

(4219) 0x53d024 STUR	Q14, [X2, #496]

(4219) 0x53d028 STP	Q6, Q7, [X2, #2000]

(4219) 0x53d02c LDP	Q15, Q16, [X18]

(4219) 0x53d030 ADD	X2, X2, #48

(4219) 0x53d034 ADD	X18, X18, #48

(4219) 0x53d038 LDUR	Q17, [X18, #496]

(4219) 0x53d03c STUR	Q17, [X2, #496]

(4219) 0x53d040 STP	Q15, Q16, [X2, #2000]

(4219) 0x53d044 LDP	Q18, Q19, [X18]

(4219) 0x53d048 ADD	X2, X2, #48

(4219) 0x53d04c ADD	X18, X18, #48

(4219) 0x53d050 LDUR	Q20, [X18, #496]

(4219) 0x53d054 STUR	Q20, [X2, #496]

(4219) 0x53d058 STP	Q18, Q19, [X2, #2000]

(4219) 0x53d05c LDP	Q21, Q22, [X18]

(4219) 0x53d060 ADD	X2, X2, #48

(4219) 0x53d064 ADD	X18, X18, #48

(4219) 0x53d068 LDUR	Q23, [X18, #496]

(4219) 0x53d06c STUR	Q23, [X2, #496]

(4219) 0x53d070 STP	Q21, Q22, [X2, #2000]

(4219) 0x53d074 CMP	X2, X19

(4219) 0x53d078 B.EQ	53d144

  (4227) 0x53d07c LDP	Q24, Q25, [X18]

  (4227) 0x53d080 ADD	X3, X18, #48

  (4227) 0x53d084 ADD	X5, X2, #48

  (4227) 0x53d088 ADD	X4, X18, #96

  (4227) 0x53d08c ADD	X21, X2, #96

  (4227) 0x53d090 LDR	Q26, [X18, #32]

  (4227) 0x53d094 ADD	X9, X18, #144

  (4227) 0x53d098 ADD	X1, X2, #144

  (4227) 0x53d09c ADD	X8, X18, #192

  (4227) 0x53d0a0 ADD	X24, X2, #192

  (4227) 0x53d0a4 ADD	X7, X18, #240

  (4227) 0x53d0a8 ADD	X12, X2, #240

  (4227) 0x53d0ac ADD	X6, X18, #288

  (4227) 0x53d0b0 ADD	X11, X2, #288

  (4227) 0x53d0b4 ADD	X13, X18, #336

  (4227) 0x53d0b8 ADD	X10, X2, #336

  (4227) 0x53d0bc STR	Q26, [X2, #32]

  (4227) 0x53d0c0 STP	Q24, Q25, [X2]

  (4227) 0x53d0c4 LDP	Q27, Q28, [X3, #16]

  (4227) 0x53d0c8 LDR	Q31, [X18, #48]

  (4227) 0x53d0cc STR	Q31, [X2, #48]

  (4227) 0x53d0d0 STP	Q27, Q28, [X5, #16]

  (4227) 0x53d0d4 LDP	Q0, Q30, [X4, #16]

  (4227) 0x53d0d8 LDR	Q29, [X18, #96]

  (4227) 0x53d0dc ADD	X18, X18, #384

  (4227) 0x53d0e0 STR	Q29, [X2, #96]

  (4227) 0x53d0e4 ADD	X2, X2, #384

  (4227) 0x53d0e8 STP	Q0, Q30, [X21, #16]

  (4227) 0x53d0ec LDP	Q1, Q2, [X9, #16]

  (4227) 0x53d0f0 LDUR	Q3, [X18, #272]

  (4227) 0x53d0f4 STUR	Q3, [X2, #272]

  (4227) 0x53d0f8 STP	Q1, Q2, [X1, #16]

  (4227) 0x53d0fc LDP	Q4, Q5, [X8, #16]

  (4227) 0x53d100 LDUR	Q6, [X18, #320]

  (4227) 0x53d104 STUR	Q6, [X2, #320]

  (4227) 0x53d108 STP	Q4, Q5, [X24, #16]

  (4227) 0x53d10c LDP	Q7, Q14, [X7, #16]

  (4227) 0x53d110 LDUR	Q15, [X18, #368]

  (4227) 0x53d114 STUR	Q15, [X2, #368]

  (4227) 0x53d118 STP	Q7, Q14, [X12, #16]

  (4227) 0x53d11c LDP	Q16, Q17, [X6, #16]

  (4227) 0x53d120 LDUR	Q18, [X18, #416]

  (4227) 0x53d124 STUR	Q18, [X2, #416]

  (4227) 0x53d128 STP	Q16, Q17, [X11, #16]

  (4227) 0x53d12c LDP	Q19, Q20, [X13, #16]

  (4227) 0x53d130 LDUR	Q21, [X18, #464]

  (4227) 0x53d134 STUR	Q21, [X2, #464]

  (4227) 0x53d138 STP	Q19, Q20, [X10, #16]

  (4227) 0x53d13c CMP	X2, X19

  (4227) 0x53d140 B.NE	53d07c

(4219) 0x53d144 TBZ	W30, #0, 53d174

(4219) 0x53d148 AND	X30, X30, #8127

(4219) 0x53d14c ADD	X19, X30, X30,LSL #1

(4219) 0x53d150 UBFM	X14, X19, #61, #60

(4219) 0x53d154 ADD	X15, X0, X19,LSL #3

(4219) 0x53d158 ADD	X16, X25, X14

(4219) 0x53d15c LDR	D22, [X0, X14]

(4219) 0x53d160 STR	D22, [X25, X14]

(4219) 0x53d164 LDR	D23, [X15, #8]

(4219) 0x53d168 STR	D23, [X16, #8]

(4219) 0x53d16c LDR	D24, [X15, #16]

(4219) 0x53d170 STR	D24, [X16, #16]

(4219) 0x53d174 LDR	X6, [X22, #8]

(4219) 0x53d178 ADRP	X7,

(4219) 0x53d17c ADD	X12, X7, #736

(4219) 0x53d180 LDR	X0, [X6, #632]

(4219) 0x53d184 ORR	X13, XZR, X0

(4219) 0x53d188 LDR	X11, [X13], #64

(4219) 0x53d18c LDR	X10, [X11, #72]

(4219) 0x53d190 CMP	X10, X12

(4219) 0x53d194 B.NE	53d518

(4219) 0x53d198 LDR	X15, [X22]

(4219) 0x53d19c ADRP	X30,

(4219) 0x53d1a0 ADD	X14, X30, #32

(4219) 0x53d1a4 LDR	X16, [X22, #16]

(4219) 0x53d1a8 LDR	X17, [X22, #72]

(4219) 0x53d1ac LDR	X18, [X15, #136]

(4219) 0x53d1b0 ADD	X28, X16, #511

(4219) 0x53d1b4 LDR	X19, [X13, #24]

(4219) 0x53d1b8 UBFM	X24, X28, #9, #63

(4219) 0x53d1bc LDR	X21, [X17, #24]

(4219) 0x53d1c0 CMP	X18, X14

(4219) 0x53d1c4 B.NE	53d508

(4219) 0x53d1c8 ADD	X2, X16, #3

(4219) 0x53d1cc AND	X5, X2, #8062

(4219) 0x53d1d0 UBFM	X3, X5, #62, #61

(4219) 0x53d1d4 LDR	X28, [X22, #432]

(4219) 0x53d1d8 STR	X3, [SP, #120]

(4219) 0x53d1dc ORR	X0, XZR, X28

(4219) 0x53d1e0 BL	4d5540

(4219) 0x53d1e4 CMP	W26, #0

(4219) 0x53d1e8 B.LE	53d370

(4219) 0x53d1ec SBFM	X14, X27, #61, #31

(4219) 0x53d1f0 CBZ	X24, 53d370

(4219) 0x53d1f4 LDR	X4, [SP, #120]

(4219) 0x53d1f8 ADD	W26, W26, W26,LSL #1

(4219) 0x53d1fc ORR	X7, XZR, X21

(4219) 0x53d200 MOVZ	W16, #0

(4219) 0x53d204 SBFM	X27, X27, #60, #30

(4219) 0x53d208 UBFM	X24, X24, #55, #54

(4219) 0x53d20c ADD	X8, X19, X14

(4219) 0x53d210 UBFM	X15, X4, #61, #60

(4219) 0x53d214 HINT	#0

(4219) 0x53d218 HINT	#0

(4219) 0x53d21c HINT	#0

  (4224) 0x53d220 ADD	W0, W16, #1

  (4224) 0x53d224 ADD	W1, W16, #2

  (4224) 0x53d228 ADD	X30, X7, X14,LSL #1

  (4224) 0x53d22c ADD	X13, X25, W16,UXTW #3

  (4224) 0x53d230 ADD	X12, X25, X0,LSL #3

  (4224) 0x53d234 MOVZ	X9, #0

  (4224) 0x53d238 ADD	X17, X14, X7

  (4224) 0x53d23c ADD	X11, X25, X1,LSL #3

  (4224) 0x53d240 ORR	X10, XZR, X27

    (4223) 0x53d244 ADD	W6, W9, #512

    (4223) 0x53d248 LDR	D29, [X11]

    (4223) 0x53d24c CMP	W6, W23

    (4223) 0x53d250 CSEL	W18, W6, W23, #13

    (4223) 0x53d254 LDR	D30, [X12]

    (4223) 0x53d258 LDR	D31, [X13]

    (4223) 0x53d25c CMP	W18, W9

    (4223) 0x53d260 B.LE	53d350

    (4223) 0x53d264 ADD	X21, X22, #200

    (4223) 0x53d268 ORR	X3, XZR, X10

    (4223) 0x53d26c LDR	D20, [X21, #136]

    (4223) 0x53d270 ORR	X2, XZR, X9

    (4223) 0x53d274 LDR	D19, [X22, #200]

    (4223) 0x53d278 LDP	D18, D17, [X21, #8]

    (4223) 0x53d27c LDP	D16, D7, [X21, #24]

    (4223) 0x53d280 LDP	D6, D5, [X21, #40]

    (4223) 0x53d284 LDP	D4, D3, [X21, #56]

    (4223) 0x53d288 LDP	D28, D27, [X21, #72]

    (4223) 0x53d28c LDP	D26, D25, [X21, #88]

    (4223) 0x53d290 LDP	D24, D23, [X21, #104]

    (4223) 0x53d294 LDP	D22, D21, [X21, #120]

    (4223) 0x53d298 HINT	#0

    (4223) 0x53d29c HINT	#0

      (4225) 0x53d2a0 LDR	D1, [X8, X2,LSL #3]

      (4225) 0x53d2a4 LDR	D2, [X19, X2,LSL #3]

      (4225) 0x53d2a8 LDR	D0, [X19, X3]

      (4225) 0x53d2ac FSUB	D1, D1, S30

      (4225) 0x53d2b0 FSUB	D2, D2, S31

      (4225) 0x53d2b4 FSUB	D0, D0, S29

      (4225) 0x53d2b8 FMUL	D14, D1, D24

      (4225) 0x53d2bc FMUL	D15, D1, D27

      (4225) 0x53d2c0 FMUL	D1, D1, D21

      (4225) 0x53d2c4 FMADD	D14, D2, D25, D14

      (4225) 0x53d2c8 FMADD	D15, D2, D28, D15

      (4225) 0x53d2cc FMADD	D1, D2, D22, D1

      (4225) 0x53d2d0 FMADD	D14, D0, D23, D14

      (4225) 0x53d2d4 FMADD	D15, D0, D26, D15

      (4225) 0x53d2d8 FRINTA	D2, D15

      (4225) 0x53d2dc FMADD	D1, D0, D20, D1

      (4225) 0x53d2e0 FRINTA	D0, D14

      (4225) 0x53d2e4 FSUB	D0, D14, S0

      (4225) 0x53d2e8 FSUB	D2, D15, S2

      (4225) 0x53d2ec FRINTA	D14, D1

      (4225) 0x53d2f0 FSUB	D15, D1, S14

      (4225) 0x53d2f4 FMUL	D14, D0, D18

      (4225) 0x53d2f8 FMUL	D1, D0, D7

      (4225) 0x53d2fc FMUL	D0, D0, D4

      (4225) 0x53d300 FMADD	D14, D2, D19, D14

      (4225) 0x53d304 FMADD	D1, D2, D16, D1

      (4225) 0x53d308 FMADD	D2, D2, D5, D0

      (4225) 0x53d30c FMADD	D14, D15, D17, D14

      (4225) 0x53d310 FMADD	D1, D15, D6, D1

      (4225) 0x53d314 FMADD	D15, D15, D3, D2

      (4225) 0x53d318 STR	D14, [X17, X2,LSL #3]

      (4225) 0x53d31c STR	D1, [X30, X2,LSL #3]

      (4225) 0x53d320 STR	D15, [X17, X3]

      (4225) 0x53d324 ADD	X3, X3, #8

      (4225) 0x53d328 LDR	D0, [X30, X2,LSL #3]

      (4225) 0x53d32c LDR	D2, [X17, X2,LSL #3]

      (4225) 0x53d330 FMUL	D14, D0, D0

      (4225) 0x53d334 FMADD	D1, D2, D2, D14

      (4225) 0x53d338 FMADD	D15, D15, D15, D1

      (4225) 0x53d33c FSQRT	D0, D15

      (4225) 0x53d340 STR	D0, [X7, X2,LSL #3]

      (4225) 0x53d344 ADD	X2, X2, #1

      (4225) 0x53d348 CMP	W18, W2

      (4225) 0x53d34c B.GT	53d2a0

    (4223) 0x53d350 ADD	X9, X9, #512

    (4223) 0x53d354 ADD	X10, X10, #1

    (4223) 0x53d358 CMP	X9, X24

    (4223) 0x53d35c B.NE	53d244

  (4224) 0x53d360 ADD	W16, W16, #3

  (4224) 0x53d364 ADD	X7, X7, X15

  (4224) 0x53d368 CMP	W26, W16

  (4224) 0x53d36c B.NE	53d220

(4219) 0x53d370 ORR	X0, XZR, X28

(4219) 0x53d374 BL	4d57e0

(4219) 0x53d378 ORR	X0, XZR, X20

(4219) 0x53d37c BL	4d57e0

(4219) 0x53d380 LDP	D14, D15, [SP, #96]

(4219) 0x53d384 LDP	X19, X20, [SP, #16]

(4219) 0x53d388 LDP	X21, X22, [SP, #32]

(4219) 0x53d38c LDP	X23, X24, [SP, #48]

(4219) 0x53d390 LDP	X25, X26, [SP, #64]

(4219) 0x53d394 LDP	X27, X28, [SP, #80]

(4219) 0x53d398 LDP	X29, X30, [SP], #160

(4219) 0x53d39c RET

(4219) 0x53d3a0 LDR	X9, [X0]

(4219) 0x53d3a4 ADRP	X6,

(4219) 0x53d3a8 ADD	X7, X2, #3

(4219) 0x53d3ac ADD	X8, X6, #32

(4219) 0x53d3b0 AND	X23, X7, #8062

(4219) 0x53d3b4 LDR	X10, [X9, #136]

(4219) 0x53d3b8 CMP	X10, X8

(4219) 0x53d3bc B.NE	53d74c

(4219) 0x53d3c0 UBFM	X19, X23, #62, #61

(4219) 0x53d3c4 ADD	X11, X22, #344

(4219) 0x53d3c8 MOVI	D0, #0

(4219) 0x53d3cc MADD	X1, X19, X1, XZR

(4219) 0x53d3d0 ORR	X0, XZR, X11

(4219) 0x53d3d4 STR	X11, [SP, #136]

(4219) 0x53d3d8 BL	517b20

(4219) 0x53d3dc LDR	X1, [X22, #24]

(4219) 0x53d3e0 ORR	X0, XZR, X21

(4219) 0x53d3e4 BL	4b0dc0

(4219) 0x53d3e8 ADD	X12, X22, #96

(4219) 0x53d3ec LDR	X1, [X22, #24]

(4219) 0x53d3f0 ORR	X0, XZR, X12

(4219) 0x53d3f4 STR	X12, [SP, #128]

(4219) 0x53d3f8 BL	4c8e60

(4219) 0x53d3fc LDR	X0, [X22, #24]

(4219) 0x53d400 CBZ	X0, 53cf08

(4219) 0x53d404 LDP	X5, X3, [SP, #128]

(4219) 0x53d408 MOVZ	X27, #0

(4219) 0x53d40c MOVZ	X28, #0

(4219) 0x53d410 UBFM	X2, X19, #61, #60

(4219) 0x53d414 UBFM	X6, X23, #61, #60

(4219) 0x53d418 MOVZ	W4, #40

  (4220) 0x53d41c UMADDL	X24, W28, W4, XZR

  (4220) 0x53d420 LDR	X13, [X21]

  (4220) 0x53d424 LDR	X15, [X3, #24]

  (4220) 0x53d428 LDR	X20, [X22, #16]

  (4220) 0x53d42c ADD	X19, X13, X24

  (4220) 0x53d430 LDR	X14, [X19, #16]

  (4220) 0x53d434 ADD	X26, X15, X27

  (4220) 0x53d438 CBNZ	X14, 53d4a0

  (4221) 0x53d43c LDR	X25, [X5]

  (4221) 0x53d440 ADD	X16, X6, X27

  (4221) 0x53d444 STR	X20, [X19, #8]

  (4221) 0x53d448 ADD	X20, X15, X16

  (4221) 0x53d44c STP	XZR, X26, [X19, #16]

  (4221) 0x53d450 ADD	X19, X25, X24

  (4221) 0x53d454 LDR	X26, [X22, #16]

  (4221) 0x53d458 LDR	X17, [X19, #16]

  (4221) 0x53d45c CBNZ	X17, 53d4c4

  (4221) 0x53d460 STR	X26, [X25, X24]

  (4221) 0x53d464 ADD	X28, X28, #1

  (4221) 0x53d468 ADD	X27, X27, X2

  (4221) 0x53d46c STR	X23, [X19, #8]

  (4221) 0x53d470 LDR	X18, [X22, #24]

  (4221) 0x53d474 STR	X20, [X19, #24]

  (4221) 0x53d478 CMP	X18, X28

  (4221) 0x53d47c B.LS	53cf08

  (4221) 0x53d480 LDR	X13, [X21]

  (4221) 0x53d484 UMADDL	X24, W28, W4, XZR

  (4221) 0x53d488 LDR	X15, [X3, #24]

  (4221) 0x53d48c LDR	X20, [X22, #16]

  (4221) 0x53d490 ADD	X19, X13, X24

  (4221) 0x53d494 LDR	X14, [X19, #16]

  (4221) 0x53d498 ADD	X26, X15, X27

  (4221) 0x53d49c CBZ	X14, 53d43c

    (4222) 0x53d4a0 LDR	X0, [X19, #24]

    (4222) 0x53d4a4 STP	X6, X2, [SP, #128]

    (4222) 0x53d4a8 STP	X3, X5, [SP, #144]

    (4222) 0x53d4ac BL	4044b0

(4219) 0x53d4b0 LDP	X3, X5, [SP, #144]

(4219) 0x53d4b4 MOVZ	W4, #40

(4219) 0x53d4b8 LDP	X6, X2, [SP, #128]

(4219) 0x53d4bc LDR	X15, [X3, #24]

(4219) 0x53d4c0 B	53d43c

  (4220) 0x53d4c4 LDR	X0, [X19, #24]

  (4220) 0x53d4c8 ADD	X28, X28, #1

  (4220) 0x53d4cc STP	X6, X2, [SP, #128]

  (4220) 0x53d4d0 STP	X3, X5, [SP, #144]

  (4220) 0x53d4d4 BL	4044b0

  (4220) 0x53d4d8 LDP	X6, X2, [SP, #128]

  (4220) 0x53d4dc MOVZ	W4, #40

  (4220) 0x53d4e0 LDP	X3, X5, [SP, #144]

  (4220) 0x53d4e4 ADD	X27, X27, X2

  (4220) 0x53d4e8 STR	XZR, [X19, #16]

  (4220) 0x53d4ec STR	X26, [X25, X24]

  (4220) 0x53d4f0 STR	X23, [X19, #8]

  (4220) 0x53d4f4 LDR	X7, [X22, #24]

  (4220) 0x53d4f8 STR	X20, [X19, #24]

  (4220) 0x53d4fc CMP	X28, X7

  (4220) 0x53d500 B.CC	53d41c

(4219) 0x53d504 B	53cf08

(4219) 0x53d508 ORR	X0, XZR, X22

(4219) 0x53d50c BLR	X18

(4219) 0x53d510 ORR	X3, XZR, X0

(4219) 0x53d514 B	53d1d4

(4219) 0x53d518 BLR	X10

(4219) 0x53d51c ORR	X13, XZR, X0

(4219) 0x53d520 B	53d198

(4219) 0x53d524 ADD	X17, X30, X30,LSL #1

(4219) 0x53d528 ORR	X28, XZR, #3841

(4219) 0x53d52c ORR	X1, XZR, X25

(4219) 0x53d530 MOVK	X28, #43691

(4219) 0x53d534 UBFM	X18, X17, #61, #60

(4219) 0x53d538 MOVK	X28, #2730

(4219) 0x53d53c ADD	X3, X0, X17,LSL #3

(4219) 0x53d540 SUB	X2, X18, #24

(4219) 0x53d544 UBFM	X5, X2, #3, #63

(4219) 0x53d548 MADD	X4, X5, X28, XZR

(4219) 0x53d54c ADD	X21, X4, #1

(4219) 0x53d550 ANDS	X9, X21, #4224

(4219) 0x53d554 B.EQ	53d670

(4219) 0x53d558 CMP	X9, #1

(4219) 0x53d55c B.EQ	53d648

(4219) 0x53d560 CMP	X9, #2

(4219) 0x53d564 B.EQ	53d628

(4219) 0x53d568 CMP	X9, #3

(4219) 0x53d56c B.EQ	53d608

(4219) 0x53d570 CMP	X9, #4

(4219) 0x53d574 B.EQ	53d5e8

(4219) 0x53d578 CMP	X9, #5

(4219) 0x53d57c B.EQ	53d5c8

(4219) 0x53d580 CMP	X9, #6

(4219) 0x53d584 B.EQ	53d5a8

(4219) 0x53d588 LDR	D25, [X0]

(4219) 0x53d58c ADD	X1, X25, #24

(4219) 0x53d590 ADD	X0, X0, #24

(4219) 0x53d594 STR	D25, [X25]

(4219) 0x53d598 LDUR	D26, [X0, #496]

(4219) 0x53d59c STR	D26, [X25, #8]

(4219) 0x53d5a0 LDUR	D27, [X0, #504]

(4219) 0x53d5a4 STR	D27, [X25, #16]

(4219) 0x53d5a8 LDR	D28, [X0]

(4219) 0x53d5ac ADD	X1, X1, #24

(4219) 0x53d5b0 ADD	X0, X0, #24

(4219) 0x53d5b4 STUR	D28, [X1, #488]

(4219) 0x53d5b8 LDUR	D31, [X0, #496]

(4219) 0x53d5bc STUR	D31, [X1, #496]

(4219) 0x53d5c0 LDUR	D0, [X0, #504]

(4219) 0x53d5c4 STUR	D0, [X1, #504]

(4219) 0x53d5c8 LDR	D30, [X0]

(4219) 0x53d5cc ADD	X1, X1, #24

(4219) 0x53d5d0 ADD	X0, X0, #24

(4219) 0x53d5d4 STUR	D30, [X1, #488]

(4219) 0x53d5d8 LDUR	D29, [X0, #496]

(4219) 0x53d5dc STUR	D29, [X1, #496]

(4219) 0x53d5e0 LDUR	D1, [X0, #504]

(4219) 0x53d5e4 STUR	D1, [X1, #504]

(4219) 0x53d5e8 LDR	D2, [X0]

(4219) 0x53d5ec ADD	X1, X1, #24

(4219) 0x53d5f0 ADD	X0, X0, #24

(4219) 0x53d5f4 STUR	D2, [X1, #488]

(4219) 0x53d5f8 LDUR	D3, [X0, #496]

(4219) 0x53d5fc STUR	D3, [X1, #496]

(4219) 0x53d600 LDUR	D4, [X0, #504]

(4219) 0x53d604 STUR	D4, [X1, #504]

(4219) 0x53d608 LDR	D5, [X0]

(4219) 0x53d60c ADD	X1, X1, #24

(4219) 0x53d610 ADD	X0, X0, #24

(4219) 0x53d614 STUR	D5, [X1, #488]

(4219) 0x53d618 LDUR	D6, [X0, #496]

(4219) 0x53d61c STUR	D6, [X1, #496]

(4219) 0x53d620 LDUR	D7, [X0, #504]

(4219) 0x53d624 STUR	D7, [X1, #504]

(4219) 0x53d628 LDR	D14, [X0]

(4219) 0x53d62c ADD	X1, X1, #24

(4219) 0x53d630 ADD	X0, X0, #24

(4219) 0x53d634 STUR	D14, [X1, #488]

(4219) 0x53d638 LDUR	D15, [X0, #496]

(4219) 0x53d63c STUR	D15, [X1, #496]

(4219) 0x53d640 LDUR	D16, [X0, #504]

(4219) 0x53d644 STUR	D16, [X1, #504]

(4219) 0x53d648 LDR	D17, [X0]

(4219) 0x53d64c ADD	X0, X0, #24

(4219) 0x53d650 ADD	X1, X1, #24

(4219) 0x53d654 STUR	D17, [X1, #488]

(4219) 0x53d658 LDUR	D18, [X0, #496]

(4219) 0x53d65c STUR	D18, [X1, #496]

(4219) 0x53d660 LDUR	D19, [X0, #504]

(4219) 0x53d664 STUR	D19, [X1, #504]

(4219) 0x53d668 CMP	X3, X0

(4219) 0x53d66c B.EQ	53d174

  (4226) 0x53d670 LDR	D20, [X0]

  (4226) 0x53d674 ORR	X8, XZR, X0

  (4226) 0x53d678 ORR	X24, XZR, X1

  (4226) 0x53d67c ADD	X0, X0, #192

  (4226) 0x53d680 ADD	X1, X1, #192

  (4226) 0x53d684 STUR	D20, [X1, #320]

  (4226) 0x53d688 LDUR	D21, [X0, #328]

  (4226) 0x53d68c STUR	D21, [X1, #328]

  (4226) 0x53d690 LDUR	D22, [X0, #336]

  (4226) 0x53d694 STUR	D22, [X1, #336]

  (4226) 0x53d698 LDUR	D23, [X0, #344]

  (4226) 0x53d69c STUR	D23, [X1, #344]

  (4226) 0x53d6a0 LDUR	D24, [X0, #352]

  (4226) 0x53d6a4 STUR	D24, [X1, #352]

  (4226) 0x53d6a8 LDUR	D25, [X0, #360]

  (4226) 0x53d6ac STUR	D25, [X1, #360]

  (4226) 0x53d6b0 LDUR	D26, [X0, #368]

  (4226) 0x53d6b4 STUR	D26, [X1, #368]

  (4226) 0x53d6b8 LDUR	D27, [X0, #376]

  (4226) 0x53d6bc STUR	D27, [X1, #376]

  (4226) 0x53d6c0 LDUR	D28, [X0, #384]

  (4226) 0x53d6c4 STUR	D28, [X1, #384]

  (4226) 0x53d6c8 LDUR	D31, [X0, #392]

  (4226) 0x53d6cc STUR	D31, [X1, #392]

  (4226) 0x53d6d0 LDUR	D0, [X0, #400]

  (4226) 0x53d6d4 STUR	D0, [X1, #400]

  (4226) 0x53d6d8 LDUR	D30, [X0, #408]

  (4226) 0x53d6dc STUR	D30, [X1, #408]

  (4226) 0x53d6e0 LDUR	D29, [X0, #416]

  (4226) 0x53d6e4 STUR	D29, [X1, #416]

  (4226) 0x53d6e8 LDUR	D1, [X0, #424]

  (4226) 0x53d6ec STUR	D1, [X1, #424]

  (4226) 0x53d6f0 LDUR	D2, [X0, #432]

  (4226) 0x53d6f4 STUR	D2, [X1, #432]

  (4226) 0x53d6f8 LDUR	D3, [X0, #440]

  (4226) 0x53d6fc STUR	D3, [X1, #440]

  (4226) 0x53d700 LDUR	D4, [X0, #448]

  (4226) 0x53d704 STUR	D4, [X1, #448]

  (4226) 0x53d708 LDUR	D5, [X0, #456]

  (4226) 0x53d70c STUR	D5, [X1, #456]

  (4226) 0x53d710 LDUR	D6, [X0, #464]

  (4226) 0x53d714 STUR	D6, [X1, #464]

  (4226) 0x53d718 LDUR	D7, [X0, #472]

  (4226) 0x53d71c STUR	D7, [X1, #472]

  (4226) 0x53d720 LDUR	D14, [X0, #480]

  (4226) 0x53d724 STUR	D14, [X1, #480]

  (4226) 0x53d728 LDUR	D15, [X0, #488]

  (4226) 0x53d72c STUR	D15, [X1, #488]

  (4226) 0x53d730 LDR	D16, [X8, #176]

  (4226) 0x53d734 STR	D16, [X24, #176]

  (4226) 0x53d738 LDR	D17, [X8, #184]

  (4226) 0x53d73c STR	D17, [X24, #184]

  (4226) 0x53d740 CMP	X3, X0

  (4226) 0x53d744 B.NE	53d670

(4219) 0x53d748 B	53d174

(4219) 0x53d74c BLR	X10

(4219) 0x53d750 LDR	X1, [X22, #24]

(4219) 0x53d754 ORR	X19, XZR, X0

(4219) 0x53d758 B	53d3c4

0x53d75c ORR	X19, XZR, X0

0x53d760 ORR	X0, XZR, X20

0x53d764 BL	4d57e0

0x53d768 ORR	X0, XZR, X19

0x53d76c BL	404170

0x53d770 HINT	#0

0x53d774 HINT	#0

0x53d778 HINT	#0

0x53d77c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.73+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:135	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	SoaDistanceTableABOMPTarget.h:61-233
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp:46
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:149,156-157,223,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:78-79
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:154,167,174-176,267
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:61-77,180-199,205-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.17 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. 80% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 4.00 to 3.75 cycles (1.07x speedup).

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
12% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Overall L1	4.00

Vectorization ratios

all	7%
load	0%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53cec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X3, X2, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CBZ X3, 53cf08 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X0, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 53d3a0 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d57e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404170 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	SoaDistanceTableABOMPTarget.h:61-233
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1128-1131
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/aligned_allocator.hpp:46
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/unique_ptr.h:193
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:149,156-157,223,248
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:280-298
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:78-79
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/OMPTarget/OMPTargetMath.hpp:38
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:154,167,174-176,267
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/SoaDistanceTableABOMPTarget.h:61-77,180-199,205-233

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 4.00 to 1.17 cycles (3.43x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

7% of VPU instructions are used in vector version (process two or more data elements in vector registers):

0% of VPU loads are used in vector version.
12% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU fused multiply-add instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 4.00 to 1.00 cycles (4.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 32 bytes. The binary function is storing 120 bytes.

General properties

nb instructions	27
loop length	108
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.88 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.00	0.00	4.00	4.00	3.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.88
Overall L1	4.00

Vectorization ratios

all	7%
load	0%
store	12%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	0%
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 4.00 cycles. At this rate:

8% of peak load performance is reached (8.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
62% of peak store performance is reached (30.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 53cec0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #864]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D14, D15, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X1, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X2, X1, [X0, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
MADD X3, X2, X1, XZR	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	2	1	scal (50.0%)
CBZ X3, 53cf08 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x48>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X4, [X0, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADD X21, X0, #72	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X5, [X21, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
CMP X5, X4	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 53d3a0 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi40EE8evaluateERNS_11ParticleSetE+0x4e0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4d57e0 <_ZN11qmcplusplus9TimerTypeINSt6chrono3_V212system_clockEE4stopEv>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404170 <@plt_start@+0x480>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼qmcplusplus::SoaDistanceTableABOMPTarget::evaluate(qmcplusplus::ParticleSet&)–	5.96	8.25
▼Loop 4219 - SoaDistanceTableABOMPTarget.h:68-233 - exec–	0.00	0.01
▼Loop 4224 - SoaDistanceTableABOMPTarget.h:214-228 - exec–	0.00	0.00
▼Loop 4223 - SoaDistanceTableABOMPTarget.h:215-228 - exec–	0.01	0.01
○Loop 4225 - SoaDistanceTableABOMPTarget.h:228-228 - exec	5.95	8.14
○Loop 4221 - OhmmsVector.h:149-248 - exec	0.00	0.00
○Loop 4227 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0.00	0.00
▼Loop 4220 - SoaDistanceTableABOMPTarget.h:73-75 - exec–	0.00	0.00
○Loop 4222 - Mallocator.hpp:78-78 - exec	0.00	0.00
○Loop 4226 - SoaDistanceTableABOMPTarget.h:194-196 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code