OV - exec - Function miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector<double, std::allocator<double> >&)

	Function: miniqmcreference::OneBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::evaluateRatios( ...	Module: exec	Source: OneBodyJastrowRef.h:132-155 [...]	Coverage (incl. loops): 0.05% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h: 993 - 1131

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993:       { return size_type(this->_M_impl._M_finish - this->_M_impl._M_start); }

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h: 132 - 155

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132:   inline void evaluateRatios(VirtualParticleSet& VP, std::vector<ValueType>& ratios)

133:   {

134:     for (int k = 0; k < ratios.size(); ++k)

135:       ratios[k] = std::exp(Vat[VP.refPtcl] - computeU(VP.getDistTableAB(myTableID).getDistRow(k).data()));

136:   }

137:

138:   inline valT computeU(const valT* dist)

139:   {

140:     valT curVat(0);

141:     if (NumGroups > 0)

142:     {

143:       for (int jg = 0; jg < NumGroups; ++jg)

144:       {

145:         if (F[jg] != nullptr)

146:           curVat += F[jg]->evaluateV(-1, Ions.first(jg), Ions.last(jg), dist, DistCompressed.data());

147:       }

148:     }

149:     else

150:     {

151:       for (int c = 0; c < Nions; ++c)

152:       {

153:         int gid = Ions.GroupID[c];

154:         if (F[gid] != nullptr)

155:           curVat += F[gid]->evaluate(dist[c]);

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 316

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

314:

315:   ///return the last index of a group i

316:   inline int last(int igroup) const { return (*group_offsets_)[igroup + 1]; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h: 166 - 260

--------------------------------------------------------------------------------

166:     if (r >= cutoff_radius)

167:       return 0.0;

168:     r *= DeltaRInv;

169:     real_type ipart, t;

170:     t     = std::modf(r, &ipart);

171:     int i = (int)ipart;

172:     real_type tp[4];

173:     tp[0] = t * t * t;

[...]

179:       (SplineCoefs[i+0]*(A[ 0]*tp[0] + A[ 1]*tp[1] + A[ 2]*tp[2] + A[ 3]*tp[3])+

180:        SplineCoefs[i+1]*(A[ 4]*tp[0] + A[ 5]*tp[1] + A[ 6]*tp[2] + A[ 7]*tp[3])+

181:        SplineCoefs[i+2]*(A[ 8]*tp[0] + A[ 9]*tp[1] + A[10]*tp[2] + A[11]*tp[3])+

182:        SplineCoefs[i+3]*(A[12]*tp[0] + A[13]*tp[1] + A[14]*tp[2] + A[15]*tp[3]));

[...]

231:   ASSUME_ALIGNED(distArrayCompressed);

232:   int iCount       = 0;

233:   const int iLimit = iEnd - iStart;

234:

235: #pragma vector always

236:   for (int jat = 0; jat < iLimit; jat++)

237:   {

238:     real_type r = distArray[jat];

239:     // pick the distances smaller than the cutoff and avoid the reference atom

240:     if (r < cutoff_radius && iStart + jat != iat)

241:       distArrayCompressed[iCount++] = distArray[jat];

242:   }

243:

244:   real_type d = 0.0;

245:   //#pragma omp simd reduction(+:d)

246:   for (int jat = 0; jat < iCount; jat++)

247:   {

248:     real_type r = distArrayCompressed[jat];

249:     r *= DeltaRInv;

250:     int i         = (int)r;

251:     real_type t   = r - real_type(i);

252:     real_type tp0 = t * t * t;

253:     real_type tp1 = t * t;

254:     real_type tp2 = t;

255:

256:     real_type d1 = SplineCoefs[i + 0] * (A[0] * tp0 + A[1] * tp1 + A[2] * tp2 + A[3]);

257:     real_type d2 = SplineCoefs[i + 1] * (A[4] * tp0 + A[5] * tp1 + A[6] * tp2 + A[7]);

258:     real_type d3 = SplineCoefs[i + 2] * (A[8] * tp0 + A[9] * tp1 + A[10] * tp2 + A[11]);

259:     real_type d4 = SplineCoefs[i + 3] * (A[12] * tp0 + A[13] * tp1 + A[14] * tp2 + A[15]);

260:     d += (d1 + d2 + d3 + d4);

0x417a00 STP	X29, X30, [SP, #832]!

0x417a04 ADD	X29, SP, #0

0x417a08 STP	X21, X22, [SP, #32]

0x417a0c ORR	X22, XZR, X1

0x417a10 STP	X23, X24, [SP, #48]

0x417a14 ADD	X23, X0, #216

0x417a18 STP	X25, X26, [SP, #64]

0x417a1c ORR	X26, XZR, X0

0x417a20 STR	X2, [SP, #160]

0x417a24 LDP	X1, X0, [X2]

0x417a28 CMP	X1, X0

0x417a2c B.EQ	417f78

0x417a30 STP	X19, X20, [SP, #16]

0x417a34 MOVZ	X20, #0

0x417a38 MOVZ	X19, #0

0x417a3c STP	X27, X28, [SP, #80]

0x417a40 STP	D8, D9, [SP, #96]

0x417a44 STP	D10, D11, [SP, #112]

0x417a48 STP	D12, D13, [SP, #128]

0x417a4c STP	D14, D15, [SP, #144]

    (278) 0x417a50 LDR	X2, [X23, #24]

    (278) 0x417a54 ORR	X0, XZR, X22

    (278) 0x417a58 LDRSW	X3, [X22, #672]

    (278) 0x417a5c LDR	W1, [X26, #168]

    (278) 0x417a60 LDR	D15, [X2, X3,LSL #3]

    (278) 0x417a64 BL	49180c

    (278) 0x417a68 LDR	X4, [X0, #72]

    (278) 0x417a6c LDR	W10, [X26, #152]

    (278) 0x417a70 ADD	X5, X4, X20

    (278) 0x417a74 LDR	X27, [X5, #24]

    (278) 0x417a78 CMP	W10, #0

    (278) 0x417a7c B.LE	417f8c

    (278) 0x417a80 LDR	X11, [X26, #456]

    (278) 0x417a84 MOVI	D1, #0

    (278) 0x417a88 MOVZ	X7, #0

    (278) 0x417a8c UBFM	X10, X10, #62, #31

    (278) 0x417a90 PTRUE	P7.B, ALL

    (278) 0x417a94 CNTW	X9, ALL

    (278) 0x417a98 HINT	#0

    (278) 0x417a9c HINT	#0

      (277) 0x417aa0 UBFM	X17, X7, #63, #62

      (277) 0x417aa4 LDR	X30, [X11, X17]

      (277) 0x417aa8 CBZ	X30, 417f28

      (277) 0x417aac LDR	X21, [X26, #160]

      (277) 0x417ab0 LDR	X6, [X26, #328]

      (277) 0x417ab4 LDR	X28, [X21, #616]

      (277) 0x417ab8 LDR	X8, [X28, #24]

      (277) 0x417abc ADD	X12, X8, X7

      (277) 0x417ac0 LDR	W13, [X8, X7]

      (277) 0x417ac4 LDR	W14, [X12, #4]

      (277) 0x417ac8 CMP	W14, W13

      (277) 0x417acc B.LE	417f28

      (277) 0x417ad0 SUB	W15, W14, W13

      (277) 0x417ad4 SBFM	X18, X13, #61, #31

      (277) 0x417ad8 LDR	D6, [X30, #8]

      (277) 0x417adc ANDS	W0, W15, #128

      (277) 0x417ae0 MOVZ	W5, #0

      (277) 0x417ae4 ADD	X28, X27, X18

      (277) 0x417ae8 ORR	W21, WZR, W13

      (277) 0x417aec B.EQ	417c24

      (277) 0x417af0 CMP	W0, #1

      (277) 0x417af4 B.EQ	417bf8

      (277) 0x417af8 CMP	W0, #2

      (277) 0x417afc B.EQ	417bd4

      (277) 0x417b00 CMP	W0, #3

      (277) 0x417b04 B.EQ	417bb0

      (277) 0x417b08 CMP	W0, #4

      (277) 0x417b0c B.EQ	417b8c

      (277) 0x417b10 CMP	W0, #5

      (277) 0x417b14 B.EQ	417b68

      (277) 0x417b18 CMP	W0, #6

      (277) 0x417b1c B.EQ	417b44

      (277) 0x417b20 LDR	D7, [X27, X18]

      (277) 0x417b24 FCMPE	D6, D7

      (277) 0x417b28 B.LS	417b3c

      (277) 0x417b2c CMN	W13, #1

      (277) 0x417b30 B.EQ	417b3c

      (277) 0x417b34 MOVZ	W5, #1

      (277) 0x417b38 STR	D7, [X6]

      (277) 0x417b3c ADD	X28, X28, #8

      (277) 0x417b40 ADD	W21, W13, #1

      (277) 0x417b44 LDR	D8, [X28]

      (277) 0x417b48 FCMPE	D6, D8

      (277) 0x417b4c B.LS	417b60

      (277) 0x417b50 CMN	W21, #1

      (277) 0x417b54 B.EQ	417b60

      (277) 0x417b58 STR	D8, [X6, X5,UXTW #3]

      (277) 0x417b5c ADD	W5, W5, #1

      (277) 0x417b60 ADD	X28, X28, #8

      (277) 0x417b64 ADD	W21, W21, #1

      (277) 0x417b68 LDR	D26, [X28]

      (277) 0x417b6c FCMPE	D6, D26

      (277) 0x417b70 B.LS	417b84

      (277) 0x417b74 CMN	W21, #1

      (277) 0x417b78 B.EQ	417b84

      (277) 0x417b7c STR	D26, [X6, X5,UXTW #3]

      (277) 0x417b80 ADD	W5, W5, #1

      (277) 0x417b84 ADD	X28, X28, #8

      (277) 0x417b88 ADD	W21, W21, #1

      (277) 0x417b8c LDR	D9, [X28]

      (277) 0x417b90 FCMPE	D6, D9

      (277) 0x417b94 B.LS	417ba8

      (277) 0x417b98 CMN	W21, #1

      (277) 0x417b9c B.EQ	417ba8

      (277) 0x417ba0 STR	D9, [X6, X5,UXTW #3]

      (277) 0x417ba4 ADD	W5, W5, #1

      (277) 0x417ba8 ADD	X28, X28, #8

      (277) 0x417bac ADD	W21, W21, #1

      (277) 0x417bb0 LDR	D10, [X28]

      (277) 0x417bb4 FCMPE	D6, D10

      (277) 0x417bb8 B.LS	417bcc

      (277) 0x417bbc CMN	W21, #1

      (277) 0x417bc0 B.EQ	417bcc

      (277) 0x417bc4 STR	D10, [X6, X5,UXTW #3]

      (277) 0x417bc8 ADD	W5, W5, #1

      (277) 0x417bcc ADD	X28, X28, #8

      (277) 0x417bd0 ADD	W21, W21, #1

      (277) 0x417bd4 LDR	D20, [X28]

      (277) 0x417bd8 FCMPE	D6, D20

      (277) 0x417bdc B.LS	417bf0

      (277) 0x417be0 CMN	W21, #1

      (277) 0x417be4 B.EQ	417bf0

      (277) 0x417be8 STR	D20, [X6, X5,UXTW #3]

      (277) 0x417bec ADD	W5, W5, #1

      (277) 0x417bf0 ADD	X28, X28, #8

      (277) 0x417bf4 ADD	W21, W21, #1

      (277) 0x417bf8 LDR	D11, [X28]

      (277) 0x417bfc FCMPE	D6, D11

      (277) 0x417c00 B.LS	417c14

      (277) 0x417c04 CMN	W21, #1

      (277) 0x417c08 B.EQ	417c14

      (277) 0x417c0c STR	D11, [X6, X5,UXTW #3]

      (277) 0x417c10 ADD	W5, W5, #1

      (277) 0x417c14 ADD	W21, W21, #1

      (277) 0x417c18 ADD	X28, X28, #8

      (277) 0x417c1c CMP	W14, W21

      (277) 0x417c20 B.EQ	417d34

        (279) 0x417c24 LDR	D12, [X28]

        (279) 0x417c28 FCMPE	D6, D12

        (279) 0x417c2c B.LS	417c40

        (279) 0x417c30 CMN	W21, #1

        (279) 0x417c34 B.EQ	417c40

        (279) 0x417c38 STR	D12, [X6, X5,UXTW #3]

        (279) 0x417c3c ADD	W5, W5, #1

        (279) 0x417c40 LDR	D13, [X28, #8]

        (279) 0x417c44 ADD	W16, W21, #1

        (279) 0x417c48 ADD	X3, X28, #8

        (279) 0x417c4c FCMPE	D6, D13

        (279) 0x417c50 B.LS	417c64

        (279) 0x417c54 CMN	W16, #1

        (279) 0x417c58 B.EQ	417c64

        (279) 0x417c5c STR	D13, [X6, X5,UXTW #3]

        (279) 0x417c60 ADD	W5, W5, #1

        (279) 0x417c64 LDR	D16, [X3, #8]

        (279) 0x417c68 ADD	W25, W16, #1

        (279) 0x417c6c FCMPE	D6, D16

        (279) 0x417c70 B.LS	417c84

        (279) 0x417c74 CMN	W25, #1

        (279) 0x417c78 B.EQ	417c84

        (279) 0x417c7c STR	D16, [X6, X5,UXTW #3]

        (279) 0x417c80 ADD	W5, W5, #1

        (279) 0x417c84 LDR	D17, [X3, #16]

        (279) 0x417c88 ADD	W2, W16, #2

        (279) 0x417c8c FCMPE	D6, D17

        (279) 0x417c90 B.LS	417ca4

        (279) 0x417c94 CMN	W2, #1

        (279) 0x417c98 B.EQ	417ca4

        (279) 0x417c9c STR	D17, [X6, X5,UXTW #3]

        (279) 0x417ca0 ADD	W5, W5, #1

        (279) 0x417ca4 LDR	D18, [X3, #24]

        (279) 0x417ca8 ADD	W1, W16, #3

        (279) 0x417cac FCMPE	D6, D18

        (279) 0x417cb0 B.LS	417cc4

        (279) 0x417cb4 CMN	W1, #1

        (279) 0x417cb8 B.EQ	417cc4

        (279) 0x417cbc STR	D18, [X6, X5,UXTW #3]

        (279) 0x417cc0 ADD	W5, W5, #1

        (279) 0x417cc4 LDR	D22, [X3, #32]

        (279) 0x417cc8 ADD	W4, W16, #4

        (279) 0x417ccc FCMPE	D6, D22

        (279) 0x417cd0 B.LS	417ce4

        (279) 0x417cd4 CMN	W4, #1

        (279) 0x417cd8 B.EQ	417ce4

        (279) 0x417cdc STR	D22, [X6, X5,UXTW #3]

        (279) 0x417ce0 ADD	W5, W5, #1

        (279) 0x417ce4 LDR	D30, [X3, #40]

        (279) 0x417ce8 ADD	W24, W16, #5

        (279) 0x417cec FCMPE	D6, D30

        (279) 0x417cf0 B.LS	417d04

        (279) 0x417cf4 CMN	W24, #1

        (279) 0x417cf8 B.EQ	417d04

        (279) 0x417cfc STR	D30, [X6, X5,UXTW #3]

        (279) 0x417d00 ADD	W5, W5, #1

        (279) 0x417d04 LDR	D31, [X3, #48]

        (279) 0x417d08 ADD	W17, W16, #6

        (279) 0x417d0c FCMPE	D6, D31

        (279) 0x417d10 B.LS	417d24

        (279) 0x417d14 CMN	W17, #1

        (279) 0x417d18 B.EQ	417d24

        (279) 0x417d1c STR	D31, [X6, X5,UXTW #3]

        (279) 0x417d20 ADD	W5, W5, #1

        (279) 0x417d24 ADD	W21, W16, #7

        (279) 0x417d28 ADD	X28, X3, #56

        (279) 0x417d2c CMP	W14, W21

        (279) 0x417d30 B.NE	417c24

      (277) 0x417d34 CBZ	W5, 417f28

      (277) 0x417d38 ADD	X12, X30, #568

      (277) 0x417d3c LD1RD	{Z3.D}, P7/Z, [X30, #3]

      (277) 0x417d40 LD1RD	{Z4.D}, P7/Z, [X30, #4]

      (277) 0x417d44 LD1RD	{Z5.D}, P7/Z, [X30, #5]

      (277) 0x417d48 LD1RD	{Z6.D}, P7/Z, [X30, #6]

      (277) 0x417d4c LD1RD	{Z7.D}, P7/Z, [X30, #7]

      (277) 0x417d50 LD1RD	{Z16.D}, P7/Z, [X30, #8]

      (277) 0x417d54 LD1RD	{Z17.D}, P7/Z, [X30, #9]

      (277) 0x417d58 LD1RD	{Z18.D}, P7/Z, [X30, #10]

      (277) 0x417d5c LD1RD	{Z19.D}, P7/Z, [X30, #11]

      (277) 0x417d60 LD1RD	{Z20.D}, P7/Z, [X30, #12]

      (277) 0x417d64 LD1RD	{Z21.D}, P7/Z, [X30, #13]

      (277) 0x417d68 LD1RD	{Z22.D}, P7/Z, [X30, #14]

      (277) 0x417d6c LD1RD	{Z23.D}, P7/Z, [X30, #15]

      (277) 0x417d70 LD1RD	{Z24.D}, P7/Z, [X30, #16]

      (277) 0x417d74 LD1RD	{Z25.D}, P7/Z, [X30, #17]

      (277) 0x417d78 LD1RD	{Z26.D}, P7/Z, [X30, #18]

      (277) 0x417d7c LDR	X30, [X30, #536]

      (277) 0x417d80 MOVZ	X14, #0

      (277) 0x417d84 ADDVL	X8, X6, #1

      (277) 0x417d88 ORR	W13, WZR, W5

      (277) 0x417d8c DUP	Z28.D, #0

      (277) 0x417d90 UQDECD	W13, ALL

      (277) 0x417d94 LD1RD	{Z2.D}, P7/Z, [X12]

      (277) 0x417d98 WHILELO	P5.D, WZR, W13

      (277) 0x417d9c ORR	Z29.D, Z28.D, Z28.D

      (277) 0x417da0 WHILELO	P6.D, WZR, W5

        (280) 0x417da4 LD1D	{Z0.D}, P5/Z, [X8, X14,LSL #3]

        (280) 0x417da8 LD1D	{Z27.D}, P6/Z, [X6, X14,LSL #3]

        (280) 0x417dac FMUL	Z8.D, Z2.D, Z0.D

        (280) 0x417db0 FMUL	Z14.D, Z2.D, Z27.D

        (280) 0x417db4 MOVPRFX	Z9, Z8

        (280) 0x417db8 FRINTZ	Z9.D, P7/M, Z8.D

        (280) 0x417dbc MOVPRFX	Z10, Z8

        (280) 0x417dc0 FCVTZS	Z10.S, P7/M, Z8.D

        (280) 0x417dc4 FSUB	Z31.D, Z8.D, Z9.D

        (280) 0x417dc8 MOVPRFX	Z11, Z14

        (280) 0x417dcc FCVTZS	Z11.S, P7/M, Z14.D

        (280) 0x417dd0 FMUL	Z27.D, Z31.D, Z31.D

        (280) 0x417dd4 MOVPRFX	Z8, Z18

        (280) 0x417dd8 FMLA	Z8.D, P7/M, Z17.D, Z31.D

        (280) 0x417ddc FMUL	Z0.D, Z27.D, Z31.D

        (280) 0x417de0 FMUL	Z12.D, Z16.D, Z27.D

        (280) 0x417de4 FMLA	Z12.D, P7/M, Z7.D, Z0.D

        (280) 0x417de8 UZP1	Z30.S, Z11.S, Z10.S

        (280) 0x417dec FADD	Z11.D, Z8.D, Z12.D

        (280) 0x417df0 MOVPRFX	Z13, Z30

        (280) 0x417df4 ADD	Z13.S, Z13.S, #1

        (280) 0x417df8 MOVPRFX	Z8, Z6

        (280) 0x417dfc FMLA	Z8.D, P7/M, Z5.D, Z31.D

        (280) 0x417e00 SUNPKHI	Z9.D, Z13

        (280) 0x417e04 LD1D	{Z12.D}, P5/Z, [X30, Z9.D,LSL #3]

        (280) 0x417e08 FMUL	Z10.D, Z4.D, Z27.D

        (280) 0x417e0c FMUL	Z11.D, Z11.D, Z12.D

        (280) 0x417e10 FMLA	Z10.D, P7/M, Z3.D, Z0.D

        (280) 0x417e14 SUNPKHI	Z9.D, Z30

        (280) 0x417e18 FADD	Z12.D, Z8.D, Z10.D

        (280) 0x417e1c LD1D	{Z8.D}, P5/Z, [X30, Z9.D,LSL #3]

        (280) 0x417e20 FMUL	Z10.D, Z20.D, Z27.D

        (280) 0x417e24 FMAD	Z12.D, P7/M, Z8.D, Z11.D

        (280) 0x417e28 FMLA	Z10.D, P7/M, Z19.D, Z0.D

        (280) 0x417e2c MOVPRFX	Z11, Z22

        (280) 0x417e30 FMLA	Z11.D, P7/M, Z21.D, Z31.D

        (280) 0x417e34 FMUL	Z27.D, Z27.D, Z24.D

        (280) 0x417e38 FADD	Z8.D, Z11.D, Z10.D

        (280) 0x417e3c FMAD	Z0.D, P7/M, Z23.D, Z27.D

        (280) 0x417e40 FADD	Z28.D, P5/M, Z28.D, Z12.D

        (280) 0x417e44 MOVPRFX	Z27, Z30

        (280) 0x417e48 ADD	Z27.S, Z27.S, #3

        (280) 0x417e4c MOVPRFX	Z12, Z30

        (280) 0x417e50 ADD	Z12.S, Z12.S, #2

        (280) 0x417e54 SUNPKHI	Z10.D, Z27

        (280) 0x417e58 SUNPKLO	Z30.D, Z30

        (280) 0x417e5c LD1D	{Z11.D}, P5/Z, [X30, Z10.D,LSL #3]

        (280) 0x417e60 FMAD	Z31.D, P7/M, Z25.D, Z26.D

        (280) 0x417e64 FADD	Z31.D, Z31.D, Z0.D

        (280) 0x417e68 SUNPKHI	Z0.D, Z12

        (280) 0x417e6c LD1D	{Z9.D}, P5/Z, [X30, Z0.D,LSL #3]

        (280) 0x417e70 FMLA	Z28.D, P5/M, Z8.D, Z9.D

        (280) 0x417e74 SUNPKLO	Z8.D, Z12

        (280) 0x417e78 FMLA	Z28.D, P5/M, Z11.D, Z31.D

        (280) 0x417e7c LD1D	{Z0.D}, P6/Z, [X30, Z8.D,LSL #3]

        (280) 0x417e80 LD1D	{Z11.D}, P6/Z, [X30, Z30.D,LSL #3]

        (280) 0x417e84 SUNPKLO	Z12.D, Z27

        (280) 0x417e88 MOVPRFX	Z31, Z14

        (280) 0x417e8c FRINTZ	Z31.D, P7/M, Z14.D

        (280) 0x417e90 SUNPKLO	Z13.D, Z13

        (280) 0x417e94 FSUB	Z8.D, Z14.D, Z31.D

        (280) 0x417e98 FMUL	Z30.D, Z8.D, Z8.D

        (280) 0x417e9c FMUL	Z27.D, Z30.D, Z8.D

        (280) 0x417ea0 FMUL	Z14.D, Z16.D, Z30.D

        (280) 0x417ea4 FMLA	Z14.D, P7/M, Z7.D, Z27.D

        (280) 0x417ea8 LD1D	{Z10.D}, P6/Z, [X30, Z13.D,LSL #3]

        (280) 0x417eac ADD	X14, X14, X9

        (280) 0x417eb0 LD1D	{Z13.D}, P6/Z, [X30, Z12.D,LSL #3]

        (280) 0x417eb4 WHILELO	P5.D, W14, W13

        (280) 0x417eb8 MOVPRFX	Z12, Z18

        (280) 0x417ebc FMLA	Z12.D, P7/M, Z17.D, Z8.D

        (280) 0x417ec0 FADD	Z31.D, Z12.D, Z14.D

        (280) 0x417ec4 MOVPRFX	Z14, Z6

        (280) 0x417ec8 FMLA	Z14.D, P7/M, Z5.D, Z8.D

        (280) 0x417ecc FMUL	Z12.D, Z31.D, Z10.D

        (280) 0x417ed0 FMUL	Z9.D, Z4.D, Z30.D

        (280) 0x417ed4 FMUL	Z10.D, Z20.D, Z30.D

        (280) 0x417ed8 FMLA	Z9.D, P7/M, Z3.D, Z27.D

        (280) 0x417edc MOVPRFX	Z31, Z22

        (280) 0x417ee0 FMLA	Z31.D, P7/M, Z21.D, Z8.D

        (280) 0x417ee4 FADD	Z9.D, Z14.D, Z9.D

        (280) 0x417ee8 FMUL	Z30.D, Z30.D, Z24.D

        (280) 0x417eec FMAD	Z9.D, P7/M, Z11.D, Z12.D

        (280) 0x417ef0 FMAD	Z8.D, P7/M, Z25.D, Z26.D

        (280) 0x417ef4 MOVPRFX	Z11, Z10

        (280) 0x417ef8 FMLA	Z11.D, P7/M, Z19.D, Z27.D

        (280) 0x417efc FADD	Z29.D, P6/M, Z29.D, Z9.D

        (280) 0x417f00 FMAD	Z27.D, P7/M, Z23.D, Z30.D

        (280) 0x417f04 FADD	Z14.D, Z31.D, Z11.D

        (280) 0x417f08 FMLA	Z29.D, P6/M, Z14.D, Z0.D

        (280) 0x417f0c FADD	Z0.D, Z8.D, Z27.D

        (280) 0x417f10 FMLA	Z29.D, P6/M, Z13.D, Z0.D

        (280) 0x417f14 WHILELO	P6.D, W14, W5

        (280) 0x417f18 B.NE	417da4

      (277) 0x417f1c FADD	Z2.D, Z29.D, Z28.D

      (277) 0x417f20 FADDV	D28, P7, Z2.D

      (277) 0x417f24 FADD	D1, D1, D28

      (277) 0x417f28 ADD	X7, X7, #4

      (277) 0x417f2c CMP	X10, X7

      (277) 0x417f30 B.NE	417aa0

    (278) 0x417f34 FSUB	D15, D15, S1

    (278) 0x417f38 FMOV	D0, D15

    (278) 0x417f3c ADD	X20, X20, #40

    (278) 0x417f40 BL	403db0

    (278) 0x417f44 LDR	X6, [SP, #160]

    (278) 0x417f48 LDP	X15, X18, [X6]

    (278) 0x417f4c SUB	X0, X18, X15

    (278) 0x417f50 STR	D0, [X15, X19,UXTW #3]

    (278) 0x417f54 ADD	X19, X19, #1

    (278) 0x417f58 CMP	X19, X0,ASR #3

    (278) 0x417f5c B.CC	417a50

(281) 0x417f60 LDP	D8, D9, [SP, #96]

(281) 0x417f64 LDP	X19, X20, [SP, #16]

(281) 0x417f68 LDP	X27, X28, [SP, #80]

(281) 0x417f6c LDP	D10, D11, [SP, #112]

(281) 0x417f70 LDP	D12, D13, [SP, #128]

(281) 0x417f74 LDP	D14, D15, [SP, #144]

(281) 0x417f78 LDP	X21, X22, [SP, #32]

(281) 0x417f7c LDP	X23, X24, [SP, #48]

(281) 0x417f80 LDP	X25, X26, [SP, #64]

(281) 0x417f84 LDP	X29, X30, [SP], #192

(281) 0x417f88 RET

  (276) 0x417f8c LDR	W6, [X26, #144]

  (276) 0x417f90 CMP	W6, #0

  (276) 0x417f94 B.LE	417f38

  (276) 0x417f98 LDR	X7, [X26, #160]

  (276) 0x417f9c MOVI	D14, #0

  (276) 0x417fa0 SBFM	X21, X6, #0, #31

  (276) 0x417fa4 MOVZ	X24, #0

  (276) 0x417fa8 LDR	X1, [X26, #456]

  (276) 0x417fac LDR	X28, [X7, #24]

  (276) 0x417fb0 TBZ	W6, #0, 418090

  (276) 0x417fb4 LDRSW	X8, [X28]

  (276) 0x417fb8 LDR	X24, [X1, X8,LSL #3]

  (276) 0x417fbc CBZ	X24, 418084

  (276) 0x417fc0 LDR	D31, [X27]

  (276) 0x417fc4 LDR	D30, [X24, #8]

  (276) 0x417fc8 FCMPE	D31, D30

  (276) 0x417fcc B.GE	418084

  (276) 0x417fd0 LDR	D0, [X24, #568]

  (276) 0x417fd4 ADD	X0, SP, #184

  (276) 0x417fd8 STR	X1, [SP, #168]

  (276) 0x417fdc FMUL	D0, D31, D0

  (276) 0x417fe0 BL	404070

  (276) 0x417fe4 FMUL	D2, D0, D0

  (276) 0x417fe8 LDP	D25, D29, [X24, #24]

  (276) 0x417fec LDP	D19, D1, [X24, #88]

  (276) 0x417ff0 LDP	D28, D23, [X24, #40]

  (276) 0x417ff4 LDP	D21, D24, [X24, #104]

  (276) 0x417ff8 FMUL	D27, D2, D0

  (276) 0x417ffc FMUL	D4, D2, D29

  (276) 0x418000 LDP	D26, D6, [X24, #56]

  (276) 0x418004 FMUL	D5, D2, D1

  (276) 0x418008 LDP	D9, D20, [X24, #120]

  (276) 0x41800c FMADD	D3, D0, D28, D23

  (276) 0x418010 FMADD	D11, D27, D25, D4

  (276) 0x418014 LDR	D22, [SP, #184]

  (276) 0x418018 FMADD	D8, D0, D21, D24

  (276) 0x41801c FMADD	D16, D27, D19, D5

  (276) 0x418020 LDP	D12, D13, [X24, #72]

  (276) 0x418024 FMUL	D7, D2, D6

  (276) 0x418028 LDP	D28, D23, [X24, #136]

  (276) 0x41802c FMUL	D10, D2, D20

  (276) 0x418030 FCVTZS	W11, D22

  (276) 0x418034 LDR	X9, [X24, #536]

  (276) 0x418038 FMADD	D17, D27, D26, D7

  (276) 0x41803c FMADD	D18, D0, D12, D13

  (276) 0x418040 LDR	X1, [SP, #168]

  (276) 0x418044 FMADD	D30, D27, D9, D10

  (276) 0x418048 FADD	D25, D11, D3

  (276) 0x41804c FMADD	D0, D0, D28, D23

  (276) 0x418050 FADD	D31, D16, D8

  (276) 0x418054 SBFM	X12, X11, #61, #31

  (276) 0x418058 ADD	X13, X9, X12

  (276) 0x41805c LDR	D19, [X9, X12]

  (276) 0x418060 LDP	D1, D2, [X13, #8]

  (276) 0x418064 LDR	D4, [X13, #24]

  (276) 0x418068 FADD	D29, D17, D18

  (276) 0x41806c FADD	D21, D0, D30

  (276) 0x418070 FMADD	D14, D19, D25, D14

  (276) 0x418074 FMUL	D3, D31, D2

  (276) 0x418078 FMADD	D27, D4, D21, D14

  (276) 0x41807c FMADD	D24, D1, D29, D3

  (276) 0x418080 FADD	D14, D24, D27

  (276) 0x418084 MOVZ	X24, #1

  (276) 0x418088 CMP	X21, X24

  (276) 0x41808c B.EQ	418240

    (282) 0x418090 LDRSW	X14, [X28, X24,LSL #2]

    (282) 0x418094 LDR	X25, [X1, X14,LSL #3]

    (282) 0x418098 CBZ	X25, 418160

    (282) 0x41809c LDR	D5, [X27, X24,LSL #3]

    (282) 0x4180a0 LDR	D26, [X25, #8]

    (282) 0x4180a4 FCMPE	D5, D26

    (282) 0x4180a8 B.GE	418160

    (282) 0x4180ac LDR	D6, [X25, #568]

    (282) 0x4180b0 ADD	X0, SP, #184

    (282) 0x4180b4 STR	X1, [SP, #168]

    (282) 0x4180b8 FMUL	D0, D5, D6

    (282) 0x4180bc BL	404070

    (282) 0x4180c0 FMUL	D12, D0, D0

    (282) 0x4180c4 LDP	D7, D8, [X25, #24]

    (282) 0x4180c8 LDP	D10, D11, [X25, #88]

    (282) 0x4180cc LDP	D9, D20, [X25, #40]

    (282) 0x4180d0 LDP	D16, D17, [X25, #104]

    (282) 0x4180d4 FMUL	D22, D12, D0

    (282) 0x4180d8 FMUL	D18, D12, D8

    (282) 0x4180dc LDP	D23, D30, [X25, #56]

    (282) 0x4180e0 FMUL	D31, D12, D11

    (282) 0x4180e4 LDP	D1, D25, [X25, #120]

    (282) 0x4180e8 FMADD	D13, D0, D9, D20

    (282) 0x4180ec FMADD	D28, D22, D7, D18

    (282) 0x4180f0 LDR	D26, [SP, #184]

    (282) 0x4180f4 FMADD	D19, D0, D16, D17

    (282) 0x4180f8 FMADD	D24, D22, D10, D31

    (282) 0x4180fc LDP	D3, D21, [X25, #72]

    (282) 0x418100 FMUL	D29, D12, D30

    (282) 0x418104 LDP	D9, D20, [X25, #136]

    (282) 0x418108 FMUL	D2, D12, D25

    (282) 0x41810c FCVTZS	W18, D26

    (282) 0x418110 LDR	X15, [X25, #536]

    (282) 0x418114 FMADD	D4, D22, D23, D29

    (282) 0x418118 FMADD	D27, D0, D3, D21

    (282) 0x41811c LDR	X1, [SP, #168]

    (282) 0x418120 FMADD	D5, D22, D1, D2

    (282) 0x418124 FADD	D6, D28, D13

    (282) 0x418128 FMADD	D0, D0, D9, D20

    (282) 0x41812c FADD	D7, D24, D19

    (282) 0x418130 SBFM	X0, X18, #61, #31

    (282) 0x418134 ADD	X3, X15, X0

    (282) 0x418138 LDR	D10, [X15, X0]

    (282) 0x41813c LDP	D11, D12, [X3, #8]

    (282) 0x418140 LDR	D18, [X3, #24]

    (282) 0x418144 FADD	D8, D4, D27

    (282) 0x418148 FADD	D16, D0, D5

    (282) 0x41814c FMADD	D14, D10, D6, D14

    (282) 0x418150 FMUL	D13, D7, D12

    (282) 0x418154 FMADD	D22, D18, D16, D14

    (282) 0x418158 FMADD	D17, D11, D8, D13

    (282) 0x41815c FADD	D14, D17, D22

    (282) 0x418160 ADD	X24, X24, #1

    (282) 0x418164 LDRSW	X16, [X28, X24,LSL #2]

    (282) 0x418168 LDR	X25, [X1, X16,LSL #3]

    (282) 0x41816c CBZ	X25, 418234

    (282) 0x418170 LDR	D31, [X27, X24,LSL #3]

    (282) 0x418174 LDR	D23, [X25, #8]

    (282) 0x418178 FCMPE	D31, D23

    (282) 0x41817c B.GE	418234

    (282) 0x418180 LDR	D30, [X25, #568]

    (282) 0x418184 ADD	X0, SP, #184

    (282) 0x418188 STR	X1, [SP, #168]

    (282) 0x41818c FMUL	D0, D31, D30

    (282) 0x418190 BL	404070

    (282) 0x418194 FMUL	D4, D0, D0

    (282) 0x418198 LDP	D1, D29, [X25, #24]

    (282) 0x41819c LDP	D19, D3, [X25, #88]

    (282) 0x4181a0 LDP	D25, D2, [X25, #40]

    (282) 0x4181a4 LDP	D21, D24, [X25, #104]

    (282) 0x4181a8 FMUL	D27, D4, D0

    (282) 0x4181ac FMUL	D28, D4, D29

    (282) 0x4181b0 LDP	D7, D8, [X25, #56]

    (282) 0x4181b4 FMUL	D6, D4, D3

    (282) 0x4181b8 LDP	D10, D20, [X25, #120]

    (282) 0x4181bc FMADD	D5, D0, D25, D2

    (282) 0x4181c0 FMADD	D12, D27, D1, D28

    (282) 0x4181c4 LDR	D23, [SP, #184]

    (282) 0x4181c8 FMADD	D9, D0, D21, D24

    (282) 0x4181cc FMADD	D17, D27, D19, D6

    (282) 0x4181d0 LDP	D13, D16, [X25, #72]

    (282) 0x4181d4 FMUL	D26, D4, D8

    (282) 0x4181d8 LDP	D25, D2, [X25, #136]

    (282) 0x4181dc FMUL	D11, D4, D20

    (282) 0x4181e0 FCVTZS	W10, D23

    (282) 0x4181e4 LDR	X2, [X25, #536]

    (282) 0x4181e8 FMADD	D18, D27, D7, D26

    (282) 0x4181ec FMADD	D22, D0, D13, D16

    (282) 0x4181f0 LDR	X1, [SP, #168]

    (282) 0x4181f4 FMADD	D30, D27, D10, D11

    (282) 0x4181f8 FADD	D1, D12, D5

    (282) 0x4181fc FMADD	D0, D0, D25, D2

    (282) 0x418200 FADD	D31, D17, D9

    (282) 0x418204 SBFM	X4, X10, #61, #31

    (282) 0x418208 ADD	X5, X2, X4

    (282) 0x41820c LDR	D19, [X2, X4]

    (282) 0x418210 LDP	D3, D4, [X5, #8]

    (282) 0x418214 LDR	D28, [X5, #24]

    (282) 0x418218 FADD	D29, D18, D22

    (282) 0x41821c FADD	D21, D0, D30

    (282) 0x418220 FMADD	D14, D19, D1, D14

    (282) 0x418224 FMUL	D5, D31, D4

    (282) 0x418228 FMADD	D27, D28, D21, D14

    (282) 0x41822c FMADD	D24, D3, D29, D5

    (282) 0x418230 FADD	D14, D24, D27

    (282) 0x418234 ADD	X24, X24, #1

    (282) 0x418238 CMP	X21, X24

    (282) 0x41823c B.NE	418090

  (276) 0x418240 FSUB	D15, D15, S14

  (276) 0x418244 B	417f38

0x418248 HINT	#0

0x41824c HINT	#0

0x418250 HINT	#0

0x418254 HINT	#0

0x418258 HINT	#0

0x41825c HINT	#0

Coverage (%)	Name	Source Location	Module
►98.55+	qmcplusplus::WaveFunction::eva[...]	stl_vector.h:992	exec
○	main._omp_fn.1	NonLocalPP.hpp:126	exec
○	gomp_thread_start	team.c:130	libgomp.so.1.0.0
○	start_thread		libc.so.6
○	thread_start		libc.so.6

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is poorly vectorized. Only 79% of vector register length is used (average across all VPU instructions). By fully vectorizing your function, you can lower the cost of an iteration from 5.50 to 5.25 cycles (1.05x speedup).

Details

23% of VPU instructions are used in vector version (process two or more data elements in vector registers):

36% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.42	1.42	1.33	1.33	1.25	1.25	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50
cycles	0.50	0.50	1.42	1.42	1.33	1.33	1.25	1.25	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Overall L1	5.50

Vectorization ratios

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

3% of peak load performance is reached (2.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
63% of peak store performance is reached (30.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 417a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #832]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X23, X0, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 417f78 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X20, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run gcc_0

Source file and lines	OneBodyJastrowRef.h:132-155
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/stl_vector.h:993,1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/include/c++/14.2.0/bits/shared_ptr_base.h:1667
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/OneBodyJastrowRef.h:132-155
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313-316
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/BsplineFunctor.h:166-173,179-182,231-260

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 5.50 to 2.00 cycles (2.75x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

23% of VPU instructions are used in vector version (process two or more data elements in vector registers):

36% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
0% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Since your execution units are vector units, only a fully vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 16 bytes. The binary function is storing 168 bytes.

General properties

nb instructions	26
loop length	104
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

2.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	0.50	0.50	1.42	1.42	1.33	1.33	1.25	1.25	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50
cycles	0.50	0.50	1.42	1.42	1.33	1.33	1.25	1.25	2.00	2.00	0.00	0.00	5.50	5.50	1.00	3.50	3.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	2.50
Overall L1	5.50

Vectorization ratios

all	23%
load	NA (no load vectorizable/vectorized instructions)
store	36%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 5.50 cycles. At this rate:

3% of peak load performance is reached (2.91 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
63% of peak store performance is reached (30.55 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 417a00

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
STP X29, X30, [SP, #832]!	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X21, X22, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X22, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X23, X24, [SP, #48]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X23, X0, #216	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X25, X26, [SP, #64]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ORR X26, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STR X2, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDP X1, X0, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
CMP X1, X0	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
B.EQ 417f78 <_ZN16miniqmcreference17OneBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE14evaluateRatiosERNS1_18VirtualParticleSetERSt6vectorIdSaIdEE+0x578>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
STP X19, X20, [SP, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
MOVZ X20, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ X19, #0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP X27, X28, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP D8, D9, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D10, D11, [SP, #112]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D12, D13, [SP, #128]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP D14, D15, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::OneBodyJastrowRef >::evaluateRatios(qmcplusplus::VirtualParticleSet&, std::vector >&)–	0.05	0.07
▼Loop 281 - OneBodyJastrowRef.h:134-155 - exec–	0.00	0.00
▼Loop 276 - BsplineFunctor.h:166-260 - exec–	0.00	0.00
▼Loop 278 - OneBodyJastrowRef.h:134-146 - exec–	0.01	0.02
▼Loop 277 - OneBodyJastrowRef.h:143-146 - exec–	0.00	0.01
○Loop 279 - BsplineFunctor.h:236-241 - exec	0.03	0.04
○Loop 280 - BsplineFunctor.h:246-260 - exec	0.00	0.01
○Loop 282 - OneBodyJastrowRef.h:151-155 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code