OV - exec - Function void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<double, 3u>, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> >, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> > >(qmcplusplus::TinyVector<double, 3u> const&, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> > const&, double*, qmcplusplus::VectorSoAContainer<double, 3u, qmcplusplus::Mallocator<double, 32ul> >&, int, int, int) const

	Function: void qmcplusplus::DTD_BConds<double, 3u, 40>::computeDistances<qmcplusplus::TinyVector<dou ...	Module: exec	Source: ParticleBConds3DSoa.h:234-257	Coverage (incl. loops): 1.82% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h: 234 - 257

--------------------------------------------------------------------------------

234: #pragma omp simd aligned(temp_r, px, py, pz, dx, dy, dz: QMC_SIMD_ALIGNMENT)

235:     for (int iat = first; iat < last; ++iat)

236:     {

237:       T displ_0 = px[iat] - x0;

238:       T displ_1 = py[iat] - y0;

239:       T displ_2 = pz[iat] - z0;

240:

241:       T ar_0 = displ_0 * g00 + displ_1 * g10 + displ_2 * g20;

242:       T ar_1 = displ_0 * g01 + displ_1 * g11 + displ_2 * g21;

243:       T ar_2 = displ_0 * g02 + displ_1 * g12 + displ_2 * g22;

244:

245:       //put them in the box

246:       ar_0 -= round(ar_0);

247:       ar_1 -= round(ar_1);

248:       ar_2 -= round(ar_2);

249:

250:       //unit2cart

251:       dx[iat] = ar_0 * r00 + ar_1 * r10 + ar_2 * r20;

252:       dy[iat] = ar_0 * r01 + ar_1 * r11 + ar_2 * r21;

253:       dz[iat] = ar_0 * r02 + ar_1 * r12 + ar_2 * r22;

254:

255:       temp_r[iat] = std::sqrt(dx[iat] * dx[iat] + dy[iat] * dy[iat] + dz[iat] * dz[iat]);

256:     }

257:   }

0x452b20 SUBS	W15, W6, W5

0x452b24 B.LE	452d58

0x452b28 LDP	D0, D1, [X1]

0x452b2c LDR	D2, [X1, #16]

0x452b30 LDR	X8, [X2, #24]

0x452b34 ORR	W14, WZR, WZR

0x452b38 LDR	X10, [X2, #8]

0x452b3c ADD	X9, X8, X10,LSL #3

0x452b40 LDR	X11, [X4, #24]

0x452b44 LDR	X13, [X4, #8]

0x452b48 ADD	X10, X8, X10,LSL #4

0x452b4c ADD	X12, X11, X13,LSL #3

0x452b50 ADD	X13, X11, X13,LSL #4

0x452b54 CMP	W15, #2

0x452b58 B.CC	452c7c

0x452b5c SUB	W16, W6, #1

0x452b60 CMP	W16, W5

0x452b64 B.LT	452c7c

0x452b68 DUP	V3.2D, V0.D[0]

0x452b6c DUP	V4.2D, V1.D[0]

0x452b70 DUP	V5.2D, V2.D[0]

0x452b74 AND	W14, W15, #1951

0x452b78 ORR	W17, WZR, W5

0x452b7c ORR	W16, WZR, W14

(1297) 0x452b80 SBFM	X18, X17, #61, #31

(1297) 0x452b84 LDUR	Q17, [X0, #72]

(1297) 0x452b88 LDP	Q19, Q18, [X0, #80]

(1297) 0x452b8c ADD	W17, W17, #2

(1297) 0x452b90 SUBS	W16, W16, #2

(1297) 0x452b94 LDR	Q6, [X8, X18]

(1297) 0x452b98 LDR	Q7, [X9, X18]

(1297) 0x452b9c LDR	Q16, [X10, X18]

(1297) 0x452ba0 FSUB	V6.2D, V6.2D, V3.2D

(1297) 0x452ba4 FSUB	V7.2D, V7.2D, V4.2D

(1297) 0x452ba8 FSUB	V16.2D, V16.2D, V5.2D

(1297) 0x452bac FMUL	V17.2D, V6.2D, V17.D[0]

(1297) 0x452bb0 FMUL	V18.2D, V6.2D, V18.D[0]

(1297) 0x452bb4 FMLA	V17.2D, V7.2D, V19.D[0]

(1297) 0x452bb8 LDUR	Q19, [X0, #104]

(1297) 0x452bbc FMLA	V18.2D, V7.2D, V19.D[0]

(1297) 0x452bc0 LDUR	Q19, [X0, #88]

(1297) 0x452bc4 FMLA	V17.2D, V16.2D, V19.D[0]

(1297) 0x452bc8 LDR	Q19, [X0, #112]

(1297) 0x452bcc FMLA	V18.2D, V16.2D, V19.D[0]

(1297) 0x452bd0 LDUR	Q19, [X0, #120]

(1297) 0x452bd4 FMUL	V6.2D, V6.2D, V19.D[0]

(1297) 0x452bd8 LDR	Q19, [X0, #128]

(1297) 0x452bdc FMLA	V6.2D, V7.2D, V19.D[0]

(1297) 0x452be0 LDR	D7, [X0, #136]

(1297) 0x452be4 FMLA	V6.2D, V16.2D, V7.D[0]

(1297) 0x452be8 FRINTA	V7.2D, V17.2D

(1297) 0x452bec FRINTA	V16.2D, V18.2D

(1297) 0x452bf0 FSUB	V7.2D, V17.2D, V7.2D

(1297) 0x452bf4 FSUB	V16.2D, V18.2D, V16.2D

(1297) 0x452bf8 LDUR	Q18, [X0, #8]

(1297) 0x452bfc FRINTA	V17.2D, V6.2D

(1297) 0x452c00 FSUB	V6.2D, V6.2D, V17.2D

(1297) 0x452c04 LDR	Q17, [X0]

(1297) 0x452c08 FMUL	V17.2D, V7.2D, V17.D[0]

(1297) 0x452c0c FMLA	V17.2D, V16.2D, V18.D[0]

(1297) 0x452c10 LDR	Q18, [X0, #16]

(1297) 0x452c14 FMLA	V17.2D, V6.2D, V18.D[0]

(1297) 0x452c18 STR	Q17, [X11, X18]

(1297) 0x452c1c LDUR	Q17, [X0, #24]

(1297) 0x452c20 LDR	Q18, [X0, #32]

(1297) 0x452c24 FMUL	V17.2D, V7.2D, V17.D[0]

(1297) 0x452c28 FMLA	V17.2D, V16.2D, V18.D[0]

(1297) 0x452c2c LDUR	Q18, [X0, #40]

(1297) 0x452c30 FMLA	V17.2D, V6.2D, V18.D[0]

(1297) 0x452c34 STR	Q17, [X12, X18]

(1297) 0x452c38 LDR	Q17, [X0, #48]

(1297) 0x452c3c FMUL	V7.2D, V7.2D, V17.D[0]

(1297) 0x452c40 LDUR	Q17, [X0, #56]

(1297) 0x452c44 FMLA	V7.2D, V16.2D, V17.D[0]

(1297) 0x452c48 LDR	Q16, [X0, #64]

(1297) 0x452c4c FMLA	V7.2D, V6.2D, V16.D[0]

(1297) 0x452c50 STR	Q7, [X13, X18]

(1297) 0x452c54 LDR	Q6, [X11, X18]

(1297) 0x452c58 LDR	Q16, [X12, X18]

(1297) 0x452c5c FMUL	V6.2D, V6.2D, V6.2D

(1297) 0x452c60 FMLA	V6.2D, V7.2D, V7.2D

(1297) 0x452c64 FMLA	V6.2D, V16.2D, V16.2D

(1297) 0x452c68 FSQRT	V6.2D, V6.2D

(1297) 0x452c6c STR	Q6, [X3, X18]

(1297) 0x452c70 B.NE	452b80

0x452c74 CMP	W15, W14

0x452c78 B.EQ	452d58

0x452c7c ADD	W14, W14, W5

(1296) 0x452c80 LDR	D3, [X8, X14,SXTW #3]

(1296) 0x452c84 LDR	D4, [X9, X14,SXTW #3]

(1296) 0x452c88 LDP	D6, D7, [X0, #72]

(1296) 0x452c8c FSUB	D3, D3, S0

(1296) 0x452c90 FSUB	D4, D4, S1

(1296) 0x452c94 LDR	D5, [X10, X14,SXTW #3]

(1296) 0x452c98 FSUB	D5, D5, S2

(1296) 0x452c9c FMUL	D6, D6, D3

(1296) 0x452ca0 FMADD	D6, D7, D4, D6

(1296) 0x452ca4 LDP	D7, D16, [X0, #88]

(1296) 0x452ca8 FMADD	D6, D7, D5, D6

(1296) 0x452cac FMUL	D7, D16, D3

(1296) 0x452cb0 LDP	D16, D17, [X0, #104]

(1296) 0x452cb4 FMADD	D7, D16, D4, D7

(1296) 0x452cb8 FMADD	D7, D17, D5, D7

(1296) 0x452cbc LDP	D16, D17, [X0, #120]

(1296) 0x452cc0 FMUL	D3, D16, D3

(1296) 0x452cc4 FMADD	D3, D17, D4, D3

(1296) 0x452cc8 LDR	D4, [X0, #136]

(1296) 0x452ccc FMADD	D3, D4, D5, D3

(1296) 0x452cd0 FRINTA	D4, D6

(1296) 0x452cd4 FRINTA	D5, D7

(1296) 0x452cd8 FSUB	D4, D6, S4

(1296) 0x452cdc FSUB	D5, D7, S5

(1296) 0x452ce0 FRINTA	D6, D3

(1296) 0x452ce4 FSUB	D3, D3, S6

(1296) 0x452ce8 LDP	D6, D7, [X0]

(1296) 0x452cec FMUL	D6, D6, D4

(1296) 0x452cf0 FMADD	D6, D7, D5, D6

(1296) 0x452cf4 LDR	D7, [X0, #16]

(1296) 0x452cf8 FMADD	D6, D3, D7, D6

(1296) 0x452cfc STR	D6, [X11, X14,SXTW #3]

(1296) 0x452d00 LDP	D6, D7, [X0, #24]

(1296) 0x452d04 FMUL	D6, D6, D4

(1296) 0x452d08 FMADD	D6, D7, D5, D6

(1296) 0x452d0c LDR	D7, [X0, #40]

(1296) 0x452d10 FMADD	D6, D7, D3, D6

(1296) 0x452d14 STR	D6, [X12, X14,SXTW #3]

(1296) 0x452d18 LDP	D6, D7, [X0, #48]

(1296) 0x452d1c FMUL	D4, D6, D4

(1296) 0x452d20 FMADD	D4, D7, D5, D4

(1296) 0x452d24 LDR	D5, [X0, #64]

(1296) 0x452d28 FMADD	D3, D5, D3, D4

(1296) 0x452d2c STR	D3, [X13, X14,SXTW #3]

(1296) 0x452d30 LDR	D4, [X11, X14,SXTW #3]

(1296) 0x452d34 LDR	D5, [X12, X14,SXTW #3]

(1296) 0x452d38 FMUL	D4, D4, D4

(1296) 0x452d3c FMADD	D3, D3, D3, D4

(1296) 0x452d40 FMADD	D3, D5, D5, D3

(1296) 0x452d44 FSQRT	D3, D3

(1296) 0x452d48 STR	D3, [X3, X14,SXTW #3]

(1296) 0x452d4c ADD	W14, W14, #1

(1296) 0x452d50 CMP	W6, W14

(1296) 0x452d54 B.NE	452c80

0x452d58 RET

0x452d5c HINT	#0

Coverage (%)	Name	Source Location	Module
►95.77+	qmcplusplus::ParticleSet::comp[...]	stl_vector.h:993	exec
○	main.omp_outlined.63	miniqmc.cpp:437	exec
○	__kmp_invoke_microtask		libomp.so
►4.23+	qmcplusplus::ParticleSet::upda[...]	stl_vector.h:993	exec
○	main.omp_outlined	miniqmc.cpp:390	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ParticleBConds3DSoa.h:234-257
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is probably not vectorized. Only 51% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 3.50 to 2.50 cycles (1.40x speedup).

Details

Store and arithmetical VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00
cycles	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.50

Vectorization ratios

all	20%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 452b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUBS W15, W6, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 452d58 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W14, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X9, X8, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X8, X10,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X11, X13,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, X13,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 452c7c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W16, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 452c7c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V4.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V5.2D, V2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND W14, W15, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W17, WZR, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W16, WZR, W14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W15, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 452d58 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	ParticleBConds3DSoa.h:234-257
Module	exec

The function is defined in /home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/Lattice/ParticleBConds3DSoa.h:234-257.

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 3.50 to 1.00 cycles (3.50x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

No data for this section

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 56 bytes.

General properties

nb instructions	29
loop length	116
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

3.50 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00
cycles	2.50	2.50	2.33	2.33	2.33	2.33	2.33	2.33	0.75	0.75	0.75	0.75	2.00	2.00	2.00	0.00	0.00

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	3.50
Overall L1	3.50

Vectorization ratios

all	20%
load	16%
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	37%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 3.50 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 452b20

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUBS W15, W6, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 452d58 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP D0, D1, [X1]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D2, [X1, #16]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDR X8, [X2, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ORR W14, WZR, WZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X10, [X2, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X9, X8, X10,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR X11, [X4, #24]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
LDR X13, [X4, #8]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
ADD X10, X8, X10,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X12, X11, X13,LSL #3	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ADD X13, X11, X13,LSL #4	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
CMP W15, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.CC 452c7c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB W16, W6, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W16, W5	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LT 452c7c <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x15c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
DUP V3.2D, V0.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V4.2D, V1.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
DUP V5.2D, V2.D[0]	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
AND W14, W15, #1951	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W17, WZR, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR W16, WZR, W14	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
CMP W15, W14	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 452d58 <_ZNK11qmcplusplus10DTD_BCondsIdLj3ELi40EE16computeDistancesINS_10TinyVectorIdLj3EEENS_18VectorSoAContainerIdLj3ENS_10MallocatorIdLm32EEEEES8_EEvRKT_RKT0_PdRT1_iii+0x238>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD W14, W14, W5	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼void qmcplusplus::DTD_BConds::computeDistances, qmcplusplus::VectorSoAContainer >, qmcplusplus::VectorSoAContainer–	1.82	2.49
○Loop 1297 - ParticleBConds3DSoa.h:234-255 - exec	1.81	2.47
○Loop 1296 - ParticleBConds3DSoa.h:234-255 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code