OV - exec - Function main.omp

	Function: main.omp_outlined.63	Module: exec	Source: miniqmc.cpp:411-475 [...]	Coverage (incl. loops): 0.01% \| (excl. loops): 0.00%

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h: 242 - 249

--------------------------------------------------------------------------------

242:   ScopeGuard(TIMER& t) : timer(t) { timer.start(); }

[...]

249:   ~ScopeGuard() { timer.stop(); }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/random.tcc: 404 - 3374

--------------------------------------------------------------------------------

404:       for (size_t __k = 0; __k < (__n - __m); ++__k)

405:         {

406: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

407: 			   | (_M_x[__k + 1] & __lower_mask));

408: 	  _M_x[__k] = (_M_x[__k + __m] ^ (__y >> 1)

409: 		       ^ ((__y & 0x01) ? __a : 0));

410:         }

411:

412:       for (size_t __k = (__n - __m); __k < (__n - 1); ++__k)

413: 	{

414: 	  _UIntType __y = ((_M_x[__k] & __upper_mask)

415: 			   | (_M_x[__k + 1] & __lower_mask));

416: 	  _M_x[__k] = (_M_x[__k + (__m - __n)] ^ (__y >> 1)

417: 		       ^ ((__y & 0x01) ? __a : 0));

418: 	}

419:

420:       _UIntType __y = ((_M_x[__n - 1] & __upper_mask)

421: 		       | (_M_x[0] & __lower_mask));

422:       _M_x[__n - 1] = (_M_x[__m - 1] ^ (__y >> 1)

423: 		       ^ ((__y & 0x01) ? __a : 0));

[...]

458:       if (_M_p >= state_size)

459: 	_M_gen_rand();

460:

461:       // Calculate o(x(i)).

462:       result_type __z = _M_x[_M_p++];

463:       __z ^= (__z >> __u) & __d;

464:       __z ^= (__z << __s) & __b;

465:       __z ^= (__z << __t) & __c;

466:       __z ^= (__z >> __l);

[...]

3365:       for (size_t __k = __m; __k != 0; --__k)

3366: 	{

3367: 	  __sum += _RealType(__urng() - __urng.min()) * __tmp;

3368: 	  __tmp *= __r;

3369: 	}

3370:       __ret = __sum / __tmp;

3371:       if (__builtin_expect(__ret >= _RealType(1), 0))

3372: 	{

3373: #if _GLIBCXX_USE_C99_MATH_FUNCS

3374: 	  __ret = std::nextafter(_RealType(1), _RealType(0));

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp: 411 - 475

--------------------------------------------------------------------------------

411: #pragma omp parallel for reduction(+ : my_accepted)

412:     for (int iw = 0; iw < nmovers; iw++)

413:     {

414:       auto& els          = *mover_list[iw]->els_ptr;

415:       auto& random_th    = mover_list[iw]->rng;

416:       auto& wavefunction = mover_list[iw]->wavefunction;

417:       auto& ecp          = mover_list[iw]->nlpp;

418:

419:       ParticlePos delta(nels);

420:       ParticlePos rOnSphere(nknots);

421:

422:       aligned_vector<RealType> ur(nels);

423:

424:       Timers[Timer_Diffusion].get().start();

425:       for (int l = 0; l < nsubsteps; ++l) // drift-and-diffusion

426:       {

427:         random_th.generate_uniform(ur.data(), nels);

428:         random_th.generate_normal(&delta[0][0], nels3);

429:         for (int iel = 0; iel < nels; ++iel)

430:         {

431:           // Compute gradient at the current position

432:           Timers[Timer_evalGrad].get().start();

433:           PosType grad_now = wavefunction.evalGrad(els, iel);

434:           Timers[Timer_evalGrad].get().stop();

435:

436:           // Construct trial move

437:           els.makeMove(iel, delta[iel]);

438:

439:           // Compute gradient at the trial position

440:           Timers[Timer_ratioGrad].get().start();

441:           PosType grad_new;

442:           wavefunction.ratioGrad(els, iel, grad_new);

443:           Timers[Timer_ratioGrad].get().stop();

444:

445:           // Accept/reject the trial move

446:           if (ur[iel] < accept) // MC

447:           {

448:             // Update position, and update temporary storage

449:             Timers[Timer_Update].get().start();

450:             wavefunction.acceptMove(els, iel);

451:             Timers[Timer_Update].get().stop();

452:             els.acceptMove(iel);

453:             my_accepted++;

454:           }

455:           else

456:           {

457:             els.rejectMove(iel);

458:             wavefunction.restore(iel);

459:           }

460:         } // iel

461:         wavefunction.completeUpdates();

462:       }   // substeps

463:

464:       els.donePbyP();

465:

466:       // evaluate Kinetic Energy

467:       wavefunction.evaluateGL(els);

468:

469:       Timers[Timer_Diffusion].get().stop();

470:

471:       // Compute NLPP energy using integral over spherical points

472:       {

473:         ecp.randomize(rOnSphere); // pick random sphere

474:         ScopedTimer local(Timers[Timer_ECP]);

475:         ecp.evaluate(els, wavefunction);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h: 939 - 940

--------------------------------------------------------------------------------

939:       for (; __first != __last; ++__first)

940: 	*__first = __value;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/StdRandom.h: 102 - 106

--------------------------------------------------------------------------------

102:     for (int i = 0; i < n; ++i)

103:       d[i] = uniform(myRNG);

104:   }

105:

106:   inline void generate_normal(T* restrict d, int n) { BoxMuller2::generate(*this, d, n); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 47 - 301

--------------------------------------------------------------------------------

47:   {

48:     if (n)

[...]

144:   virtual ~Vector() { free(); }

[...]

210:     if (nAllocated)

211:     {

212:       mAllocator.deallocate(X, nAllocated);

[...]

289:   T* X = nullptr;

[...]

300:     X          = mAllocator.allocate(n);

301:     nLocal     = n;

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleAttrib.h: 34 - 34

--------------------------------------------------------------------------------

34:   explicit inline ParticleAttrib(size_t n = 0) : __my_base(n), InUnit(0) {}

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/new_allocator.h: 134 - 172

--------------------------------------------------------------------------------

134: 	if (__builtin_expect(__n > this->_M_max_size(), false))

135: 	  {

136: 	    // _GLIBCXX_RESOLVE_LIB_DEFECTS

137: 	    // 3190. allocator::allocate sometimes returns too little storage

138: 	    if (__n > (std::size_t(-1) / sizeof(_Tp)))

139: 	      std::__throw_bad_array_new_length();

[...]

151: 	return static_cast<_Tp*>(_GLIBCXX_OPERATOR_NEW(__n * sizeof(_Tp)));

[...]

172: 	_GLIBCXX_OPERATOR_DELETE(_GLIBCXX_SIZED_DEALLOC(__p, __n));

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp: 76 - 78

--------------------------------------------------------------------------------

76:     if (n == 0)

77:       throw std::runtime_error("Mallocator::deallocate does not accept size 0 allocations.");

78:     free(p);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h: 99 - 1131

--------------------------------------------------------------------------------

99: 	: _M_start(), _M_finish(), _M_end_of_storage()

[...]

368: 	_M_deallocate(_M_impl._M_start,

369: 		      _M_impl._M_end_of_storage - _M_impl._M_start);

[...]

380: 	return __n != 0 ? _Tr::allocate(_M_impl, __n) : pointer();

[...]

388: 	if (__p)

[...]

398: 	this->_M_impl._M_start = this->_M_allocate(__n);

399: 	this->_M_impl._M_finish = this->_M_impl._M_start;

400: 	this->_M_impl._M_end_of_storage = this->_M_impl._M_start + __n;

[...]

1131: 	return *(this->_M_impl._M_start + __n);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/alloc_traits.h: 277 - 334

--------------------------------------------------------------------------------

277: 	  ::new((void*)__p) _Tp(std::forward<_Args>(__args)...);

[...]

334:       { return __a.allocate(__n); }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/unique_ptr.h: 193 - 193

--------------------------------------------------------------------------------

193:       pointer    _M_ptr() const noexcept { return std::get<0>(_M_t); }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/random.h: 2011 - 2011

--------------------------------------------------------------------------------

2011: 	  return (__aurng() * (__p.b() - __p.a())) + __p.a();

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h: 62 - 62

--------------------------------------------------------------------------------

62:       X[d] = T(0);

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/refwrap.h: 351 - 351

--------------------------------------------------------------------------------

351:       { return *_M_data; }

0x4092a0 SUB	SP, SP, #432

0x4092a4 STR	D10, [SP, #304]

0x4092a8 STP	D9, D8, [SP, #320]

0x4092ac STP	X29, X30, [SP, #336]

0x4092b0 STP	X28, X27, [SP, #352]

0x4092b4 STP	X26, X25, [SP, #368]

0x4092b8 STP	X24, X23, [SP, #384]

0x4092bc STP	X22, X21, [SP, #400]

0x4092c0 STP	X20, X19, [SP, #416]

0x4092c4 ADD	X29, SP, #336

0x4092c8 LDR	W8, [X2]

0x4092cc STR	X7, [SP, #88]

0x4092d0 STR	X6, [SP, #136]

0x4092d4 SUBS	W19, W8, #1

0x4092d8 STP	X5, X3, [SP, #40]

0x4092dc STR	X4, [SP, #120]

0x4092e0 B.LT	409ac4

0x4092e4 LDR	W1, [X0]

0x4092e8 MOVZ	W8, #1

0x4092ec ADRP	X0,

0x4092f0 ADD	X0, X0, #2928

0x4092f4 SUB	X3, X29, #48

0x4092f8 SUB	X4, X29, #20

0x4092fc SUB	X5, X29, #24

0x409300 STP	W19, WZR, [X29, #488]

0x409304 STUR	XZR, [X29, #460]

0x409308 STUR	W8, [X29, #468]

0x40930c SUB	X6, X29, #44

0x409310 MOVZ	W2, #34

0x409314 MOVZ	W7, #1

0x409318 STR	W8, [SP]

0x40931c STR	W1, [SP, #12]

0x409320 BL	404980

0x409324 LDP	W8, W28, [X29, #488]

0x409328 SBFM	X28, X28, #0, #31

0x40932c CMP	W8, W19

0x409330 CSEL	W8, W8, W19, #11

0x409334 STUR	W8, [X29, #488]

0x409338 CMP	W28, W8

0x40933c B.LE	4093c8

0x409340 LDR	W20, [SP, #12]

0x409344 LDR	X19, [X29, #112]

0x409348 ADRP	X0,

0x40934c ADD	X0, X0, #2952

0x409350 ORR	W1, WZR, W20

0x409354 BL	404b60

0x409358 SUB	X8, X29, #52

0x40935c ADRP	X6,

0x409360 ADRP	X0,

0x409364 ADD	X0, X0, #2976

0x409368 ADRP	X5, 409368

0x40936c ADD	X5, X5, #640

0x409370 ORR	W1, WZR, W20

0x409374 STUR	X8, [X29, #416]

0x409378 SUB	X4, X29, #96

0x40937c MOVZ	W2, #1

0x409380 MOVZ	W3, #8

0x409384 LDR	X6, [X6, #3896]

0x409388 BL	404a90

0x40938c CMP	W0, #2

0x409390 B.EQ	409abc

0x409394 CMP	W0, #1

0x409398 B.NE	409ac4

0x40939c LDR	W8, [X19]

0x4093a0 LDUR	W9, [X29, #460]

0x4093a4 ADRP	X2,

0x4093a8 ADRP	X0,

0x4093ac ADD	X0, X0, #2976

0x4093b0 ORR	W1, WZR, W20

0x4093b4 ADD	W8, W9, W8

0x4093b8 STR	W8, [X19]

0x4093bc LDR	X2, [X2, #3896]

0x4093c0 BL	4047f0

0x4093c4 B	409ac4

0x4093c8 LDR	X8, [X29, #104]

0x4093cc MOVZ	W20, #45279

0x4093d0 MOVK	W20, #39176

0x4093d4 STR	X8, [SP, #112]

0x4093d8 LDR	X8, [X29, #96]

0x4093dc STR	X8, [SP, #80]

0x4093e0 ADRP	X8, 4ad3e0

0x4093e4 LDR	Q0, [X8, #3616]

0x4093e8 BL	404900

0x4093ec ADRP	X8, 4ad3ec

0x4093f0 STUR	Q0, [X29, #352]

0x4093f4 LDR	Q0, [X8, #3632]

0x4093f8 BL	404900

0x4093fc ORR	V1.16B, V0.16B, V0.16B

0x409400 LDUR	Q0, [X29, #352]

0x409404 BL	4046b0

0x409408 BL	4047a0

0x40940c ADD	X8, X0, #52

0x409410 ORR	X9, XZR, #6177

0x409414 ORR	W22, WZR, #1887

0x409418 MOVZ	W25, #1

0x40941c FMOV	D8, #1.0000000

0x409420 MOVZ	W24, #4984

0x409424 MOVZ	W23, #5000

0x409428 DUP	V0.2D, X9

0x40942c UDIV	X8, X8, X0

0x409430 STUR	Q0, [X29, #352]

0x409434 STR	X8, [SP, #72]

0x409438 DUP	V2.2D, X22

0x40943c DUP	V0.2D, X25

0x409440 STP	Q0, Q2, [SP, #144]

0x409444 B	409458

    (33) 0x409448 LDURSW	X9, [X29, #488]

    (33) 0x40944c ADD	X28, X21, #1

    (33) 0x409450 CMP	X21, X9

    (33) 0x409454 B.GE	409340

    (33) 0x409458 LDR	X8, [SP, #48]

    (33) 0x40945c MOVZ	X21, #24

    (33) 0x409460 LDR	X8, [X8]

    (33) 0x409464 LDR	X27, [X8, X28,LSL #3]

    (33) 0x409468 LDR	X8, [X27, #5064]

    (33) 0x40946c STR	X8, [SP, #128]

    (33) 0x409470 LDR	X8, [SP, #120]

    (33) 0x409474 LDRSW	X8, [X8]

    (33) 0x409478 STR	X8, [SP, #64]

    (33) 0x40947c CBZ	W8, 4094c4

    (33) 0x409480 TBNZ	W8, #31, 409aec

    (33) 0x409484 ADD	X8, X8, X8,LSL #1

    (33) 0x409488 UBFM	X19, X8, #61, #60

    (33) 0x40948c ORR	X0, XZR, X19

    (33) 0x409490 BL	4044f0

    (33) 0x409494 STR	X0, [SP, #96]

    (33) 0x409498 ORR	X9, XZR, #3841

    (33) 0x40949c SUB	X8, X19, #24

    (33) 0x4094a0 LDR	X0, [SP, #96]

    (33) 0x4094a4 ORR	W1, WZR, WZR

    (33) 0x4094a8 MOVK	X9, #43691

    (33) 0x4094ac UMULH	X8, X8, X9

    (33) 0x4094b0 MOVZ	W9, #24

    (33) 0x4094b4 UBFM	X8, X8, #4, #63

    (33) 0x4094b8 MADD	X2, X8, X9, X21

    (33) 0x4094bc BL	404920

    (33) 0x4094c0 B	4094c8

    (33) 0x4094c4 STR	XZR, [SP, #96]

    (33) 0x4094c8 LDR	X8, [SP, #40]

    (33) 0x4094cc LDRSW	X26, [X8]

    (33) 0x4094d0 ADRP	X8,

    (33) 0x4094d4 ADD	X8, X8, #3184

    (33) 0x4094d8 STP	X8, X26, [X29, #928]

    (33) 0x4094dc SUB	X8, X29, #96

    (33) 0x4094e0 STP	XZR, XZR, [X8, #16]

    (33) 0x4094e4 CBZ	W26, 409528

    (33) 0x4094e8 TBNZ	W26, #31, 409aec

    (33) 0x4094ec ADD	X8, X26, X26,LSL #1

    (33) 0x4094f0 UBFM	X19, X8, #61, #60

    (33) 0x4094f4 ORR	X0, XZR, X19

    (33) 0x4094f8 BL	4044f0

    (33) 0x4094fc ORR	X9, XZR, #3841

    (33) 0x409500 SUB	X8, X19, #24

    (33) 0x409504 STP	X26, X0, [X29, #944]

    (33) 0x409508 STUR	X26, [X29, #424]

    (33) 0x40950c ORR	W1, WZR, WZR

    (33) 0x409510 MOVK	X9, #43691

    (33) 0x409514 UMULH	X8, X8, X9

    (33) 0x409518 MOVZ	W9, #24

    (33) 0x40951c UBFM	X8, X8, #4, #63

    (33) 0x409520 MADD	X2, X8, X9, X21

    (33) 0x409524 BL	404920

    (33) 0x409528 LDR	X1, [SP, #64]

    (33) 0x40952c ADRP	X8,

    (33) 0x409530 ADD	X8, X8, #3112

    (33) 0x409534 STUR	WZR, [X29, #452]

    (33) 0x409538 STP	XZR, XZR, [X29, #904]

    (33) 0x40953c STP	XZR, X8, [X29, #920]

    (33) 0x409540 CBZ	W1, 40956c

    (33) 0x409544 SUB	X0, X29, #120

    (33) 0x409548 BL	40b860

    (33) 0x40954c LDR	X8, [SP, #64]

    (33) 0x409550 STUR	X0, [X29, #392]

    (33) 0x409554 ORR	W1, WZR, WZR

    (33) 0x409558 UBFM	X2, X8, #61, #60

    (33) 0x40955c ADD	X19, X0, X8,LSL #3

    (33) 0x409560 BL	404920

    (33) 0x409564 ORR	X8, XZR, X19

    (33) 0x409568 B	409578

    (33) 0x40956c ORR	X19, XZR, XZR

    (33) 0x409570 ORR	X8, XZR, XZR

    (33) 0x409574 STUR	XZR, [X29, #392]

    (33) 0x409578 STP	X8, X19, [X29, #912]

    (33) 0x40957c LDR	X8, [SP, #136]

    (33) 0x409580 LDR	X8, [X8]

    (33) 0x409584 LDR	X0, [X8, #16]

    (33) 0x409588 BL	468a00

    (33) 0x40958c LDR	X8, [SP, #88]

    (33) 0x409590 STR	X28, [SP, #56]

    (33) 0x409594 LDR	W8, [X8]

    (33) 0x409598 CMP	W8, #1

    (33) 0x40959c B.LT	4099f0

  (27) 0x4095a0 ADD	X28, X27, #16

  (27) 0x4095a4 ADD	X21, X27, #1832

  (27) 0x4095a8 ORR	W8, WZR, WZR

  (27) 0x4095ac STR	W8, [SP, #108]

  (27) 0x4095b0 LDR	X8, [SP, #120]

  (27) 0x4095b4 LDR	W14, [X8]

  (27) 0x4095b8 CMP	W14, #1

  (27) 0x4095bc B.LT	409860

  (27) 0x4095c0 LDR	D0, [X27, #5024]

  (27) 0x4095c4 LDR	D9, [X27, #5016]

  (27) 0x4095c8 LDR	X8, [SP, #72]

  (27) 0x4095cc ORR	X26, XZR, XZR

  (27) 0x4095d0 CMP	X8, #1

  (27) 0x4095d4 LDUR	X15, [X29, #392]

  (27) 0x4095d8 LDR	X19, [X27, #5008]

  (27) 0x4095dc CSINC	X16, X8, XZR, #8

  (27) 0x4095e0 FSUB	D10, D0, S9

    (29) 0x4095e4 MOVI	D0, #0

    (29) 0x4095e8 FMOV	D1, #1.0000000

    (29) 0x4095ec ORR	X8, XZR, X16

    (29) 0x4095f0 B	409654

0x4095f4 HINT	#0

0x4095f8 HINT	#0

0x4095fc HINT	#0

      (30) 0x409600 ORR	X9, XZR, X19

      (30) 0x409604 ADD	X19, X19, #1

      (30) 0x409608 SUBS	X8, X8, #1

      (30) 0x40960c STR	X19, [X27, #5008]

      (30) 0x409610 LDR	X9, [X28, X9,LSL #3]

      (30) 0x409614 UBFM	X10, X9, #11, #42

      (30) 0x409618 EOR	X9, X10, X9

      (30) 0x40961c MOVZ	W10, #22144

      (30) 0x409620 MOVK	W10, #40236

      (30) 0x409624 AND	X10, X10, X9,LSL #7

      (30) 0x409628 EOR	X9, X10, X9

      (30) 0x40962c MOVZ	W10, #61382

      (30) 0x409630 AND	X10, X10, X9,LSL #15

      (30) 0x409634 EOR	X9, X10, X9

      (30) 0x409638 EOR	X9, X9, X9,LSR #18

      (30) 0x40963c UCVTF	D2, X9

      (30) 0x409640 MOVZ	X9, #16880

      (30) 0x409644 FMADD	D0, D1, D2, D0

      (30) 0x409648 FMOV	D2, X9

      (30) 0x40964c FMUL	D1, D1, D2

      (30) 0x409650 B.EQ	409804

      (30) 0x409654 CMP	X19, #624

      (30) 0x409658 B.CC	409600

      (30) 0x40965c LD1R	{V2.2D}, [X28]

      (30) 0x409660 LDUR	Q18, [X29, #352]

      (30) 0x409664 LDP	Q20, Q19, [SP, #144]

      (30) 0x409668 MOVN	X9, #1791

        (31) 0x40966c ADD	X10, X27, X9

        (31) 0x409670 DUP	V17.2D, X20

        (31) 0x409674 ADDS	X9, X9, #32

        (31) 0x409678 ADD	X11, X10, #1816

        (31) 0x40967c ADD	X12, X10, #1832

        (31) 0x409680 LDR	Q3, [X11]

        (31) 0x409684 EXT	V4.16B, V2.16B, V3.16B, #8

        (31) 0x409688 LDR	Q2, [X12]

        (31) 0x40968c AND	V6.16B, V3.16B, V19.16B

        (31) 0x409690 AND	V4.16B, V4.16B, V18.16B

        (31) 0x409694 ORR	V4.16B, V6.16B, V4.16B

        (31) 0x409698 LDR	Q6, [X10, X24]

        (31) 0x40969c EXT	V5.16B, V3.16B, V2.16B, #8

        (31) 0x4096a0 AND	V7.16B, V2.16B, V19.16B

        (31) 0x4096a4 AND	V3.16B, V3.16B, V20.16B

        (31) 0x4096a8 AND	V16.16B, V2.16B, V20.16B

        (31) 0x4096ac USHR	V4.2D, V4.2D, #1

        (31) 0x4096b0 AND	V5.16B, V5.16B, V18.16B

        (31) 0x4096b4 CMEQ	V3.2D, V3.2D, #0

        (31) 0x4096b8 CMEQ	V16.2D, V16.2D, #0

        (31) 0x4096bc ORR	V5.16B, V7.16B, V5.16B

        (31) 0x4096c0 LDR	Q7, [X10, X23]

        (31) 0x4096c4 BIC	V3.16B, V17.16B, V3.16B

        (31) 0x4096c8 BIC	V16.16B, V17.16B, V16.16B

        (31) 0x4096cc EOR	V3.16B, V6.16B, V3.16B

        (31) 0x4096d0 USHR	V5.2D, V5.2D, #1

        (31) 0x4096d4 EOR	V3.16B, V4.16B, V3.16B

        (31) 0x4096d8 EOR	V4.16B, V7.16B, V16.16B

        (31) 0x4096dc STR	Q3, [X10, #1808]

        (31) 0x4096e0 EOR	V4.16B, V5.16B, V4.16B

        (31) 0x4096e4 STR	Q4, [X10, #1824]

        (31) 0x4096e8 B.NE	40966c

      (30) 0x4096ec LDR	X10, [X27, #1816]

      (30) 0x4096f0 LDR	X11, [X27, #1824]

      (30) 0x4096f4 MOV	X9, V2.D[1]

      (30) 0x4096f8 AND	X9, X9, #6177

      (30) 0x4096fc AND	X12, X10, #6015

      (30) 0x409700 AND	X13, X10, #6177

      (30) 0x409704 SBFM	X10, X10, #0, #0

      (30) 0x409708 ORR	X9, X12, X9

      (30) 0x40970c AND	X12, X11, #6015

      (30) 0x409710 AND	X10, X10, X20

      (30) 0x409714 ORR	X12, X12, X13

      (30) 0x409718 LDR	X13, [X27, #4984]

      (30) 0x40971c EOR	X9, X13, X9,LSR #1

      (30) 0x409720 LDR	X13, [X27, #4992]

      (30) 0x409724 EOR	X9, X9, X10

      (30) 0x409728 SBFM	X10, X11, #0, #0

      (30) 0x40972c AND	X10, X10, X20

      (30) 0x409730 STR	X9, [X27, #1808]

      (30) 0x409734 AND	X9, X11, #6177

      (30) 0x409738 EOR	X12, X13, X12,LSR #1

      (30) 0x40973c EOR	X10, X12, X10

      (30) 0x409740 STR	X10, [X27, #1816]

      (30) 0x409744 LDR	X10, [X27, #1832]

      (30) 0x409748 AND	X11, X10, #6015

      (30) 0x40974c DUP	V2.2D, X10

      (30) 0x409750 ORR	X9, X11, X9

      (30) 0x409754 LDR	X11, [X27, #5000]

      (30) 0x409758 EOR	X9, X11, X9,LSR #1

      (30) 0x40975c SBFM	X11, X10, #0, #0

      (30) 0x409760 ORR	X10, XZR, X21

      (30) 0x409764 AND	X11, X11, X20

      (30) 0x409768 EOR	X9, X9, X11

      (30) 0x40976c STR	X9, [X27, #1824]

      (30) 0x409770 MOVZ	W9, #396

      (30) 0x409774 HINT	#0

      (30) 0x409778 HINT	#0

      (30) 0x40977c HINT	#0

        (32) 0x409780 LDUR	Q3, [X10, #8]

        (32) 0x409784 DUP	V4.2D, X22

        (32) 0x409788 SUB	X11, X10, #1816

        (32) 0x40978c SUBS	X9, X9, #2

        (32) 0x409790 EXT	V2.16B, V2.16B, V3.16B, #8

        (32) 0x409794 DUP	V5.2D, X25

        (32) 0x409798 AND	V4.16B, V3.16B, V4.16B

        (32) 0x40979c AND	V5.16B, V3.16B, V5.16B

        (32) 0x4097a0 DUP	V6.2D, X20

        (32) 0x4097a4 AND	V2.16B, V2.16B, V18.16B

        (32) 0x4097a8 CMEQ	V5.2D, V5.2D, #0

        (32) 0x4097ac ORR	V2.16B, V4.16B, V2.16B

        (32) 0x4097b0 LDR	Q4, [X11]

        (32) 0x4097b4 BIC	V5.16B, V6.16B, V5.16B

        (32) 0x4097b8 USHR	V2.2D, V2.2D, #1

        (32) 0x4097bc EOR	V4.16B, V4.16B, V5.16B

        (32) 0x4097c0 EOR	V2.16B, V2.16B, V4.16B

        (32) 0x4097c4 STR	Q2, [X10], #16

        (32) 0x4097c8 ORR	V2.16B, V3.16B, V3.16B

        (32) 0x4097cc B.NE	409780

      (30) 0x4097d0 LDR	X9, [X27, #5000]

      (30) 0x4097d4 LDR	X10, [X27, #16]

      (30) 0x4097d8 ORR	X19, XZR, XZR

      (30) 0x4097dc AND	X9, X9, #6177

      (30) 0x4097e0 AND	X11, X10, #6015

      (30) 0x4097e4 SBFM	X10, X10, #0, #0

      (30) 0x4097e8 ORR	X9, X11, X9

      (30) 0x4097ec LDR	X11, [X27, #3184]

      (30) 0x4097f0 AND	X10, X10, X20

      (30) 0x4097f4 EOR	X9, X11, X9,LSR #1

      (30) 0x4097f8 EOR	X9, X9, X10

      (30) 0x4097fc STR	X9, [X27, #5000]

      (30) 0x409800 B	409600

    (29) 0x409804 FDIV	D0, D0, D1

    (29) 0x409808 FCMP	D0, D8

    (29) 0x40980c B.GE	409828

    (29) 0x409810 FMADD	D0, D0, D10, D9

    (29) 0x409814 STR	D0, [X15, X26,LSL #3]

    (29) 0x409818 ADD	X26, X26, #1

    (29) 0x40981c CMP	X26, X14

    (29) 0x409820 B.NE	4095e4

  (27) 0x409824 B	409860

    (29) 0x409828 FMOV	D0, #1.0000000

    (29) 0x40982c MOVI	D1, #0

    (29) 0x409830 STP	X15, X14, [SP, #24]

    (29) 0x409834 STR	X16, [SP, #16]

    (29) 0x409838 BL	404a50

    (29) 0x40983c LDP	X16, X15, [SP, #16]

    (29) 0x409840 LDR	X14, [SP, #32]

    (29) 0x409844 FMADD	D0, D0, D10, D9

    (29) 0x409848 STR	D0, [X15, X26,LSL #3]

    (29) 0x40984c ADD	X26, X26, #1

    (29) 0x409850 CMP	X26, X14

    (29) 0x409854 B.NE	4095e4

  (27) 0x409858 HINT	#0

  (27) 0x40985c HINT	#0

  (27) 0x409860 LDR	X8, [SP, #80]

  (27) 0x409864 LDR	W2, [X8]

  (27) 0x409868 LDR	X1, [SP, #96]

  (27) 0x40986c ORR	X0, XZR, X27

  (27) 0x409870 BL	40bda0

  (27) 0x409874 LDR	X8, [SP, #120]

  (27) 0x409878 LDR	W8, [X8]

  (27) 0x40987c CMP	W8, #1

  (27) 0x409880 B.LT	4099c8

(28) 0x409884 LDR	X26, [SP, #96]

(28) 0x409888 ORR	X19, XZR, XZR

(28) 0x40988c B	4098b8

0x409890 HINT	#0

0x409894 HINT	#0

0x409898 HINT	#0

0x40989c HINT	#0

(28) 0x4098a0 LDR	X8, [SP, #120]

(28) 0x4098a4 ADD	X19, X19, #1

(28) 0x4098a8 ADD	X26, X26, #24

(28) 0x4098ac LDRSW	X8, [X8]

(28) 0x4098b0 CMP	X19, X8

(28) 0x4098b4 B.GE	4099c8

(28) 0x4098b8 LDR	X8, [SP, #136]

(28) 0x4098bc LDR	X8, [X8]

(28) 0x4098c0 LDR	X0, [X8, #40]

(28) 0x4098c4 BL	468a00

(28) 0x4098c8 LDR	X1, [SP, #128]

(28) 0x4098cc MOVZ	W8, #5072

(28) 0x4098d0 ORR	W2, WZR, W19

(28) 0x4098d4 ADD	X0, X27, X8

(28) 0x4098d8 BL	40d910

(28) 0x4098dc LDR	X8, [SP, #136]

(28) 0x4098e0 LDR	X8, [X8]

(28) 0x4098e4 LDR	X0, [X8, #40]

(28) 0x4098e8 BL	468b20

(28) 0x4098ec LDR	X0, [SP, #128]

(28) 0x4098f0 MOVZ	W3, #1

(28) 0x4098f4 ORR	W1, WZR, W19

(28) 0x4098f8 ORR	X2, XZR, X26

(28) 0x4098fc BL	4476a0

(28) 0x409900 LDR	X8, [SP, #136]

(28) 0x409904 LDR	X8, [X8]

(28) 0x409908 LDR	X0, [X8, #48]

(28) 0x40990c BL	468a00

(28) 0x409910 STP	XZR, XZR, [X29, #880]

(28) 0x409914 STUR	XZR, [X29, #384]

(28) 0x409918 LDR	X1, [SP, #128]

(28) 0x40991c MOVZ	W8, #5072

(28) 0x409920 SUB	X3, X29, #144

(28) 0x409924 ORR	W2, WZR, W19

(28) 0x409928 ADD	X0, X27, X8

(28) 0x40992c BL	40da30

(28) 0x409930 LDR	X8, [SP, #136]

(28) 0x409934 LDR	X8, [X8]

(28) 0x409938 LDR	X0, [X8, #48]

(28) 0x40993c BL	468b20

(28) 0x409940 LDUR	X8, [X29, #392]

(28) 0x409944 LDR	D0, [X8, X19,LSL #3]

(28) 0x409948 LDR	X8, [SP, #112]

(28) 0x40994c LDR	D1, [X8]

(28) 0x409950 FCMP	D0, D1

(28) 0x409954 B.GE	4099a8

(28) 0x409958 LDR	X8, [SP, #136]

(28) 0x40995c LDR	X8, [X8]

(28) 0x409960 LDR	X0, [X8, #56]

(28) 0x409964 BL	468a00

(28) 0x409968 LDR	X1, [SP, #128]

(28) 0x40996c MOVZ	W8, #5072

(28) 0x409970 ORR	W2, WZR, W19

(28) 0x409974 ADD	X0, X27, X8

(28) 0x409978 BL	40dc10

(28) 0x40997c LDR	X8, [SP, #136]

(28) 0x409980 LDR	X8, [X8]

(28) 0x409984 LDR	X0, [X8, #56]

(28) 0x409988 BL	468b20

(28) 0x40998c LDR	X0, [SP, #128]

(28) 0x409990 ORR	W1, WZR, W19

(28) 0x409994 BL	447e70

(28) 0x409998 LDUR	W8, [X29, #460]

(28) 0x40999c ADD	W8, W8, #1

(28) 0x4099a0 STUR	W8, [X29, #460]

(28) 0x4099a4 B	4098a0

(28) 0x4099a8 LDR	X0, [SP, #128]

(28) 0x4099ac ORR	W1, WZR, W19

(28) 0x4099b0 BL	448190

(28) 0x4099b4 MOVZ	W8, #5072

(28) 0x4099b8 ORR	W1, WZR, W19

(28) 0x4099bc ADD	X0, X27, X8

(28) 0x4099c0 BL	40dd50

(28) 0x4099c4 B	4098a0

  (27) 0x4099c8 MOVZ	W8, #5072

  (27) 0x4099cc ADD	X0, X27, X8

  (27) 0x4099d0 BL	40dce0

  (27) 0x4099d4 LDR	W9, [SP, #108]

  (27) 0x4099d8 LDR	X8, [SP, #88]

  (27) 0x4099dc ADD	W9, W9, #1

  (27) 0x4099e0 LDR	W8, [X8]

  (27) 0x4099e4 CMP	W9, W8

  (27) 0x4099e8 ORR	W8, WZR, W9

  (27) 0x4099ec B.LT	4095ac

    (33) 0x4099f0 LDR	X0, [SP, #128]

    (33) 0x4099f4 ORR	W1, WZR, WZR

    (33) 0x4099f8 BL	4481a0

    (33) 0x4099fc LDR	X21, [SP, #56]

    (33) 0x409a00 LDR	X1, [SP, #128]

    (33) 0x409a04 MOVZ	W8, #5072

    (33) 0x409a08 ADD	X0, X27, X8

    (33) 0x409a0c BL	40dd60

    (33) 0x409a10 LDR	X8, [SP, #136]

    (33) 0x409a14 LDR	X8, [X8]

    (33) 0x409a18 LDR	X0, [X8, #16]

    (33) 0x409a1c BL	468b20

    (33) 0x409a20 MOVZ	W8, #5184

    (33) 0x409a24 SUB	X1, X29, #96

    (33) 0x409a28 ADD	X0, X27, X8

    (33) 0x409a2c BL	40a7a0

    (33) 0x409a30 LDR	X8, [SP, #136]

    (33) 0x409a34 LDR	X8, [X8]

    (33) 0x409a38 LDR	X19, [X8, #24]

    (33) 0x409a3c ORR	X0, XZR, X19

    (33) 0x409a40 BL	468a00

    (33) 0x409a44 LDR	X1, [SP, #128]

    (33) 0x409a48 MOVZ	W8, #5184

    (33) 0x409a4c ADD	X0, X27, X8

    (33) 0x409a50 MOVZ	W8, #5072

    (33) 0x409a54 ADD	X2, X27, X8

    (33) 0x409a58 BL	40aa60

    (33) 0x409a5c ORR	X0, XZR, X19

    (33) 0x409a60 BL	468b20

    (33) 0x409a64 LDUR	X0, [X29, #392]

    (33) 0x409a68 CBZ	X0, 409a7c

    (33) 0x409a6c LDUR	X8, [X29, #408]

    (33) 0x409a70 CMP	X8, X0

    (33) 0x409a74 B.EQ	409af0

    (33) 0x409a78 BL	404c20

    (33) 0x409a7c ADRP	X8,

    (33) 0x409a80 ADD	X8, X8, #3184

    (33) 0x409a84 STUR	X8, [X29, #416]

    (33) 0x409a88 LDUR	X8, [X29, #432]

    (33) 0x409a8c CBZ	X8, 409aa0

    (33) 0x409a90 LDUR	X0, [X29, #440]

    (33) 0x409a94 ADD	X8, X8, X8,LSL #1

    (33) 0x409a98 UBFM	X1, X8, #61, #60

    (33) 0x409a9c BL	4044d0

    (33) 0x409aa0 LDR	X8, [SP, #64]

    (33) 0x409aa4 CBZ	W8, 409448

    (33) 0x409aa8 LDR	X0, [SP, #96]

    (33) 0x409aac ADD	X8, X8, X8,LSL #1

    (33) 0x409ab0 UBFM	X1, X8, #61, #60

    (33) 0x409ab4 BL	4044d0

    (33) 0x409ab8 B	409448

0x409abc LDUR	W8, [X29, #460]

0x409ac0 LDADD	W8, W8, [X19]

0x409ac4 LDP	D9, D8, [SP, #320]

0x409ac8 LDR	D10, [SP, #304]

0x409acc LDP	X20, X19, [SP, #416]

0x409ad0 LDP	X22, X21, [SP, #400]

0x409ad4 LDP	X24, X23, [SP, #384]

0x409ad8 LDP	X26, X25, [SP, #368]

0x409adc LDP	X28, X27, [SP, #352]

0x409ae0 LDP	X29, X30, [SP, #336]

0x409ae4 ADD	SP, SP, #432

0x409ae8 RET

0x409aec BL	4046d0

0x409af0 MOVZ	W0, #16

0x409af4 BL	404670

0x409af8 ORR	X19, XZR, X0

0x409afc ADRP	X1,

0x409b00 ADD	X1, X1, #3407

0x409b04 BL	404550

0x409b08 ADRP	X1,

0x409b0c ADRP	X2,

0x409b10 ORR	X0, XZR, X19

0x409b14 LDR	X1, [X1, #4008]

0x409b18 LDR	X2, [X2, #3952]

0x409b1c BL	404860

0x409b20 BL	409c40

0x409b24 ORR	X20, XZR, X0

0x409b28 ORR	X0, XZR, X19

0x409b2c BL	404a30

0x409b30 ORR	X0, XZR, X20

0x409b34 BL	409c40

0x409b38 BL	409c40

0x409b3c BL	409c40

0x409b40 BL	409c40

0x409b44 BL	409c40

0x409b48 BL	409c40

0x409b4c HINT	#0

Coverage (%)	Name	Source Location	Module
○100.00	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	miniqmc.cpp:411-475
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/random.tcc:404-423,458-466,3365-3374
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:411-475
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:939-940
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/StdRandom.h:102-106
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:47-48,144,210-212,289,300-301
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleAttrib.h:34
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/new_allocator.h:134-139,151,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:76-78
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:99,368-369,380,388,398-400,1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/alloc_traits.h:277,334
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/unique_ptr.h:193
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/random.h:2011
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/refwrap.h:351

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 4.17 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 59% of vector register length is used (average across all VPU instructions).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

36% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 260 bytes. The binary function is storing 296 bytes.

General properties

nb instructions	150
loop length	600
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	13.50	13.50	13.58	13.58	13.50	13.50	13.42	13.42	2.50	2.50	1.00	1.00	17.00	17.00	17.00	10.50	10.50
cycles	13.50	13.50	13.58	13.58	13.50	13.50	13.42	13.42	2.50	2.50	1.00	1.00	17.00	17.00	17.00	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.63
Overall L1	17.63-20.00

Vectorization ratios

INT

all	14%
load	36%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	36%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

13% of peak load performance is reached (13.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4092a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #432	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D10, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D9, D8, [SP, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUBS W19, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STP X5, X3, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.LT 409ac4 <main.omp_outlined.63+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4eb2ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2928	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W19, WZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR W8, [X29, #468]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #44	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 404980 <@plt_start@+0x560>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W28, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X28, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
CMP W8, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W28, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4093c8 <main.omp_outlined.63+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4eb348>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2952	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404b60 <@plt_start@+0x740>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #52	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <4ef35c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4eb360>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2976	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, 409368 <main.omp_outlined.63+0xc8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X5, X5, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X6, [X6, #3896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 404a90 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 409abc <main.omp_outlined.63+0x81c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 409ac4 <main.omp_outlined.63+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR W9, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X2, <4ef3a4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4eb3a8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2976	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W9, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2, #3896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4047f0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 409ac4 <main.omp_outlined.63+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W20, #45279	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVK W20, #39176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X8, 4ad3e0 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi32EE18DTABMultiWalkerMemC2Ev+0x60>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q0, [X8, #3616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 404900 <@plt_start@+0x4e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, 4ad3ec <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi32EE18DTABMultiWalkerMemC2Ev+0x6c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q0, [X29, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Q0, [X8, #3632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 404900 <@plt_start@+0x4e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V1.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDUR Q0, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 4046b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4047a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X0, #52	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, #6177	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W22, WZR, #1887	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV D8, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W24, #4984	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W23, #5000	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP V0.2D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
UDIV X8, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
STUR Q0, [X29, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP V2.2D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP V0.2D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STP Q0, Q2, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
B 409458 <main.omp_outlined.63+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR W8, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDADD W8, W8, [X19]																					N/A
LDP D9, D8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D10, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #432	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4046d0 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404670 <@plt_start@+0x250>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <4aeafc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #3407	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404550 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <4efb08>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X2, <4efb0c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X1, #4008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2, #3952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 404860 <@plt_start@+0x440>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404a30 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	miniqmc.cpp:411-475
Module	exec

The function is defined in:

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/NewTimer.h:242,249
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/random.tcc:404-423,458-466,3365-3374
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Drivers/miniqmc.cpp:411-475
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:939-940
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Utilities/StdRandom.h:102-106
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:47-48,144,210-212,289,300-301
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleAttrib.h:34
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/new_allocator.h:134-139,151,172
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/Mallocator.hpp:76-78
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:99,368-369,380,388,398-400,1131
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/alloc_traits.h:277,334
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/unique_ptr.h:193
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/random.h:2011
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/TinyVector.h:62
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/refwrap.h:351

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 20.00 to 4.17 cycles (4.80x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 59% of vector register length is used (average across all VPU instructions).

Details

14% of VPU instructions are used in vector version (process two or more data elements in vector registers):

36% of VPU loads are used in vector version.
15% of VPU stores are used in vector version.
0% of VPU addition or subtraction instructions are used in vector version.
5% of VPU instructions that are not load, store, addition, subtraction nor multiply instructions are used in vector version.

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 20.00 to 10.00 cycles (2.00x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 260 bytes. The binary function is storing 296 bytes.

General properties

nb instructions	150
loop length	600
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

17.63 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	13.50	13.50	13.58	13.58	13.50	13.50	13.42	13.42	2.50	2.50	1.00	1.00	17.00	17.00	17.00	10.50	10.50
cycles	13.50	13.50	13.58	13.58	13.50	13.50	13.42	13.42	2.50	2.50	1.00	1.00	17.00	17.00	17.00	10.50	10.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

5.00-20.00

Cycles summary

Front-end	17.63
Overall L1	17.63-20.00

Vectorization ratios

INT

all	14%
load	36%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
other	5%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	14%
load	36%
store	15%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	0%
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	5%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 20.00 cycles. At this rate:

13% of peak load performance is reached (13.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
30% of peak store performance is reached (14.80 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 4092a0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #432	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D10, [SP, #304]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP D9, D8, [SP, #320]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #336	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR W8, [X2]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X7, [SP, #88]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X6, [SP, #136]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUBS W19, W8, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	N/A
STP X5, X3, [SP, #40]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STR X4, [SP, #120]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B.LT 409ac4 <main.omp_outlined.63+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W1, [X0]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W8, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X0, <4eb2ec>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2928	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
SUB X3, X29, #48	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X4, X29, #20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
SUB X5, X29, #24	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STP W19, WZR, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR XZR, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR W8, [X29, #468]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
SUB X6, X29, #44	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W2, #34	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W7, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR W8, [SP]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
STR W1, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
BL 404980 <@plt_start@+0x560>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDP W8, W28, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
SBFM X28, X28, #0, #31	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (100.0%)
CMP W8, W19	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
CSEL W8, W8, W19, #11	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR W8, [X29, #488]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
CMP W28, W8	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.LE 4093c8 <main.omp_outlined.63+0x128>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W20, [SP, #12]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
LDR X19, [X29, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
ADRP X0, <4eb348>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2952	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404b60 <@plt_start@+0x740>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
SUB X8, X29, #52	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X6, <4ef35c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4eb360>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2976	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X5, 409368 <main.omp_outlined.63+0xc8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	scal (50.0%)
ADD X5, X5, #640	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STUR X8, [X29, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
SUB X4, X29, #96	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
MOVZ W2, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
MOVZ W3, #8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
LDR X6, [X6, #3896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 404a90 <@plt_start@+0x670>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #2	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.EQ 409abc <main.omp_outlined.63+0x81c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
CMP W0, #1	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.33	scal (25.0%)
B.NE 409ac4 <main.omp_outlined.63+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR W8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDUR W9, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ADRP X2, <4ef3a4>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X0, <4eb3a8>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X0, X0, #2976	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR W1, WZR, W20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADD W8, W9, W8	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR W8, [X19]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (25.0%)
LDR X2, [X2, #3896]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 4047f0 <@plt_start@+0x3d0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
B 409ac4 <main.omp_outlined.63+0x824>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X8, [X29, #104]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
MOVZ W20, #45279	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVK W20, #39176	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
STR X8, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
LDR X8, [X29, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
STR X8, [SP, #80]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
ADRP X8, 4ad3e0 <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi32EE18DTABMultiWalkerMemC2Ev+0x60>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
LDR Q0, [X8, #3616]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 404900 <@plt_start@+0x4e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X8, 4ad3ec <_ZN11qmcplusplus27SoaDistanceTableABOMPTargetIdLj3ELi32EE18DTABMultiWalkerMemC2Ev+0x6c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
STUR Q0, [X29, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
LDR Q0, [X8, #3632]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 404900 <@plt_start@+0x4e0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR V1.16B, V0.16B, V0.16B	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	vect (100.0%)
LDUR Q0, [X29, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
BL 4046b0 <@plt_start@+0x290>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4047a0 <@plt_start@+0x380>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADD X8, X0, #52	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X9, XZR, #6177	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR W22, WZR, #1887	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W25, #1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
FMOV D8, #1.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W24, #4984	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
MOVZ W23, #5000	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
DUP V0.2D, X9	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
UDIV X8, X8, X0	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	5-20	5-20	N/A
STUR Q0, [X29, #352]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	vect (100.0%)
STR X8, [SP, #72]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
DUP V2.2D, X22	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
DUP V0.2D, X25	1	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	3	1	scal (50.0%)
STP Q0, Q2, [SP, #144]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	1	vect (100.0%)
B 409458 <main.omp_outlined.63+0x1b8>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDUR W8, [X29, #460]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDADD W8, W8, [X19]																					N/A
LDP D9, D8, [SP, #320]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	vect (100.0%)
LDR D10, [SP, #304]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #416]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #400]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #384]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #368]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #352]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #336]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #432	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 4046d0 <@plt_start@+0x2b0>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
MOVZ W0, #16	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404670 <@plt_start@+0x250>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X19, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ADRP X1, <4aeafc>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADD X1, X1, #3407	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404550 <@plt_start@+0x130>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ADRP X1, <4efb08>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ADRP X2, <4efb0c>	1	0	0	0.25	0.25	0	0	0.25	0.25	0	0	0	0	0	0	0	0	0	1	0.25	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
LDR X1, [X1, #4008]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
LDR X2, [X2, #3952]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	N/A
BL 404860 <@plt_start@+0x440>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 404a30 <@plt_start@+0x610>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
ORR X0, XZR, X20	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
BL 409c40 <__clang_call_terminate>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼main.omp_outlined.63–	0.01	0.01
▼Loop 28 - miniqmc.cpp:412-475 - exec–	0.01	0.02
▼Loop 27 - miniqmc.cpp:412-475 - exec–	0.00	0.00
▼Loop 29 - StdRandom.h:102-103 - exec–	0.00	0.00
▼Loop 30 - random.tcc:404-3368 - exec–	0.00	0.00
○Loop 32 - random.tcc:414-417 - exec	0.00	0.00
○Loop 31 - random.tcc:406-409 - exec	0.00	0.00
○Loop 33 - new_allocator.h:134-172 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code