OV - exec - Function miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::recompute(qmcplusplus::ParticleSet&)

	Function: miniqmcreference::TwoBodyJastrowRef<qmcplusplus::BsplineFunctor<double> >::recompute(qmcpl ...	Module: exec	Source: TwoBodyJastrowRef.h:268-402 [...]	Coverage (incl. loops): 0.09% \| (excl. loops): 0.00%

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_numeric.h: 140 - 141

--------------------------------------------------------------------------------

140:       for (; __first != __last; ++__first)

141: 	__init = _GLIBCXX_MOVE_IF_20(__init) + *__first;

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/shared_ptr_base.h: 1667 - 1667

--------------------------------------------------------------------------------

1667:       { return _M_ptr; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h: 952 - 1146

--------------------------------------------------------------------------------

952: 	*__first = __tmp;

[...]

1146:       if (__n <= 0)

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_iterator.h: 1068 - 1068

--------------------------------------------------------------------------------

1068:       : _M_current(__i) { }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h: 223 - 249

--------------------------------------------------------------------------------

223:     return X[i];

[...]

229:     return X[i];

[...]

249:   inline const_pointer data() const { return X; }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h: 268 - 402

--------------------------------------------------------------------------------

268:   const int igt = P.GroupID[iat] * NumGroups;

269:   for (int jg = 0; jg < NumGroups; ++jg)

270:   {

271:     const FuncType& f2(*F[igt + jg]);

272:     int iStart = P.first(jg);

273:     int iEnd   = std::min(jelmax, P.last(jg));

274:     f2.evaluateVGL(iat, iStart, iEnd, dist, u, du, d2u, DistCompressed.data(), DistIndice.data());

[...]

359: {

360:   const auto& d_table = P.getDistTableAA(myTableID);

361:   for (int ig = 0; ig < NumGroups; ++ig)

362:   {

363:     const int igt = ig * NumGroups;

364:     for (int iat = P.first(ig), last = P.last(ig); iat < last; ++iat)

365:     {

366:       computeU3(P, iat, d_table.getDistRow(iat).data(), cur_u.data(), cur_du.data(), cur_d2u.data(), true);

367:       Uat[iat] = std::accumulate(cur_u.begin(), cur_u.begin() + iat, valT());

[...]

375:       for (int jat = 0; jat < iat; ++jat)

376:         lap += d2u[jat] + lapfac * du[jat];

377:       for (int idim = 0; idim < OHMMS_DIM; ++idim)

378:       {

379:         const valT* restrict dX = displ.data(idim);

380:         valT s                  = valT();

381:         for (int jat = 0; jat < iat; ++jat)

382:           s += du[jat] * dX[jat];

383:         grad[idim] = s;

384:       }

385:       dUat(iat)  = grad;

386:       d2Uat[iat] = -lap;

387:       // add the contribution from the upper triangle

388:       for (int jat = 0; jat < iat; jat++)

389:       {

390:         Uat[jat] += u[jat];

391:         d2Uat[jat] -= d2u[jat] + lapfac * du[jat];

[...]

397:         for (int jat = 0; jat < iat; jat++)

398:           save_g[jat] -= du[jat] * dX[jat];

399:       }

400:     }

401:   }

402: }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h: 313 - 313

--------------------------------------------------------------------------------

313:   inline int first(int igroup) const { return (*group_offsets_)[igroup]; }

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h: 1131 - 1263

--------------------------------------------------------------------------------

1131: 	return *(this->_M_impl._M_start + __n);

[...]

1150: 	return *(this->_M_impl._M_start + __n);

[...]

1263:       { return _M_data_ptr(this->_M_impl._M_start); }

/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h: 244 - 273

--------------------------------------------------------------------------------

244:         *(_base + M * i) = rhs[i];

[...]

263:   inline Accessor operator()(size_t i) { return Accessor(myData + i, nGhosts); }

[...]

271:   inline T* restrict data(size_t i) { return myData + i * nGhosts; }

272:   ///return the const pointer of the i-th components

273:   inline const T* restrict data(size_t i) const { return myData + i * nGhosts; }

0x419aa0 SUB	SP, SP, #208

0x419aa4 STR	D8, [SP, #96]

0x419aa8 STP	X29, X30, [SP, #112]

0x419aac STP	X28, X27, [SP, #128]

0x419ab0 STP	X26, X25, [SP, #144]

0x419ab4 STP	X24, X23, [SP, #160]

0x419ab8 STP	X22, X21, [SP, #176]

0x419abc STP	X20, X19, [SP, #192]

0x419ac0 ADD	X29, SP, #112

0x419ac4 ORR	X19, XZR, X1

0x419ac8 LDR	W1, [X0, #584]

0x419acc ORR	X20, XZR, X0

0x419ad0 ORR	X0, XZR, X19

0x419ad4 BL	4471f0

0x419ad8 LDR	X28, [X20, #160]

0x419adc CBZ	X28, 41a690

0x419ae0 FMOV	D8, #-2.0000000

0x419ae4 MOVZ	W6, #40

0x419ae8 ORR	X30, XZR, X19

0x419aec ORR	X21, XZR, X0

0x419af0 ORR	X9, XZR, XZR

0x419af4 STUR	X28, [X29, #464]

0x419af8 STR	X0, [SP, #32]

0x419afc STUR	X19, [X29, #504]

0x419b00 B	419b1c

      (322) 0x419b04 LDUR	X8, [X29, #464]

      (322) 0x419b08 LDR	X9, [SP, #16]

      (322) 0x419b0c STUR	X8, [X29, #464]

      (322) 0x419b10 ADD	X9, X9, #1

      (322) 0x419b14 CMP	X8, X9

      (322) 0x419b18 B.LS	41a690

      (322) 0x419b1c LDR	X8, [X30, #616]

      (322) 0x419b20 STR	X9, [SP, #16]

      (322) 0x419b24 LDR	X8, [X8, #24]

      (322) 0x419b28 ADD	X8, X8, X9,LSL #2

      (322) 0x419b2c LDP	W27, W8, [X8]

      (322) 0x419b30 STR	W8, [SP, #52]

      (322) 0x419b34 CMP	W27, W8

      (322) 0x419b38 B.GE	419b04

    (324) 0x419b3c LDR	X22, [X20, #320]

    (324) 0x419b40 LDR	X24, [X20, #344]

    (324) 0x419b44 LDR	X25, [X20, #368]

    (324) 0x419b48 MOVN	X8, #57344

    (324) 0x419b4c SBFM	X23, X27, #0, #31

    (324) 0x419b50 ORR	X19, XZR, XZR

    (324) 0x419b54 ADD	X9, X8, W27,SXTW

    (324) 0x419b58 STUR	WZR, [X29, #492]

    (324) 0x419b5c ORR	W8, WZR, W27

    (324) 0x419b60 STR	X23, [SP, #24]

    (324) 0x419b64 STR	X27, [SP, #40]

    (324) 0x419b68 STP	X9, X8, [X29, #984]

    (324) 0x419b6c B	419bb4

0x419b70 HINT	#0

0x419b74 HINT	#0

0x419b78 HINT	#0

0x419b7c HINT	#0

    (324) 0x419b80 LDUR	W9, [X29, #492]

    (324) 0x419b84 ADD	W8, W8, #1

    (324) 0x419b88 ADD	X23, X23, #1

    (324) 0x419b8c ADD	X19, X19, #1

    (324) 0x419b90 ADD	W9, W9, #1

    (324) 0x419b94 STUR	W9, [X29, #492]

    (324) 0x419b98 LDUR	X9, [X29, #472]

    (324) 0x419b9c ADD	X9, X9, #1

    (324) 0x419ba0 STP	X9, X8, [X29, #984]

    (324) 0x419ba4 LDR	W9, [SP, #52]

    (324) 0x419ba8 ORR	X8, XZR, X28

    (324) 0x419bac CMP	W9, W23

    (324) 0x419bb0 B.EQ	419b08

    (324) 0x419bb4 LDR	X8, [X21, #72]

    (324) 0x419bb8 UBFM	X26, X23, #61, #60

    (324) 0x419bbc STR	X19, [SP, #56]

    (324) 0x419bc0 MADD	X8, X23, X6, X8

    (324) 0x419bc4 LDR	X27, [X8, #24]

    (324) 0x419bc8 CMP	X23, #1

    (324) 0x419bcc B.LT	419c08

    (324) 0x419bd0 ORR	X0, XZR, X22

    (324) 0x419bd4 ORR	W1, WZR, WZR

    (324) 0x419bd8 ORR	X2, XZR, X26

    (324) 0x419bdc BL	404920

    (324) 0x419be0 ORR	X0, XZR, X24

    (324) 0x419be4 ORR	W1, WZR, WZR

    (324) 0x419be8 ORR	X2, XZR, X26

    (324) 0x419bec BL	404920

    (324) 0x419bf0 ORR	X0, XZR, X25

    (324) 0x419bf4 ORR	W1, WZR, WZR

    (324) 0x419bf8 ORR	X2, XZR, X26

    (324) 0x419bfc BL	404920

    (324) 0x419c00 LDUR	X30, [X29, #504]

    (324) 0x419c04 MOVZ	W6, #40

    (324) 0x419c08 LDUR	X9, [X29, #464]

    (324) 0x419c0c CBZ	X9, 419d40

    (324) 0x419c10 LDR	X8, [X30, #24]

    (324) 0x419c14 ORR	X19, XZR, X26

    (324) 0x419c18 ORR	X21, XZR, XZR

    (324) 0x419c1c LDR	W8, [X8, X23,LSL #2]

    (324) 0x419c20 MADD	W8, W8, W9, WZR

    (324) 0x419c24 SBFM	X26, X8, #61, #31

      (329) 0x419c28 LDR	X8, [X20, #512]

      (329) 0x419c2c LDR	X9, [X20, #488]

      (329) 0x419c30 ORR	W1, WZR, W23

      (329) 0x419c34 ORR	X4, XZR, X27

      (329) 0x419c38 ORR	X5, XZR, X22

      (329) 0x419c3c ORR	X6, XZR, X24

      (329) 0x419c40 ORR	X7, XZR, X25

      (329) 0x419c44 ADD	X8, X8, X26

      (329) 0x419c48 LDR	X0, [X8, X21,LSL #3]

      (329) 0x419c4c LDR	X8, [X30, #616]

      (329) 0x419c50 LDR	X8, [X8, #24]

      (329) 0x419c54 ADD	X8, X8, X21,LSL #2

      (329) 0x419c58 LDP	W2, W8, [X8]

      (329) 0x419c5c CMP	W8, W23

      (329) 0x419c60 CSEL	W3, W8, W23, #11

      (329) 0x419c64 LDR	X8, [X20, #464]

      (329) 0x419c68 STP	X8, X9, [SP]

      (329) 0x419c6c BL	416a40

      (329) 0x419c70 LDUR	X30, [X29, #504]

      (329) 0x419c74 LDR	X28, [X20, #160]

      (329) 0x419c78 ADD	X21, X21, #1

      (329) 0x419c7c CMP	X28, X21

      (329) 0x419c80 B.HI	419c28

    (324) 0x419c84 LDR	X22, [X20, #320]

    (324) 0x419c88 LDP	X21, X27, [SP, #32]

    (324) 0x419c8c MOVZ	W6, #40

    (324) 0x419c90 ORR	X26, XZR, X19

    (324) 0x419c94 STUR	X28, [X29, #464]

    (324) 0x419c98 CBZ	X23, 419d4c

    (324) 0x419c9c LDR	X19, [SP, #56]

    (324) 0x419ca0 LDR	X8, [SP, #24]

    (324) 0x419ca4 MOVI	D0, #0

    (324) 0x419ca8 ADD	X8, X19, X8

    (324) 0x419cac SUB	X8, X8, #1

    (324) 0x419cb0 AND	X9, X8, #7936

    (324) 0x419cb4 ORR	X8, XZR, X22

    (324) 0x419cb8 CMP	X9, #3

    (324) 0x419cbc B.CC	419d10

    (324) 0x419cc0 LDUR	X8, [X29, #472]

    (324) 0x419cc4 ADD	X9, X9, #1

    (324) 0x419cc8 ADD	X12, X22, #16

    (324) 0x419ccc MOVI	V0.2D, #0

    (324) 0x419cd0 MOVI	V1.2D, #0

    (324) 0x419cd4 AND	X10, X9, #7934

    (324) 0x419cd8 AND	X8, X8, #7936

    (324) 0x419cdc ADD	X8, X8, #1

    (324) 0x419ce0 AND	X11, X8, #7934

    (324) 0x419ce4 ADD	X8, X22, X10,LSL #3

      (328) 0x419ce8 LDP	Q2, Q3, [X12, #2032]

      (328) 0x419cec ADD	X12, X12, #32

      (328) 0x419cf0 SUBS	X11, X11, #4

      (328) 0x419cf4 FADD	V1.2D, V3.2D, V1.2D

      (328) 0x419cf8 FADD	V0.2D, V2.2D, V0.2D

      (328) 0x419cfc B.NE	419ce8

    (324) 0x419d00 FADD	V0.2D, V1.2D, V0.2D

    (324) 0x419d04 FADDP	D0, V0.2D

    (324) 0x419d08 CMP	X9, X10

    (324) 0x419d0c B.EQ	419d54

    (324) 0x419d10 ADD	X9, X22, X23,LSL #3

    (324) 0x419d14 HINT	#0

    (324) 0x419d18 HINT	#0

    (324) 0x419d1c HINT	#0

      (323) 0x419d20 LDR	D1, [X8], #8

      (323) 0x419d24 FADD	D0, D1, D0

      (323) 0x419d28 CMP	X8, X9

      (323) 0x419d2c B.NE	419d20

    (324) 0x419d30 B	419d54

0x419d34 HINT	#0

0x419d38 HINT	#0

0x419d3c HINT	#0

    (324) 0x419d40 LDR	X27, [SP, #40]

    (324) 0x419d44 STUR	XZR, [X29, #464]

    (324) 0x419d48 CBNZ	X23, 419c9c

    (324) 0x419d4c LDR	X19, [SP, #56]

    (324) 0x419d50 MOVI	D0, #0

    (324) 0x419d54 LDR	X11, [X21, #96]

    (324) 0x419d58 LDUR	X8, [X29, #480]

    (324) 0x419d5c LDUR	W9, [X29, #492]

    (324) 0x419d60 MADD	X12, X23, X6, X11

    (324) 0x419d64 LDR	X16, [X20, #216]

    (324) 0x419d68 LDR	X24, [X20, #344]

    (324) 0x419d6c LDR	X25, [X20, #368]

    (324) 0x419d70 ORR	W8, WZR, W8

    (324) 0x419d74 AND	X10, X8, #6014

    (324) 0x419d78 ADD	W9, W27, W9

    (324) 0x419d7c STR	D0, [X16, X23,LSL #3]

    (324) 0x419d80 CMP	X23, #0

    (324) 0x419d84 B.LE	419da0

  (327) 0x419d88 CMP	W9, #3

  (327) 0x419d8c B.HI	419dc0

  (327) 0x419d90 MOVI	D0, #0

  (327) 0x419d94 ORR	X11, XZR, XZR

  (327) 0x419d98 B	419e20

0x419d9c HINT	#0

    (324) 0x419da0 LDR	X11, [X12, #24]

    (324) 0x419da4 LDR	X12, [X12, #8]

    (324) 0x419da8 MOVI	D0, #0

    (324) 0x419dac B	419e6c

0x419db0 HINT	#0

0x419db4 HINT	#0

0x419db8 HINT	#0

0x419dbc HINT	#0

(325) 0x419dc0 AND	X11, X9, #6014

(325) 0x419dc4 ADD	X13, X25, #16

(325) 0x419dc8 ADD	X14, X24, #16

(325) 0x419dcc MOVI	V0.2D, #0

(325) 0x419dd0 ORR	X15, XZR, X10

(325) 0x419dd4 MOVI	V1.2D, #0

(325) 0x419dd8 HINT	#0

(325) 0x419ddc HINT	#0

  (321) 0x419de0 LDP	Q2, Q3, [X13, #2032]

  (321) 0x419de4 LDP	Q4, Q5, [X14, #2032]

  (321) 0x419de8 ADD	X13, X13, #32

  (321) 0x419dec ADD	X14, X14, #32

  (321) 0x419df0 SUBS	X15, X15, #4

  (321) 0x419df4 FADD	V5.2D, V5.2D, V5.2D

  (321) 0x419df8 FADD	V1.2D, V3.2D, V1.2D

  (321) 0x419dfc FADD	V4.2D, V4.2D, V4.2D

  (321) 0x419e00 FADD	V0.2D, V2.2D, V0.2D

  (321) 0x419e04 FADD	V1.2D, V1.2D, V5.2D

  (321) 0x419e08 FADD	V0.2D, V0.2D, V4.2D

  (321) 0x419e0c B.NE	419de0

(325) 0x419e10 FADD	V0.2D, V1.2D, V0.2D

(325) 0x419e14 FADDP	D0, V0.2D

(325) 0x419e18 CMP	X11, X9

(325) 0x419e1c B.EQ	419e48

  (327) 0x419e20 ADD	X13, X24, X11,LSL #3

  (327) 0x419e24 ADD	X14, X25, X11,LSL #3

  (327) 0x419e28 SUB	X11, X8, X11

    (326) 0x419e2c LDR	D1, [X14], #8

    (326) 0x419e30 LDR	D2, [X13], #8

    (326) 0x419e34 SUBS	X11, X11, #1

    (326) 0x419e38 FADD	D2, D2, D2

    (326) 0x419e3c FADD	D0, D1, D0

    (326) 0x419e40 FADD	D0, D0, D2

    (326) 0x419e44 B.NE	419e2c

  (327) 0x419e48 LDR	X11, [X12, #24]

  (327) 0x419e4c LDR	X12, [X12, #8]

  (327) 0x419e50 CMP	X23, #1

  (327) 0x419e54 B.LT	419e6c

  (327) 0x419e58 CMP	W9, #4

  (327) 0x419e5c B.CS	419e7c

  (327) 0x419e60 ORR	X13, XZR, XZR

  (327) 0x419e64 MOVI	D1, #0

  (327) 0x419e68 B	419ed0

    (324) 0x419e6c MOVI	D1, #0

    (324) 0x419e70 MOVI	D2, #0

    (324) 0x419e74 MOVI	D3, #0

    (324) 0x419e78 B	41a018

  (327) 0x419e7c AND	X13, X9, #6014

  (327) 0x419e80 ADD	X14, X24, #16

  (327) 0x419e84 ADD	X15, X11, #16

  (327) 0x419e88 MOVI	V1.2D, #0

  (327) 0x419e8c ORR	X17, XZR, X10

  (327) 0x419e90 MOVI	V2.2D, #0

  (327) 0x419e94 HINT	#0

  (327) 0x419e98 HINT	#0

  (327) 0x419e9c HINT	#0

    (341) 0x419ea0 LDP	Q3, Q4, [X14, #2032]

    (341) 0x419ea4 LDP	Q5, Q6, [X15, #2032]

    (341) 0x419ea8 ADD	X14, X14, #32

    (341) 0x419eac ADD	X15, X15, #32

    (341) 0x419eb0 SUBS	X17, X17, #4

    (341) 0x419eb4 FMLA	V2.2D, V6.2D, V4.2D

    (341) 0x419eb8 FMLA	V1.2D, V5.2D, V3.2D

    (341) 0x419ebc B.NE	419ea0

  (327) 0x419ec0 FADD	V1.2D, V2.2D, V1.2D

  (327) 0x419ec4 FADDP	D1, V1.2D

  (327) 0x419ec8 CMP	X13, X9

  (327) 0x419ecc B.EQ	419ef4

  (327) 0x419ed0 ADD	X14, X24, X13,LSL #3

  (327) 0x419ed4 ADD	X15, X11, X13,LSL #3

  (327) 0x419ed8 SUB	X13, X8, X13

  (327) 0x419edc HINT	#0

    (346) 0x419ee0 LDR	D2, [X14], #8

    (346) 0x419ee4 LDR	D3, [X15], #8

    (346) 0x419ee8 SUBS	X13, X13, #1

    (346) 0x419eec FMADD	D1, D3, D2, D1

    (346) 0x419ef0 B.NE	419ee0

  (327) 0x419ef4 CMP	W9, #4

  (327) 0x419ef8 B.CS	419f08

  (327) 0x419efc ORR	X13, XZR, XZR

  (327) 0x419f00 MOVI	D2, #0

  (327) 0x419f04 B	419f54

  (327) 0x419f08 ADD	X15, X11, X12,LSL #3

  (327) 0x419f0c AND	X13, X9, #6014

  (327) 0x419f10 ADD	X14, X24, #16

  (327) 0x419f14 MOVI	V2.2D, #0

  (327) 0x419f18 ORR	X17, XZR, X10

  (327) 0x419f1c MOVI	V3.2D, #0

  (327) 0x419f20 ADD	X15, X15, #16

    (342) 0x419f24 LDP	Q4, Q5, [X14, #2032]

    (342) 0x419f28 LDP	Q6, Q7, [X15, #2032]

    (342) 0x419f2c ADD	X14, X14, #32

    (342) 0x419f30 ADD	X15, X15, #32

    (342) 0x419f34 SUBS	X17, X17, #4

    (342) 0x419f38 FMLA	V3.2D, V7.2D, V5.2D

    (342) 0x419f3c FMLA	V2.2D, V6.2D, V4.2D

    (342) 0x419f40 B.NE	419f24

  (327) 0x419f44 FADD	V2.2D, V3.2D, V2.2D

  (327) 0x419f48 FADDP	D2, V2.2D

  (327) 0x419f4c CMP	X13, X9

  (327) 0x419f50 B.EQ	419f7c

  (327) 0x419f54 UBFM	X15, X13, #61, #60

  (327) 0x419f58 SUB	X14, X8, X13

  (327) 0x419f5c ADD	X13, X24, X13,LSL #3

  (327) 0x419f60 ADD	X15, X15, X12,LSL #3

  (327) 0x419f64 ADD	X15, X11, X15

    (345) 0x419f68 LDR	D3, [X13], #8

    (345) 0x419f6c LDR	D4, [X15], #8

    (345) 0x419f70 SUBS	X14, X14, #1

    (345) 0x419f74 FMADD	D2, D4, D3, D2

    (345) 0x419f78 B.NE	419f68

  (327) 0x419f7c UBFM	X13, X12, #60, #59

  (327) 0x419f80 CMP	W9, #4

  (327) 0x419f84 B.CS	419f94

  (327) 0x419f88 ORR	X14, XZR, XZR

  (327) 0x419f8c MOVI	D3, #0

  (327) 0x419f90 B	419ff0

  (327) 0x419f94 ADD	X17, X11, X13

  (327) 0x419f98 AND	X14, X9, #6014

  (327) 0x419f9c ADD	X15, X24, #16

  (327) 0x419fa0 MOVI	V3.2D, #0

  (327) 0x419fa4 ORR	X18, XZR, X10

  (327) 0x419fa8 MOVI	V4.2D, #0

  (327) 0x419fac ADD	X17, X17, #16

  (327) 0x419fb0 HINT	#0

  (327) 0x419fb4 HINT	#0

  (327) 0x419fb8 HINT	#0

  (327) 0x419fbc HINT	#0

    (343) 0x419fc0 LDP	Q5, Q6, [X15, #2032]

    (343) 0x419fc4 LDP	Q7, Q16, [X17, #2032]

    (343) 0x419fc8 ADD	X15, X15, #32

    (343) 0x419fcc ADD	X17, X17, #32

    (343) 0x419fd0 SUBS	X18, X18, #4

    (343) 0x419fd4 FMLA	V4.2D, V16.2D, V6.2D

    (343) 0x419fd8 FMLA	V3.2D, V7.2D, V5.2D

    (343) 0x419fdc B.NE	419fc0

  (327) 0x419fe0 FADD	V3.2D, V4.2D, V3.2D

  (327) 0x419fe4 FADDP	D3, V3.2D

  (327) 0x419fe8 CMP	X14, X9

  (327) 0x419fec B.EQ	41a018

  (327) 0x419ff0 SUB	X15, X8, X14

  (327) 0x419ff4 ADD	X13, X13, X14,LSL #3

  (327) 0x419ff8 ADD	X14, X24, X14,LSL #3

  (327) 0x419ffc HINT	#0

    (344) 0x41a000 LDR	D4, [X14], #8

    (344) 0x41a004 LDR	D5, [X11, X13]

    (344) 0x41a008 SUBS	X15, X15, #1

    (344) 0x41a00c ADD	X13, X13, #8

    (344) 0x41a010 FMADD	D3, D5, D4, D3

    (344) 0x41a014 B.NE	41a000

    (324) 0x41a018 LDR	X13, [X20, #256]

    (324) 0x41a01c LDR	X17, [X20, #240]

    (324) 0x41a020 LDR	X0, [X20, #296]

    (324) 0x41a024 FNEG	D0, D0

    (324) 0x41a028 ADD	X15, X13, X23,LSL #3

    (324) 0x41a02c UBFM	X14, X17, #60, #59

    (324) 0x41a030 STR	D1, [X15]

    (324) 0x41a034 STR	D2, [X15, X17,LSL #3]

    (324) 0x41a038 STR	D3, [X15, X14]

    (324) 0x41a03c STR	D0, [X0, X26]

    (324) 0x41a040 CMP	X23, #1

    (324) 0x41a044 B.LT	419b80

    (324) 0x41a048 ADD	W15, W27, W19

    (324) 0x41a04c UBFM	X18, X9, #61, #31

    (324) 0x41a050 CMP	W9, #7

    (324) 0x41a054 B.HI	41a124

    (324) 0x41a058 ORR	X1, XZR, XZR

    (324) 0x41a05c ORR	X5, XZR, X1

    (324) 0x41a060 TBZ	W15, #0, 41a090

    (324) 0x41a064 LDR	D0, [X22, X1,LSL #3]

    (324) 0x41a068 LDR	D1, [X16, X1,LSL #3]

    (324) 0x41a06c ORR	X5, X1, #4096

    (324) 0x41a070 FADD	D0, D1, D0

    (324) 0x41a074 STR	D0, [X16, X1,LSL #3]

    (324) 0x41a078 LDR	D0, [X25, X1,LSL #3]

    (324) 0x41a07c LDR	D1, [X24, X1,LSL #3]

    (324) 0x41a080 LDR	D2, [X0, X1,LSL #3]

    (324) 0x41a084 FNMSUB	D0, D1, D8, D0

    (324) 0x41a088 FADD	D0, D0, D2

    (324) 0x41a08c STR	D0, [X0, X1,LSL #3]

    (324) 0x41a090 SUB	X2, X15, #1

    (324) 0x41a094 CMP	X1, X2

    (324) 0x41a098 B.EQ	41a240

    (324) 0x41a09c ADD	X2, X24, X5,LSL #3

    (324) 0x41a0a0 ADD	X3, X25, X5,LSL #3

    (324) 0x41a0a4 ADD	X4, X22, X5,LSL #3

    (324) 0x41a0a8 ADD	X16, X16, X5,LSL #3

    (324) 0x41a0ac ADD	X0, X0, X5,LSL #3

    (324) 0x41a0b0 SUB	X1, X8, X5

    (324) 0x41a0b4 ADD	X2, X2, #8

    (324) 0x41a0b8 ADD	X3, X3, #8

    (324) 0x41a0bc ADD	X4, X4, #8

    (324) 0x41a0c0 ADD	X16, X16, #8

    (324) 0x41a0c4 ADD	X0, X0, #8

      (339) 0x41a0c8 LDUR	D0, [X4, #504]

      (339) 0x41a0cc LDUR	D1, [X16, #504]

      (339) 0x41a0d0 SUBS	X1, X1, #2

      (339) 0x41a0d4 FADD	D0, D1, D0

      (339) 0x41a0d8 STUR	D0, [X16, #504]

      (339) 0x41a0dc LDUR	D0, [X3, #504]

      (339) 0x41a0e0 LDUR	D1, [X2, #504]

      (339) 0x41a0e4 LDUR	D2, [X0, #504]

      (339) 0x41a0e8 FNMSUB	D0, D1, D8, D0

      (339) 0x41a0ec FADD	D0, D0, D2

      (339) 0x41a0f0 STUR	D0, [X0, #504]

      (339) 0x41a0f4 LDR	D0, [X4], #16

      (339) 0x41a0f8 LDR	D1, [X16]

      (339) 0x41a0fc FADD	D0, D1, D0

      (339) 0x41a100 STR	D0, [X16], #16

      (339) 0x41a104 LDR	D0, [X3], #16

      (339) 0x41a108 LDR	D1, [X2], #16

      (339) 0x41a10c LDR	D2, [X0]

      (339) 0x41a110 FNMSUB	D0, D1, D8, D0

      (339) 0x41a114 FADD	D0, D0, D2

      (339) 0x41a118 STR	D0, [X0], #16

      (339) 0x41a11c B.NE	41a0c8

    (324) 0x41a120 B	41a240

    (324) 0x41a124 ADD	X5, X22, X18

    (324) 0x41a128 ADD	X21, X16, X18

    (324) 0x41a12c ADD	X6, X25, X18

    (324) 0x41a130 ADD	X7, X24, X18

    (324) 0x41a134 ADD	X26, X0, X18

    (324) 0x41a138 ORR	X1, XZR, XZR

    (324) 0x41a13c CMP	X16, X5

    (324) 0x41a140 CCMP	X22, X21, #2, #3

    (324) 0x41a144 CSINC	W2, WZR, WZR, #2

    (324) 0x41a148 CMP	X16, X6

    (324) 0x41a14c CCMP	X25, X21, #2, #3

    (324) 0x41a150 CSINC	W3, WZR, WZR, #2

    (324) 0x41a154 CMP	X16, X7

    (324) 0x41a158 CCMP	X24, X21, #2, #3

    (324) 0x41a15c CSINC	W4, WZR, WZR, #2

    (324) 0x41a160 CMP	X0, X5

    (324) 0x41a164 CCMP	X22, X26, #2, #3

    (324) 0x41a168 CSINC	W5, WZR, WZR, #2

    (324) 0x41a16c CMP	X0, X6

    (324) 0x41a170 CCMP	X25, X26, #2, #3

    (324) 0x41a174 CSINC	W6, WZR, WZR, #2

    (324) 0x41a178 CMP	X0, X7

    (324) 0x41a17c CCMP	X24, X26, #2, #3

    (324) 0x41a180 CSINC	W7, WZR, WZR, #2

    (324) 0x41a184 CMP	X0, X21

    (324) 0x41a188 CCMP	X16, X26, #2, #3

    (324) 0x41a18c B.CC	41a684

    (324) 0x41a190 LDR	X21, [SP, #32]

    (324) 0x41a194 TBNZ	W2, #0, 41a688

    (324) 0x41a198 TBNZ	W3, #0, 41a688

    (324) 0x41a19c TBNZ	W4, #0, 41a688

    (324) 0x41a1a0 TBNZ	W5, #0, 41a688

    (324) 0x41a1a4 TBNZ	W6, #0, 41a688

    (324) 0x41a1a8 MOVZ	W6, #40

    (324) 0x41a1ac TBNZ	W7, #0, 41a05c

    (324) 0x41a1b0 AND	X1, X9, #6014

    (324) 0x41a1b4 ADD	X2, X22, #16

    (324) 0x41a1b8 ADD	X3, X0, #16

    (324) 0x41a1bc ADD	X4, X16, #16

    (324) 0x41a1c0 ADD	X5, X24, #16

    (324) 0x41a1c4 ADD	X6, X25, #16

    (324) 0x41a1c8 ORR	X7, XZR, X10

      (340) 0x41a1cc LDP	Q0, Q1, [X2, #2032]

      (340) 0x41a1d0 LDP	Q2, Q3, [X4, #2032]

      (340) 0x41a1d4 FMOV	V6.2D, #-2.0000000

      (340) 0x41a1d8 SUBS	X7, X7, #4

      (340) 0x41a1dc ADD	X2, X2, #32

      (340) 0x41a1e0 FADD	V1.2D, V3.2D, V1.2D

      (340) 0x41a1e4 LDP	Q4, Q5, [X3, #2032]

      (340) 0x41a1e8 FADD	V0.2D, V2.2D, V0.2D

      (340) 0x41a1ec LDP	Q2, Q3, [X5, #2032]

      (340) 0x41a1f0 ADD	X5, X5, #32

      (340) 0x41a1f4 STP	Q0, Q1, [X4, #2032]

      (340) 0x41a1f8 LDP	Q0, Q1, [X6, #2032]

      (340) 0x41a1fc ADD	X4, X4, #32

      (340) 0x41a200 ADD	X6, X6, #32

      (340) 0x41a204 FNEG	V1.2D, V1.2D

      (340) 0x41a208 FNEG	V0.2D, V0.2D

      (340) 0x41a20c FMLA	V1.2D, V3.2D, V6.2D

      (340) 0x41a210 FMLA	V0.2D, V2.2D, V6.2D

      (340) 0x41a214 FADD	V1.2D, V1.2D, V5.2D

      (340) 0x41a218 FADD	V0.2D, V0.2D, V4.2D

      (340) 0x41a21c STP	Q0, Q1, [X3, #2032]

      (340) 0x41a220 ADD	X3, X3, #32

      (340) 0x41a224 B.NE	41a1cc

    (324) 0x41a228 MOVZ	W6, #40

    (324) 0x41a22c CMP	X1, X9

    (324) 0x41a230 B.NE	41a05c

    (324) 0x41a234 HINT	#0

    (324) 0x41a238 HINT	#0

    (324) 0x41a23c HINT	#0

    (324) 0x41a240 CMP	X23, #1

    (324) 0x41a244 B.LT	419b80

    (324) 0x41a248 LDUR	X16, [X29, #480]

    (324) 0x41a24c AND	X16, X16, #4160

    (324) 0x41a250 CMP	W9, #4

    (324) 0x41a254 B.CS	41a328

    (324) 0x41a258 ORR	X0, XZR, XZR

    (324) 0x41a25c ORR	X3, XZR, X0

    (324) 0x41a260 ANDS	XZR, X15, #4160

    (324) 0x41a264 B.EQ	41a2a0

    (324) 0x41a268 ORR	X1, XZR, X16

    (324) 0x41a26c ORR	X3, XZR, X0

    (324) 0x41a270 HINT	#0

    (324) 0x41a274 HINT	#0

    (324) 0x41a278 HINT	#0

    (324) 0x41a27c HINT	#0

      (337) 0x41a280 LDR	D0, [X24, X3,LSL #3]

      (337) 0x41a284 LDR	D1, [X11, X3,LSL #3]

      (337) 0x41a288 LDR	D2, [X13, X3,LSL #3]

      (337) 0x41a28c SUBS	X1, X1, #1

      (337) 0x41a290 FMSUB	D0, D1, D0, D2

      (337) 0x41a294 STR	D0, [X13, X3,LSL #3]

      (337) 0x41a298 ADD	X3, X3, #1

      (337) 0x41a29c B.NE	41a280

    (324) 0x41a2a0 SUB	X0, X0, X15

    (324) 0x41a2a4 CMN	X0, #4

    (324) 0x41a2a8 B.HI	41a3a0

    (324) 0x41a2ac SUB	X0, X8, X3

    (324) 0x41a2b0 ADD	X1, X13, X3,LSL #3

    (324) 0x41a2b4 ADD	X2, X11, X3,LSL #3

    (324) 0x41a2b8 ADD	X3, X24, X3,LSL #3

    (324) 0x41a2bc ADD	X1, X1, #16

    (324) 0x41a2c0 ADD	X2, X2, #16

    (324) 0x41a2c4 ADD	X3, X3, #16

      (336) 0x41a2c8 LDUR	D0, [X3, #496]

      (336) 0x41a2cc LDUR	D1, [X2, #496]

      (336) 0x41a2d0 LDP	D2, D3, [X1, #1008]

      (336) 0x41a2d4 SUBS	X0, X0, #4

      (336) 0x41a2d8 FMSUB	D0, D1, D0, D2

      (336) 0x41a2dc STUR	D0, [X1, #496]

      (336) 0x41a2e0 LDUR	D0, [X3, #504]

      (336) 0x41a2e4 LDUR	D1, [X2, #504]

      (336) 0x41a2e8 FMSUB	D0, D1, D0, D3

      (336) 0x41a2ec LDP	D2, D3, [X1]

      (336) 0x41a2f0 STUR	D0, [X1, #504]

      (336) 0x41a2f4 LDR	D0, [X3]

      (336) 0x41a2f8 LDR	D1, [X2]

      (336) 0x41a2fc FMSUB	D0, D1, D0, D2

      (336) 0x41a300 STR	D0, [X1]

      (336) 0x41a304 LDR	D0, [X3, #8]

      (336) 0x41a308 LDR	D1, [X2, #8]

      (336) 0x41a30c ADD	X2, X2, #32

      (336) 0x41a310 ADD	X3, X3, #32

      (336) 0x41a314 FMSUB	D0, D1, D0, D3

      (336) 0x41a318 STR	D0, [X1, #8]

      (336) 0x41a31c ADD	X1, X1, #32

      (336) 0x41a320 B.NE	41a2c8

    (324) 0x41a324 B	41a3a0

    (324) 0x41a328 ADD	X1, X11, X18

    (324) 0x41a32c ADD	X2, X13, X18

    (324) 0x41a330 ADD	X3, X24, X18

    (324) 0x41a334 ORR	X0, XZR, XZR

    (324) 0x41a338 CMP	X13, X1

    (324) 0x41a33c CCMP	X11, X2, #2, #3

    (324) 0x41a340 CSINC	W1, WZR, WZR, #2

    (324) 0x41a344 CMP	X24, X2

    (324) 0x41a348 CCMP	X13, X3, #2, #3

    (324) 0x41a34c B.CC	41a25c

    (324) 0x41a350 TBNZ	W1, #0, 41a25c

    (324) 0x41a354 AND	X0, X9, #6014

    (324) 0x41a358 ADD	X1, X24, #16

    (324) 0x41a35c ADD	X2, X11, #16

    (324) 0x41a360 ADD	X3, X13, #16

    (324) 0x41a364 ORR	X4, XZR, X10

      (338) 0x41a368 LDP	Q0, Q1, [X1, #2032]

      (338) 0x41a36c LDP	Q2, Q3, [X2, #2032]

      (338) 0x41a370 ADD	X1, X1, #32

      (338) 0x41a374 ADD	X2, X2, #32

      (338) 0x41a378 SUBS	X4, X4, #4

      (338) 0x41a37c LDP	Q4, Q5, [X3, #2032]

      (338) 0x41a380 FMLS	V5.2D, V3.2D, V1.2D

      (338) 0x41a384 FMLS	V4.2D, V2.2D, V0.2D

      (338) 0x41a388 STP	Q4, Q5, [X3, #2032]

      (338) 0x41a38c ADD	X3, X3, #32

      (338) 0x41a390 B.NE	41a368

    (324) 0x41a394 CMP	X0, X9

    (324) 0x41a398 B.NE	41a25c

    (324) 0x41a39c HINT	#0

    (324) 0x41a3a0 ADD	X0, X13, X17,LSL #3

    (324) 0x41a3a4 ADD	X1, X11, X12,LSL #3

    (324) 0x41a3a8 CMP	W9, #4

    (324) 0x41a3ac B.CS	41a480

    (324) 0x41a3b0 ORR	X2, XZR, XZR

    (324) 0x41a3b4 ORR	X3, XZR, X2

    (324) 0x41a3b8 ANDS	XZR, X15, #4160

    (324) 0x41a3bc B.EQ	41a3e8

    (324) 0x41a3c0 ORR	X4, XZR, X16

    (324) 0x41a3c4 ORR	X3, XZR, X2

      (334) 0x41a3c8 LDR	D0, [X24, X3,LSL #3]

      (334) 0x41a3cc LDR	D1, [X1, X3,LSL #3]

      (334) 0x41a3d0 LDR	D2, [X0, X3,LSL #3]

      (334) 0x41a3d4 SUBS	X4, X4, #1

      (334) 0x41a3d8 FMSUB	D0, D1, D0, D2

      (334) 0x41a3dc STR	D0, [X0, X3,LSL #3]

      (334) 0x41a3e0 ADD	X3, X3, #1

      (334) 0x41a3e4 B.NE	41a3c8

    (324) 0x41a3e8 SUB	X0, X2, X15

    (324) 0x41a3ec CMN	X0, #4

    (324) 0x41a3f0 B.HI	41a520

    (324) 0x41a3f4 UBFM	X1, X3, #61, #60

    (324) 0x41a3f8 UBFM	X2, X12, #61, #60

    (324) 0x41a3fc SUB	X0, X8, X3

    (324) 0x41a400 ADD	X1, X1, X17,LSL #3

    (324) 0x41a404 ADD	X2, X2, X3,LSL #3

    (324) 0x41a408 ADD	X3, X24, X3,LSL #3

    (324) 0x41a40c ADD	X1, X13, X1

    (324) 0x41a410 ADD	X2, X11, X2

    (324) 0x41a414 ADD	X3, X3, #16

    (324) 0x41a418 ADD	X1, X1, #16

    (324) 0x41a41c ADD	X2, X2, #16

      (333) 0x41a420 LDUR	D0, [X3, #496]

      (333) 0x41a424 LDUR	D1, [X2, #496]

      (333) 0x41a428 LDP	D2, D3, [X1, #1008]

      (333) 0x41a42c SUBS	X0, X0, #4

      (333) 0x41a430 FMSUB	D0, D1, D0, D2

      (333) 0x41a434 STUR	D0, [X1, #496]

      (333) 0x41a438 LDUR	D0, [X3, #504]

      (333) 0x41a43c LDUR	D1, [X2, #504]

      (333) 0x41a440 FMSUB	D0, D1, D0, D3

      (333) 0x41a444 LDP	D2, D3, [X1]

      (333) 0x41a448 STUR	D0, [X1, #504]

      (333) 0x41a44c LDR	D0, [X3]

      (333) 0x41a450 LDR	D1, [X2]

      (333) 0x41a454 FMSUB	D0, D1, D0, D2

      (333) 0x41a458 STR	D0, [X1]

      (333) 0x41a45c LDR	D0, [X3, #8]

      (333) 0x41a460 LDR	D1, [X2, #8]

      (333) 0x41a464 ADD	X2, X2, #32

      (333) 0x41a468 ADD	X3, X3, #32

      (333) 0x41a46c FMSUB	D0, D1, D0, D3

      (333) 0x41a470 STR	D0, [X1, #8]

      (333) 0x41a474 ADD	X1, X1, #32

      (333) 0x41a478 B.NE	41a420

    (324) 0x41a47c B	41a520

    (324) 0x41a480 ADD	X3, X17, X9

    (324) 0x41a484 ADD	X5, X24, X18

    (324) 0x41a488 ORR	X2, XZR, XZR

    (324) 0x41a48c ADD	X4, X13, X3,LSL #3

    (324) 0x41a490 ADD	X3, X12, X9

    (324) 0x41a494 ADD	X3, X11, X3,LSL #3

    (324) 0x41a498 CMP	X0, X3

    (324) 0x41a49c CCMP	X1, X4, #2, #3

    (324) 0x41a4a0 CSINC	W3, WZR, WZR, #2

    (324) 0x41a4a4 CMP	X24, X4

    (324) 0x41a4a8 CCMP	X0, X5, #2, #3

    (324) 0x41a4ac B.CC	41a3b4

    (324) 0x41a4b0 TBNZ	W3, #0, 41a3b4

    (324) 0x41a4b4 ADD	X4, X13, X17,LSL #3

    (324) 0x41a4b8 ADD	X5, X11, X12,LSL #3

    (324) 0x41a4bc AND	X2, X9, #6014

    (324) 0x41a4c0 ADD	X3, X24, #16

    (324) 0x41a4c4 ORR	X6, XZR, X10

    (324) 0x41a4c8 ADD	X4, X4, #16

    (324) 0x41a4cc ADD	X5, X5, #16

    (324) 0x41a4d0 HINT	#0

    (324) 0x41a4d4 HINT	#0

    (324) 0x41a4d8 HINT	#0

    (324) 0x41a4dc HINT	#0

      (335) 0x41a4e0 LDP	Q0, Q1, [X3, #2032]

      (335) 0x41a4e4 LDP	Q2, Q3, [X5, #2032]

      (335) 0x41a4e8 SUBS	X6, X6, #4

      (335) 0x41a4ec ADD	X3, X3, #32

      (335) 0x41a4f0 ADD	X5, X5, #32

      (335) 0x41a4f4 LDP	Q4, Q5, [X4, #2032]

      (335) 0x41a4f8 FMLS	V5.2D, V3.2D, V1.2D

      (335) 0x41a4fc FMLS	V4.2D, V2.2D, V0.2D

      (335) 0x41a500 STP	Q4, Q5, [X4, #2032]

      (335) 0x41a504 ADD	X4, X4, #32

      (335) 0x41a508 B.NE	41a4e0

    (324) 0x41a50c MOVZ	W6, #40

    (324) 0x41a510 CMP	X2, X9

    (324) 0x41a514 B.NE	41a3b4

    (324) 0x41a518 HINT	#0

    (324) 0x41a51c HINT	#0

    (324) 0x41a520 ADD	X0, X13, X17,LSL #4

    (324) 0x41a524 UBFM	X17, X12, #60, #59

    (324) 0x41a528 ADD	X12, X11, X12,LSL #4

    (324) 0x41a52c CMP	W9, #4

    (324) 0x41a530 B.CS	41a600

    (324) 0x41a534 ORR	X1, XZR, XZR

    (324) 0x41a538 ORR	X18, XZR, X1

    (324) 0x41a53c ANDS	XZR, X15, #4160

    (324) 0x41a540 B.EQ	41a568

    (324) 0x41a544 ORR	X18, XZR, X1

      (331) 0x41a548 LDR	D0, [X24, X18,LSL #3]

      (331) 0x41a54c LDR	D1, [X12, X18,LSL #3]

      (331) 0x41a550 LDR	D2, [X0, X18,LSL #3]

      (331) 0x41a554 SUBS	X16, X16, #1

      (331) 0x41a558 FMSUB	D0, D1, D0, D2

      (331) 0x41a55c STR	D0, [X0, X18,LSL #3]

      (331) 0x41a560 ADD	X18, X18, #1

      (331) 0x41a564 B.NE	41a548

    (324) 0x41a568 SUB	X9, X1, X15

    (324) 0x41a56c CMN	X9, #4

    (324) 0x41a570 B.HI	419b80

    (324) 0x41a574 ADD	X10, X14, X18,LSL #3

    (324) 0x41a578 ADD	X12, X17, X18,LSL #3

    (324) 0x41a57c SUB	X9, X8, X18

    (324) 0x41a580 ADD	X10, X13, X10

    (324) 0x41a584 ADD	X11, X11, X12

    (324) 0x41a588 ADD	X12, X24, X18,LSL #3

    (324) 0x41a58c ADD	X10, X10, #16

    (324) 0x41a590 ADD	X11, X11, #16

    (324) 0x41a594 ADD	X12, X12, #16

    (324) 0x41a598 HINT	#0

    (324) 0x41a59c HINT	#0

      (330) 0x41a5a0 LDUR	D0, [X12, #496]

      (330) 0x41a5a4 LDUR	D1, [X11, #496]

      (330) 0x41a5a8 LDP	D2, D3, [X10, #1008]

      (330) 0x41a5ac SUBS	X9, X9, #4

      (330) 0x41a5b0 FMSUB	D0, D1, D0, D2

      (330) 0x41a5b4 STUR	D0, [X10, #496]

      (330) 0x41a5b8 LDUR	D0, [X12, #504]

      (330) 0x41a5bc LDUR	D1, [X11, #504]

      (330) 0x41a5c0 FMSUB	D0, D1, D0, D3

      (330) 0x41a5c4 LDP	D2, D3, [X10]

      (330) 0x41a5c8 STUR	D0, [X10, #504]

      (330) 0x41a5cc LDR	D0, [X12]

      (330) 0x41a5d0 LDR	D1, [X11]

      (330) 0x41a5d4 FMSUB	D0, D1, D0, D2

      (330) 0x41a5d8 STR	D0, [X10]

      (330) 0x41a5dc LDR	D0, [X12, #8]

      (330) 0x41a5e0 LDR	D1, [X11, #8]

      (330) 0x41a5e4 ADD	X11, X11, #32

      (330) 0x41a5e8 ADD	X12, X12, #32

      (330) 0x41a5ec FMSUB	D0, D1, D0, D3

      (330) 0x41a5f0 STR	D0, [X10, #8]

      (330) 0x41a5f4 ADD	X10, X10, #32

      (330) 0x41a5f8 B.NE	41a5a0

    (324) 0x41a5fc B	419b80

    (324) 0x41a600 ADD	X2, X13, X14

    (324) 0x41a604 ADD	X3, X24, X18

    (324) 0x41a608 ORR	X1, XZR, XZR

    (324) 0x41a60c ADD	X2, X2, X18

    (324) 0x41a610 ADD	X18, X17, X18

    (324) 0x41a614 ADD	X18, X11, X18

    (324) 0x41a618 CMP	X0, X18

    (324) 0x41a61c CCMP	X12, X2, #2, #3

    (324) 0x41a620 CSINC	W18, WZR, WZR, #2

    (324) 0x41a624 CMP	X24, X2

    (324) 0x41a628 CCMP	X0, X3, #2, #3

    (324) 0x41a62c B.CC	41a538

    (324) 0x41a630 TBNZ	W18, #0, 41a538

    (324) 0x41a634 ADD	X2, X13, X14

    (324) 0x41a638 ADD	X3, X11, X17

    (324) 0x41a63c AND	X1, X9, #6014

    (324) 0x41a640 ADD	X18, X24, #16

    (324) 0x41a644 ADD	X2, X2, #16

    (324) 0x41a648 ADD	X3, X3, #16

      (332) 0x41a64c LDP	Q0, Q1, [X18, #2032]

      (332) 0x41a650 LDP	Q2, Q3, [X3, #2032]

      (332) 0x41a654 SUBS	X10, X10, #4

      (332) 0x41a658 ADD	X18, X18, #32

      (332) 0x41a65c ADD	X3, X3, #32

      (332) 0x41a660 LDP	Q4, Q5, [X2, #2032]

      (332) 0x41a664 FMLS	V5.2D, V3.2D, V1.2D

      (332) 0x41a668 FMLS	V4.2D, V2.2D, V0.2D

      (332) 0x41a66c STP	Q4, Q5, [X2, #2032]

      (332) 0x41a670 ADD	X2, X2, #32

      (332) 0x41a674 B.NE	41a64c

    (324) 0x41a678 CMP	X1, X9

    (324) 0x41a67c B.EQ	419b80

    (324) 0x41a680 B	41a538

    (324) 0x41a684 LDR	X21, [SP, #32]

    (324) 0x41a688 MOVZ	W6, #40

    (324) 0x41a68c B	41a05c

0x41a690 LDR	D8, [SP, #96]

0x41a694 LDP	X20, X19, [SP, #192]

0x41a698 LDP	X22, X21, [SP, #176]

0x41a69c LDP	X24, X23, [SP, #160]

0x41a6a0 LDP	X26, X25, [SP, #144]

0x41a6a4 LDP	X28, X27, [SP, #128]

0x41a6a8 LDP	X29, X30, [SP, #112]

0x41a6ac ADD	SP, SP, #208

0x41a6b0 RET

0x41a6b4 HINT	#0

0x41a6b8 HINT	#0

0x41a6bc HINT	#0

Coverage (%)	Name	Source Location	Module
►100.00+	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:421	exec
○	miniqmcreference::TwoBodyJastr[...]	TwoBodyJastrowRef.h:411	exec
○	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:175	exec
○	main.omp_outlined	miniqmc.cpp:379	exec
○	__kmp_invoke_microtask		libomp.so

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

min	med	avg	max

Percentile Index	10	20	30	40	50	60	70	80	90	100
Value

Path /

Average path: Display a virtual path defined by average values of all real paths

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	TwoBodyJastrowRef.h:268-402
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_numeric.h:140-141
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/shared_ptr_base.h:1667
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:952,1146
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_iterator.h:1068
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:268-274,359-367,375-391,397-402
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131,1150,1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263,271-273

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.33 to 0.83 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Your function is not vectorized. Only 69% of vector register length is used (average across all VPU instructions). By vectorizing your function, you can lower the cost of an iteration from 6.33 to 5.25 cycles (1.21x speedup).

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.33 to 0.50 cycles (12.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Overall L1	6.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.33 cycles. At this rate:

19% of peak load performance is reached (18.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 419aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W1, [X0, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4471f0 <_ZNK11qmcplusplus11ParticleSet14getDistTableAAEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X28, 41a690 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0xbf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D8, #-2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W6, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X28, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X19, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 419b1c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

The code analyzed by CQA in that panel excludes loops and represents 0.00% of application time for run orig_0

Source file and lines	TwoBodyJastrowRef.h:268-402
Module	exec

The function is defined in:

/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_numeric.h:140-141
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/shared_ptr_base.h:1667
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_algobase.h:952,1146
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_iterator.h:1068
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/OhmmsVector.h:223,229,249
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/QMCWaveFunctions/Jastrow/TwoBodyJastrowRef.h:268-274,359-367,375-391,397-402
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Particle/ParticleSet.h:313
/opt/arm/gcc-14.2.0_AmazonLinux-2023/lib/gcc/aarch64-linux-gnu/14.2.0/../../../../include/c++/14.2.0/bits/stl_vector.h:1131,1150,1263
/home/hbollore/qaas/qaas-runs/174-135-6342/intel/miniqmc/build/miniqmc/src/Numerics/OhmmsPETE/VectorSoAContainer.h:244,263,271-273

Warnings:
Ignoring paths for analysis

gain
potential
hint
expert

Code clean check

Detected a slowdown caused by scalar integer instructions (typically used for address computation). By removing them, you can lower the cost of an iteration from 6.33 to 0.83 cycles (7.60x speedup).

Workaround

Try to reorganize arrays of structures to structures of arrays
Consider to permute loops (see vectorization gain report)

Vectorization

Details

All VPU instructions are used in scalar version (process only one data element in vector registers). Since your execution units are vector units, only a vectorized function can use their full power.

Workaround

Try another compiler or update/tune your current one
Make array accesses unit-stride:
- If your function streams arrays of structures (AoS), try to use structures of arrays instead (SoA): for(i) a[i].x = b[i].x; (slow, non stride 1) => for(i) a.x[i] = b.x[i]; (fast, stride 1)

Expensive FP math instructions/calls

Detected performance impact from expensive FP math instructions/calls. By removing/reexpressing them, you can lower the cost of an iteration from 6.33 to 0.50 cycles (12.67x speedup).

Matching between your function (in the source code) and the binary function

The binary function does not contain any FP arithmetical operations. The binary function is loading 116 bytes. The binary function is storing 128 bytes.

General properties

nb instructions	49
loop length	196
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.25 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16
uops	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50
cycles	2.00	2.00	1.83	1.83	1.83	1.83	1.83	1.83	0.50	0.50	0.50	0.50	6.33	6.33	6.33	4.50	4.50

Execution ports to units layout:

P0: BRU
P1: BRU
P2: ALU
P3: ALU
P4: ALU
P5: ALU
P6: ALU
P7: ALU
P8 (128 bits): VPU, FP store data, ALU, DIV/SQRT
P9 (128 bits): VPU, ALU, FP store data
P10 (128 bits): VPU, ALU, DIV/SQRT
P11 (128 bits): ALU, VPU
P12 (256 bits): store address, load
P13 (256 bits): store address, load
P14 (256 bits): load
P15 (64 bits): store data
P16 (64 bits): store data

Cycles executing div or sqrt instructions

Cycles summary

Front-end	4.25
Overall L1	6.33

Vectorization ratios

INT

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
other	0%

all	0%
load	NA (no load vectorizable/vectorized instructions)
store	NA (no store vectorizable/vectorized instructions)
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

INT+FP

all	0%
load	0%
store	0%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	0%

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each call to the function takes 6.33 cycles. At this rate:

19% of peak load performance is reached (18.32 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
42% of peak store performance is reached (20.21 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the function is: 419aa0

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14	P15	P16	Latency	Recip. throughput	Vectorization
SUB SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
STR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	0	0	2	0.50	scal (50.0%)
STP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
STP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (100.0%)
ADD X29, SP, #112	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X19, XZR, X1	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
LDR W1, [X0, #584]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (25.0%)
ORR X20, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
ORR X0, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
BL 4471f0 <_ZNK11qmcplusplus11ParticleSet14getDistTableAAEi>	1	0.50	0.50	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
LDR X28, [X20, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.33	scal (50.0%)
CBZ X28, 41a690 <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0xbf0>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
FMOV D8, #-2.0000000	1	0	0	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	2	0.25	scal (50.0%)
MOVZ W6, #40	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (25.0%)
ORR X30, XZR, X19	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X21, XZR, X0	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
ORR X9, XZR, XZR	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	scal (50.0%)
STUR X28, [X29, #464]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STR X0, [SP, #32]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
STUR X19, [X29, #504]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.50	0.50	0	0.50	0.50	1	0.50	scal (50.0%)
B 419b1c <_ZN16miniqmcreference17TwoBodyJastrowRefIN11qmcplusplus14BsplineFunctorIdEEE9recomputeERNS1_11ParticleSetE+0x7c>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A
LDR D8, [SP, #96]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	6	0.33	scal (50.0%)
LDP X20, X19, [SP, #192]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
LDP X22, X21, [SP, #176]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X24, X23, [SP, #160]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X26, X25, [SP, #144]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X28, X27, [SP, #128]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	scal (100.0%)
LDP X29, X30, [SP, #112]	1	0	0	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	0	0	4	0.50	N/A
ADD SP, SP, #208	1	0	0	0.17	0.17	0.17	0.17	0.17	0.17	0	0	0	0	0	0	0	0	0	1	0.17	N/A
RET	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0.50	N/A
HINT #0																					N/A
HINT #0																					N/A
HINT #0																					N/A

Name	Coverage (%)	Time (s)
▼miniqmcreference::TwoBodyJastrowRef >::recompute(qmcplusplus::ParticleSet&)–	0.09	0.12
▼Loop 325 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
○Loop 321 - TwoBodyJastrowRef.h:375-376 - exec	0.01	0.01
▼Loop 327 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.00
○Loop 341 - TwoBodyJastrowRef.h:381-382 - exec	0.02	0.02
○Loop 342 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.02
○Loop 343 - TwoBodyJastrowRef.h:381-382 - exec	0.01	0.02
▼Loop 324 - TwoBodyJastrowRef.h:268-398 - exec–	0.00	0.01
○Loop 340 - TwoBodyJastrowRef.h:388-391 - exec	0.02	0.02
○Loop 338 - TwoBodyJastrowRef.h:397-398 - exec	0.01	0.01
○Loop 335 - TwoBodyJastrowRef.h:397-398 - exec	0.01	0.01
○Loop 332 - TwoBodyJastrowRef.h:397-398 - exec	0.01	0.01
○Loop 328 - stl_numeric.h:141-141 - exec	0.00	0.01
○Loop 329 - TwoBodyJastrowRef.h:269-274 - exec	0.00	0.00
○Loop 323 - stl_numeric.h:140-141 - exec	0.00	0.00
○Loop 334 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 330 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 333 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 339 - TwoBodyJastrowRef.h:388-391 - exec	0.00	0.00
○Loop 322 - TwoBodyJastrowRef.h:361-364 - exec	0.00	0.00
○Loop 336 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 331 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 337 - TwoBodyJastrowRef.h:397-398 - exec	0.00	0.00
○Loop 345 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 344 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00
○Loop 326 - TwoBodyJastrowRef.h:375-376 - exec	0.00	0.00
○Loop 346 - TwoBodyJastrowRef.h:381-382 - exec	0.00	0.00

Report Configuration

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Code clean check

Workaround

Vectorization

Details

Workaround

Expensive FP math instructions/calls

Matching between your function (in the source code) and the binary function

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code