OV - exec - Loop 926

0x451fb4 LDR	D25, [X1, X17,LSL #3]    [1]

0x451fb8 ADD	X30, X17, #1

0x451fbc ADD	X12, X17, #2

0x451fc0 ADD	X11, X17, #3

0x451fc4 ADD	X17, X17, #4

0x451fc8 LDP	D28, D29, [X18, #8]    [7]

0x451fcc LDR	D26, [X1, X30,LSL #3]    [3]

0x451fd0 LDP	D30, D31, [X18, #32]    [7]

0x451fd4 FMADD	D2, D28, D25, D23

0x451fd8 FMADD	D0, D25, D29, D24

0x451fdc LDR	D27, [X1, X12,LSL #3]    [5]

0x451fe0 LDP	D1, D16, [X18, #56]    [7]

0x451fe4 LDR	D6, [X18]    [7]

0x451fe8 FMADD	D4, D30, D26, D2

0x451fec FMADD	D3, D26, D31, D0

0x451ff0 LDR	D7, [X1, X11,LSL #3]    [4]

0x451ff4 LDP	D22, D23, [X18, #72]    [7]

0x451ff8 ADD	X18, X18, #96

0x451ffc LDUR	D24, [X18, #504]    [6]

0x452000 FMADD	D19, D1, D27, D4

0x452004 FMADD	D20, D27, D16, D3

0x452008 FMADD	D21, D6, D25, D5

0x45200c LDUR	D17, [X18, #440]    [6]

0x452010 LDUR	D25, [X18, #464]    [6]

0x452014 FMADD	D23, D23, D7, D19

0x452018 FMADD	D24, D7, D24, D20

0x45201c FMADD	D5, D17, D26, D21

0x452020 FMADD	D26, D25, D27, D5

0x452024 STP	D23, D24, [SP, #56]    [2]

0x452028 FMADD	D5, D22, D7, D26

0x45202c CMP	W4, W17

0x452030 B.GT	451fb4

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h: 63 - 94

--------------------------------------------------------------------------------

63:     return (a * b);

[...]

94:     (const_cast<T1&>(a) += b);

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp: 154 - 154

--------------------------------------------------------------------------------

154:   for (int i = 0; i < n; i++)

Coverage (%)	Name	Source Location	Module
►66.67+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec
►33.33+	qmcplusplus::WaveFunction::eva[...]	WaveFunction.cpp:177	exec
○	main._omp_fn.0	miniqmc.cpp:390	exec
○	GOMP_parallel		libomp.so
○	main	stl_vector.h:1043	exec
○	__libc_start_main		libc-2.31.so
○	_start	miniqmc.cpp:546	exec

Path /

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.46
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source	OperatorTags.h:63-63,OperatorTags.h:94-94,inner_product.hpp:154-154
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.31
Front-end cycles	4.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	4.50
P10 cycles	4.17
P11 cycles	4.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.46
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	34.62
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Metric	Value
CQA speedup if no scalar integer	1.00
CQA speedup if FP arith vectorized	1.00
CQA speedup if fully vectorized	3.46
CQA speedup if no inter-iteration dependency	NA
CQA speedup if next bottleneck killed	1.78
Bottlenecks
Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source	OperatorTags.h:63-63,OperatorTags.h:94-94,inner_product.hpp:154-154
Source loop unroll info	unrolled by 3
Source loop unroll confidence level	high
Unroll/vectorization loop type	NA
Unroll factor	1
CQA cycles	8.00
CQA cycles if no scalar integer	8.00
CQA cycles if FP arith vectorized	8.00
CQA cycles if fully vectorized	2.31
Front-end cycles	4.00
DIV/SQRT cycles	0.50
P0 cycles	0.50
P1 cycles	1.50
P2 cycles	1.50
P3 cycles	1.50
P4 cycles	1.50
P5 cycles	3.25
P6 cycles	3.25
P7 cycles	3.25
P8 cycles	3.25
P9 cycles	4.50
P10 cycles	4.17
P11 cycles	4.33
P12 cycles	0.00
P13 cycles	0.00
P14 cycles	0.00
Inter-iter dependencies cycles	8
FE+BE cycles (UFS)	NA
Stall cycles (UFS)	NA
Nb insns	32.00
Nb uops	32.00
Nb loads	NA
Nb stores	1.00
Nb stack references	0.00
FLOP/cycle	3.00
Nb FLOP add-sub	0.00
Nb FLOP mul	0.00
Nb FLOP fma	12.00
Nb FLOP div	0.00
Nb FLOP rcp	0.00
Nb FLOP sqrt	0.00
Nb FLOP rsqrt	0.00
Bytes/cycle	18.00
Bytes prefetched	0.00
Bytes loaded	128.00
Bytes stored	16.00
Stride 0	NA
Stride 1	NA
Stride n	NA
Stride unknown	NA
Stride indirect	NA
Vectorization ratio all	38.46
Vectorization ratio load	33.33
Vectorization ratio store	100.00
Vectorization ratio mul	NA
Vectorization ratio add_sub	NA
Vectorization ratio fma	NA
Vectorization ratio div_sqrt	NA
Vectorization ratio other	NA
Vector-efficiency ratio all	34.62
Vector-efficiency ratio load	33.33
Vector-efficiency ratio store	50.00
Vector-efficiency ratio mul	NA
Vector-efficiency ratio add_sub	NA
Vector-efficiency ratio fma	NA
Vector-efficiency ratio div_sqrt	NA
Vector-efficiency ratio other	NA

Path /

Average path: Display a virtual path defined by average values of all real paths

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154

The related source loop is unrolled by 3 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is poorly vectorized. Only 34% of vector register length is used (average across all VPU instructions).

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	4.50	4.17	4.33	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	4.50	4.17	4.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	38%
load	33%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451fb4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D25, [X1, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X30, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D28, D29, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D26, [X1, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D30, D31, [X18, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D2, D28, D25, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D0, D25, D29, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D27, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D1, D16, [X18, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D4, D30, D26, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D26, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [X1, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D22, D23, [X18, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X18, X18, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D24, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D1, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D20, D27, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D21, D6, D25, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D17, [X18, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D25, [X18, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D23, D23, D7, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D24, D7, D24, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D5, D17, D26, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D26, D25, D27, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D23, D24, [SP, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D5, D22, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W4, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 451fb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Function	miniqmcreference::DiracDeterminantRef >::evaluateLog(qmcplusplus::ParticleSet&, qmcplusplus::ParticleAttrib, std::allocator > >&, qmcplusplus::ParticleAttrib >&)
Source file and lines	inner_product.hpp:154-154
Module	exec

The loop is defined in:

/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Numerics/PETE/OperatorTags.h:63,94
/home/hbollore/qaas/qaas-runs/169-816-8620/intel/miniqmc/build/miniqmc/src/Platforms/CPU/SIMD/inner_product.hpp:154

The related source loop is unrolled by 3 (including vectorization).

gain
potential
hint
expert

Unrolling/vectorization cost

This loop is peel/tail of a unrolled/vectorized loop. If its cost is not negligible compared to the main (unrolled/vectorized) loop, unrolling/vectorization is counterproductive due to low trip count.

Details

The more iterations the main loop is processing, the higher the trip count must be to amortize peel/tail overhead.

Workaround

recompile with -fprofile-generate, execute and recompile with -fprofile-use (profile-guided optimization)
hardcode most frequent values of loop bounds by adding specialized paths.:
- For instance, replace for (i=0; i<n; i++) foo(i) with: switch (n) { case (4): for (i=0; i<4; i++) foo(i); break; case (6): for (i=0; i<6; i++) foo(i); break; default : for (i=0; i<n; i++) foo(i); break; }

Vectorization

Your loop is poorly vectorized. Only 34% of vector register length is used (average across all VPU instructions).

Details

38% of VPU instructions are used in vector version (process two or more data elements in vector registers):

33% of VPU loads are used in vector version.

FMA

Detected 12 FMA (fused multiply-add) operations.

Matching between your loop (in the source code) and the binary loop

The binary loop is composed of 24 FP arithmetical operations:

12: addition or subtraction (all inside FMA instructions)
12: multiply (all inside FMA instructions)

The binary loop is loading 128 bytes. The binary loop is storing 16 bytes.

Arithmetic intensity

Arithmetic intensity is 0.17 FP operations per loaded or stored byte.

General properties

nb instructions	32
loop length	128
nb stack references	0

Front-end

FIT IN UOP CACHE

front end

4.00 cycles

Back-end

	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	P13	P14
uops	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	4.50	4.17	4.33	0.00	0.00
cycles	0.50	0.50	1.50	1.50	1.50	1.50	3.25	3.25	3.25	3.25	4.50	4.17	4.33	0.00	0.00

Cycles executing div or sqrt instructions	NA
Longest recurrence chain latency (RecMII)	8.00

Cycles summary

Front-end	4.00
Data deps.	8.00
Overall L1	8.00

Vectorization ratios

all	38%
load	33%
store	100%
mul	NA (no mul vectorizable/vectorized instructions)
add-sub	NA (no add-sub vectorizable/vectorized instructions)
fma	NA (no fma vectorizable/vectorized instructions)
div/sqrt	NA (no div/sqrt vectorizable/vectorized instructions)
other	NA (no other vectorizable/vectorized instructions)

Cycles and memory resources usage

Assuming all data fit into the L1 cache, each iteration of the binary loop takes 8.00 cycles. At this rate:

16% of peak load performance is reached (16.00 out of 96.00 bytes loaded per cycle (GB/s @ 1GHz))
4% of peak store performance is reached (2.00 out of 48.00 bytes stored per cycle (GB/s @ 1GHz))

ASM code

In the binary file, the address of the loop is: 451fb4

Instruction	Nb FU	P0	P1	P2	P3	P4	P5	P6	P7	P8	P9	P10	P11	P12	Latency	Recip. throughput
LDR D25, [X1, X17,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X30, X17, #1	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X12, X17, #2	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X11, X17, #3	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
ADD X17, X17, #4	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDP D28, D29, [X18, #8]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D26, [X1, X30,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D30, D31, [X18, #32]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D2, D28, D25, D23	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D0, D25, D29, D24	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D27, [X1, X12,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D1, D16, [X18, #56]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDR D6, [X18]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D4, D30, D26, D2	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D3, D26, D31, D0	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDR D7, [X1, X11,LSL #3]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDP D22, D23, [X18, #72]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
ADD X18, X18, #96	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.25
LDUR D24, [X18, #504]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D19, D1, D27, D4	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D20, D27, D16, D3	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D21, D6, D25, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
LDUR D17, [X18, #440]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
LDUR D25, [X18, #464]	1	0	0	0	0	0	0	0	0	0	0	0.33	0.33	0.33	6	0.33
FMADD D23, D23, D7, D19	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D24, D7, D24, D20	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D5, D17, D26, D21	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
FMADD D26, D25, D27, D5	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
STP D23, D24, [SP, #56]	1	0	0	0	0	0	0	0.50	0.50	0	0	0.50	0.50	0	2	0.50
FMADD D5, D22, D7, D26	1	0	0	0	0	0	0	0.25	0.25	0.25	0.25	0	0	0	4	0.25
CMP W4, W17	1	0	0	0.25	0.25	0.25	0.25	0	0	0	0	0	0	0	1	0.33
B.GT 451fb4 <_ZN16miniqmcreference19DiracDeterminantRefIN11qmcplusplus13DelayedUpdateIddEEE11evaluateLogERNS1_11ParticleSetERNS1_14ParticleAttribINS1_10TinyVectorIdLj3EEESaIS9_EEERNS7_IdSaIdEEE+0x134>	1	0.50	0.50	0	0	0	0	0	0	0	0	0	0	0	1	0.50

Report Configuration

Unrolling/vectorization cost

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Workaround

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code

Unrolling/vectorization cost

Details

Workaround

Vectorization

Details

FMA

Matching between your loop (in the source code) and the binary loop

Arithmetic intensity

General properties

Front-end

Back-end

Cycles summary

Vectorization ratios

Cycles and memory resources usage

ASM code